On Mon, Feb 09, 2009 at 09:56:43PM -0500, Ben Perry wrote:
> So I am using higher-level interfaces to write to these registers.
> Namely I am concerned with writing to the output enable register for
> RxA. From my understanding of what I have to do I set up my source_c
> and then I am able to write
So I am using higher-level interfaces to write to these registers.
Namely I am concerned with writing to the output enable register for
RxA. From my understanding of what I have to do I set up my source_c
and then I am able to write_oe/io with a value to either 0 for a? and
1 for b?. My code is bel
On Mon, Feb 09, 2009 at 01:06:36AM -0500, Ben Perry wrote:
> I am trying to write to an IO register on my FPGA to open the lines of
> communication. Right now I am just using benchmark_tx.py as my test
> case.
>
> In transmit_path.py I added the following
>
> self.u._write_fpga_reg(usrp.FR_OE_1,4
I am trying to write to an IO register on my FPGA to open the lines of
communication. Right now I am just using benchmark_tx.py as my test
case.
In transmit_path.py I added the following
self.u._write_fpga_reg(usrp.FR_OE_1,4227922944)
self.u._write_fpga_reg(usrp.FR_IO_1,4227922944)
I based this
