Hi Lance,
On 12/14/06, seph 004 <[EMAIL PROTECTED]> wrote:
Hi
It seems the more I read through the fpga code, the more confused I get.
There are a few things I'm unsure about:
In the fpga DDC, are I and Q samples being generated from complex samples?
The adc_interface module just seems to mul
Hi
It seems the more I read through the fpga code, the more confused I get. There
are a few things I'm unsure about:
In the fpga DDC, are I and Q samples being generated from complex samples? The
adc_interface module just seems to multiplex the same complex sample on to 2
lines. It would seem
