On Thursday, April 10, 2014 04:13:23 PM Matthew Garrett wrote:
> The list of machines in the "Use native backlight" table is getting longer
> and longer, which is a solid indication that we're doing something wrong.
> Disable the ACPI backlight interface if the system claims to be Windows 8
> or
This patch adds common part of dsi node.
Changelog v2:
- Uses clock macros instead of numbers (commented by Sachin Kamat)
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
arch/arm/boot/dts/exynos5420.dtsi | 15 +++
1 file changed, 15 insertions(+)
This patch adds mipi-phy node for MIPI-DSI device.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
arch/arm/boot/dts/exynos5420.dtsi |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
This patch adds sysreg device node, and sysreg property to fimd device node
which is required to use I80 interface.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
arch/arm/boot/dts/exynos5.dtsi |6 ++
1 file changed, 6 insertions(+)
diff --git
This patch adds sysreg property to fimd device node which is required
to use I80 interface.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
arch/arm/boot/dts/exynos4.dtsi |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/exynos4.dtsi
This patch adds MIPI-DSI command mode based S6E3FA0 AMOLED LCD Panel driver.
Changelog v2:
- Declares delay, size properties in probe routine instead of DT
Changelog v3:
- Moves CPU timings relevant properties from FIMD DT
(commented by Laurent Pinchart, Andrzej Hajda)
Signed-off-by: YoungJun
This patch adds DT bindings for s6e3fa0 panel.
The bindings describes panel resources, display timings and cpu timings.
Changelog v2:
- Adds unit address (commented by Sachin Kamat)
Changelog v3:
- Removes optional delay, size properties (commented by Laurent Pinchart)
- Adds OLED detection, TE
The offset of register DSIM_PLLTMR_REG in Exynos5420 is different
from the one in Exynos4 SoC.
In case of Exynos5420 SoC, there is no frequency band bit in DSIM_PLLCTRL_REG,
and it uses DSIM_PHYCTRL_REG and DSIM_PHYTIMING*_REG instead.
So this patch adds driver data to distinguish it.
This patch adds relevant to exynos5420 compatible for exynos5420 SoC support.
Changelog v2:
- Changes title, description and fixes typo (commented by Sachin Kamat)
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
.../devicetree/bindings/video/exynos_dsim.txt |
This patch adds I80 interface for FIMD to support command mode panel.
For this, the below features are added:
- Sets display interface mode relevant registers properly according to the
interface type from DT
- Adds drm_panel_cpu_timings structure
. The command mode panel sets them as the
In case of using CPU interface panel, the relevant registers should be set.
So this patch adds relevant dt bindings.
Changelog v2:
- Changes "samsung,sysreg-phandle" to "samsung,sysreg"
Changelog v3:
- Moves CPU timings relevant properties to panel DT
(commented by Laurent Pinchart, Andrzej
This patch adds relevant to exynos5 compatible for exynos5 SoCs.
Changelog v2:
- Changes title and description (commented by Sachin Kamat)
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
.../devicetree/bindings/arm/samsung/sysreg.txt |1 +
1 file changed, 1
There could be the case that the page flip operation isn't finished correctly
with some abnormal condition such as panel reset. So this patch replaces
wait_event() with wait_event_timeout() to avoid waiting for page flip completion
infinitely.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Some phy control registers are not kept after software reset.
So this patch makes the clocks containing phy control to be set
after software reset.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c |2 +-
1 file changed, 1
This configuration could be used in MIPI DSI command mode also.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
This patch series includes the followings:
- FIMD I80 interface
- DSI command mode interface for Exynos5420 SoC
- S6E3FA0 command mode type panel driver
- Some bugs modification
The patch series is based on exynos-drm-next branch.
Previous patch set,
RFC v1:
ttp://lists.freedesktop.org/archives/dri-devel/attachments/20140421/13bef5a1/attachment.html>
he bug.
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On Monday 21 April 2014 15:08:24 Ed Tomlinson wrote:
> On Monday 21 April 2014 10:25:25 Ed Tomlinson wrote:
> > On Saturday 19 April 2014 21:03:05 Markus Trippelsdorf wrote:
> > > On 2014.04.19 at 08:19 +0100, Dave Airlie wrote:
> > > >
> > > > Unfortunately this contains no easter eggs, its a
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On Monday 21 April 2014 10:25:25 Ed Tomlinson wrote:
> On Saturday 19 April 2014 21:03:05 Markus Trippelsdorf wrote:
> > On 2014.04.19 at 08:19 +0100, Dave Airlie wrote:
> > >
> > > Unfortunately this contains no easter eggs, its a bit larger than I'd
> > > like, but I included a patch that just
Set the correct subdev/engine classes when GK20A (0xea) is probed.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/device/nve0.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
Skip the creation of a software channel for GK20A as software methods
are not yet supported.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/nouveau_drm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c
Add a GR device for GK20A based on NVE4, with the correct classes
definitions (GK20A's 3D class is 0xa297).
Most of the NVE4 code can be used on GK20A, so make relevant bits of
NVE4 available to other chips as well.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile
Pad the microcode to a multiple of 0x40 bytes, otherwise firmware will
fail to run from non-prepadded firmware files.
Signed-off-by: Alexandre Courbot
Reviewed-by: Thierry Reding
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 4
1 file changed, 4 insertions(+)
diff --git
nvc0_graph_ctor() would only let the graphics engine be enabled if its
oclass has a proper microcode linked to it. This prevents GR from being
enabled at all on chips that rely exclusively on external firmware, even
though such a use-case is valid.
Relax the conditions enabling the GR engine to
GK20A's FIFO is compatible with NVE0, but only features 128 channels and
1 runlist.
Signed-off-by: Alexandre Courbot
Reviewed-by: Thierry Reding
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/engine/fifo/gk20a.c | 35 ++
Add a simple FB device for GK20A, as well as a RAM implementation based
on contiguous DMA memory allocations suitable for chips that use system
memory as video RAM.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 2 +
Add support for initializing the priv ring of GK20A. This is done by the
BIOS on desktop GPUs, but needs to be done by hand on Tegra.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/include/subdev/ibus.h | 1 +
Adapt the NVC0 BAR driver to make it able to support chips that do not
expose a BAR3. When this happens, BAR1 is then used for USERD mapping
and the BAR alloc() functions is disabled, making GPU objects unable
to rely on BAR for data access and falling back to PRAMIN.
Signed-off-by: Alexandre
Some chips that use system memory exclusively (e.g. GK20A) do not
expose 2 BAR regions. For them only BAR1 exists, and it should be used
for USERD mapping. Do not map BAR3 if its resource does not exist.
Signed-off-by: Alexandre Courbot
Reviewed-by: Thierry Reding
---
Hi everyone,
Way overdue v2 of the final patches that enable basic GK20A support. Hopefully
all the issues raised with v1 have been addressed.
Changes since v1:
- Use gk20a clock driver by Ben instead of twiddling nv04's
- Name new classes after gk20a instead of nvea
- Addressed comments about
On Wed, 2 Apr 2014, Ross Zwisler wrote:
> With this commit:
>
> 2a0788dc9bc4 x86: Use clflushopt in drm_clflush_virt_range
>
> If clflushopt is available on the system, we use it instead of clflush
> in drm_clflush_virt_range. There were two calls to clflush in this
> function, but only one was
On Mon, Apr 21, 2014 at 2:02 AM, Alexandre Courbot
wrote:
> Skip the creation of a software channel for GK20A as software methods
> are not yet supported.
How is GK20A different from a nvc0+ card that lacks PDISPLAY (like all
the 3D Controller ones, and I guess even some that come up as VGA
On Mon, Apr 21, 2014 at 2:02 AM, Alexandre Courbot
wrote:
> Pad the microcode to a multiple of 0x40 bytes, otherwise firmware will
bytes or u32's? From the code, I'm guessing the latter. (Similar
concern about comment in the code.)
> fail to run from non-prepadded firmware files.
>
>
On 04/17/2014 06:02 AM, Thierry Reding wrote:
> From: Thierry Reding
>
> Properties referencing GPIOs should use the plural suffix -gpios. This
> convention is encoded in the device tree backend of gpiod_get(), which
> we'll eventually want to migrate to.
Wouldn't it be simpler to fix the GPIO
https://bugzilla.kernel.org/show_bug.cgi?id=73931
--- Comment #9 from Pali Roh?r ---
Any idea about what to do with last two NULL pointer dereference in
radeon_driver_open_kms?
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On Saturday 19 April 2014 21:03:05 Markus Trippelsdorf wrote:
> On 2014.04.19 at 08:19 +0100, Dave Airlie wrote:
> >
> > Unfortunately this contains no easter eggs, its a bit larger than I'd
> > like, but I included a patch that just moves code from one file to another
> > and I'd like to avoid
On Apr-07-2014 3:24 PM, Vandana Kannan wrote:
> On Apr-07-2014 3:33 PM, Kannan, Vandana wrote:
>> Added a property to enable user space to set aspect ratio.
>> This patch contains declaration of the property and code to create the
>> property.
>>
>> Signed-off-by: Vandana Kannan
>> Cc: dri-devel
On Saturday, April 19, 2014 4:43 AM, Ajay kumar wrote:
> On Fri, Apr 18, 2014 at 2:17 PM, Jingoo Han wrote:
> > On Wednesday, April 16, 2014 11:33 PM, Ajay Kumar wrote:
[.]
> > > +struct panel_exynos_dp {
> > > + struct drm_panelbase;
> > > + struct regulator
On Saturday, April 19, 2014 4:51 AM, Ajay Kumar wrote:
> On Fri, Apr 18, 2014 at 2:27 PM, Jingoo Han wrote:
> > On Wednesday, April 16, 2014 11:33 PM, Ajay Kumar wrote:
[.]
> > > +#ifdef CONFIG_DRM_PANEL_EXYNOS_DP
> > > + platform_driver_unregister(_dp_panel_driver);
> > >
https://bugzilla.kernel.org/show_bug.cgi?id=73111
Zhang Rui changed:
What|Removed |Added
CC||rui.zhang at intel.com
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