SERT_WITH_CODE(
> --
> 2.5.5
>
> ___
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
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On Thu, May 12, 2016 at 12:53:48PM +0300, Jani Nikula wrote:
> On Wed, 11 May 2016, Muhammad Falak R Wani wrote:
> > Use ARRAY_SIZE() for the size calculation of the array. Also move the
> > condition evaulation function out of the for loop.
> > Although, any respectable c-compiler would optimize
Am 13.05.2016 um 18:48 schrieb Alex Deucher:
> Uses same packets as gfx.
>
> Signed-off-by: Alex Deucher
For the series Reviewed-by: Christian König
> ---
> tests/amdgpu/basic_tests.c | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git
Hi Thierry Reding,
I will have to answer this question next week, the member of my team with a
HDMI spec is not here today.
Hi Jani Nikula,
Thank you for noticing the formatting mistake, the checkpatch script did not
catch this, I will prepare a new patch with the formatting fixed.
inc/amd_powerplay.h | 2 +
> >> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 +
> >> 8 files changed, 236 insertions(+), 2 deletions(-)
> >>
> >> --
> >> 2.5.5
> >>
> >> ___
> >> dri-devel mailing list
> >> dri-devel at lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
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are the assignee for the bug.
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L:
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ling list
> dri-devel at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
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This patch expand the cea861 mode timing table to include vic 65
to 107. This allows more modes to be reported on newer displays,
including 4k at 60Hz on HDMI, which was previously only reported if
the display edid has a detailed timing descriptor block specifying
the exact timing
v2:
- fix
From: Ville Syrjälä
DRM_DEBUG_ATOMIC generates a lot of noise that no one normally cares
about. However error paths everyone cares about, so hiding thea error
debugs under DRM_DEBUG_ATOMIC is a bad idea. Let's use DRM_DEBUG_KMS
for those instead.
Signed-off-by:
...
URL:
<https://lists.freedesktop.org/archives/dri-devel/attachments/20160513/3b916616/attachment.html>
On Fri, May 13, 2016 at 3:45 PM, Mike Lothian wrote:
> Hi
>
> I gave this a spin but I just get:
>
> [ 1073.096585] Trying to freeze SCLK DPM when DPM is disabled
> [ 1073.097667] Trying to Unfreeze SCLK DPM when DPM is disabled
> [ 1073.100118] Trying to freeze SCLK DPM when DPM is disabled
> [
From: Eric Huang
Fixes OD failures on Tonga.
Reviewed-by: Alex Deucher
Signed-off-by: Eric Huang
Signed-off-by: Alex Deucher
---
This fixes OD failures on Tonga in some cases.
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 8
1 file changed, 4
Handle any error due to partial reads, timeouts etc. to avoid parsing
uninitialized data subsequently. Also bail out if the parsing itself
fails.
v2:
- Remove blank lines before returns to match the rest of file (Lyude)
CC: Dave Airlie
Signed-off-by: Imre Deak
Reviewed-by: Lyude
---
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On Thu, 12 May 2016, Eric Yang wrote:
> This patch expand the cea861 mode timing table to include vic 65
> to 107. This allows more modes to be reported on newer displays,
> including 4k at 60Hz on HDMI, which was previously only reported if
> the display edid has a detailed timing descriptor
> -Original Message-
> From: Muhammad Falak R Wani [mailto:falakreyaz at gmail.com]
> Sent: Friday, May 13, 2016 1:17 PM
> To: Jani Nikula
> Cc: Koenig, Christian; Nils Wallménius; Zhou, Jammy; linux-
> kernel at vger.kernel.org; dri-devel at lists.freedesktop.org; Deucher,
> Alexander;
Hi Dave,
Here is the pull request for the extern C addition to our UAPI headers.
Many maintainers are in favour of the idea and considering the lack of
volunteers for the `make headers_install' route I'm hoping that we can get
these in and revert, if needed, at a later stage.
Thanks
Emil
The
On Fri, May 13, 2016 at 2:54 PM, Mike Lothian wrote:
> Sounds fancy but what does it do?
Whoops, meant to define OD in the cover letter, the patches have the
details. OD = Overclocking.
Alex
>
> On Fri, 13 May 2016 at 19:49 Alex Deucher wrote:
>>
>> This adds initial OverDrive (OD) support
From: Eric Huang
This implements sclk overdrive(OD) overclocking support for Polaris10,
and the maximum overdrive percentage is 20.
Reviewed-by: Alex Deucher
Signed-off-by: Eric Huang
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
From: Eric Huang
This implements sclk overdrive(OD) overclocking support for Tonga,
and the maximum overdrive percentage is 20.
Reviewed-by: Alex Deucher
Signed-off-by: Eric Huang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c |
From: Eric Huang
This implements sclk overdrive(OD) overclocking support for Fiji,
and the maximum overdrive percentage is 20.
Reviewed-by: Alex Deucher
Signed-off-by: Eric Huang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 43
From: Eric Huang
Add a new sysfs entry pp_sclk_od to support sclk overdrive(OD) overclocking,
the entry is read/write, the value of input/output is an integer which is the
over percentage of the highest sclk.
Reviewed-by: Alex Deucher
Signed-off-by: Eric Huang
From: Eric Huang
Update sclk smc table rather than mclk smc table for sclk updates.
Reviewed-by: Alex Deucher
Signed-off-by: Eric Huang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 2 +-
1 file changed, 1 insertion(+), 1
From: Eric Huang
Update sclk smc table rather than mclk smc table for sclk updates.
Reviewed-by: Alex Deucher
Signed-off-by: Eric Huang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 2 +-
1 file changed, 1 insertion(+), 1
This adds initial OverDrive (OD) support for the gfx engine
clock (sclk). It's enabled by selecting a percentage (0-20)
and writing it to a new sysfs file. It's currently available
on Tonga, Fiji, and Polaris.
Eric Huang (6):
drm/amd/powerplay: fix a bug on updating sclk for Fiji
From: Rex Zhu
This avoids problems with multiple GPUs. For example,
if the first GPU failed before amdgpu_fence_init() was
called, amdgpu_fence_slab_ref is still 0 and it will
get decremented in amdgpu_fence_driver_fini(). This
will lead to a crash during init of the second
From: Rex Zhu
It's generic and used by multiple asics.
Signed-off-by: Rex Zhu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 37 +
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 38
From: Rex Zhu
&& was used instead of ||
Signed-off-by: Rex Zhu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
From: Rex Zhu
SMC uses CurrSclkPllRange structure to keep track of what range of
PLL SCLK is sitting on. Driver overwrites this value to 0 because
it's part of DPM table and driver doesn't program this.
This change will set this field to 0xFF every time there's a
init SMC table
Hi Lothar,
Am Freitag, den 13.05.2016, 12:33 +0200 schrieb Lothar WaÃmann:
> Hi,
>
> the commit 503fe87bd0a8 ("gpu: ipu-v3: Fix imx-ipuv3-crtc module autoloading")
> indeed fixes the autoloading issue, but completely breaks the driver in
> non-modular mode (at least with the parallel-display
From: Sonny Jiang
Signed-off-by: Sonny Jiang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
tests/amdgpu/cs_tests.c | 48 ++--
1 file changed, 42 insertions(+), 6 deletions(-)
diff --git a/tests/amdgpu/cs_tests.c
From: Leo Liu
Signed-off-by: Leo Liu
Reviewed-by: Alex Deucher
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
tests/amdgpu/cs_tests.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c
Signed-off-by: Alex Deucher
---
tests/amdgpu/basic_tests.c | 41 ++---
1 file changed, 34 insertions(+), 7 deletions(-)
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 05ab145..e512bda 100644
--- a/tests/amdgpu/basic_tests.c
+++
Uses same packets as gfx.
Signed-off-by: Alex Deucher
---
tests/amdgpu/basic_tests.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 599c090..05ab145 100644
--- a/tests/amdgpu/basic_tests.c
+++
Here are a few late bugfixes for vc4. I figure it's best to bring
them in through -next since 4.6 is about done. I've based them late
in your -next branch to avoid needing conflict resolution.
The following changes since commit bafb86f5bc3173479002555dea7f31d943b12332:
Merge tag 'v4.6-rc7'
Hi,
the commit 503fe87bd0a8 ("gpu: ipu-v3: Fix imx-ipuv3-crtc module autoloading")
indeed fixes the autoloading issue, but completely breaks the driver in
non-modular mode (at least with the parallel-display driver I didn't
yet check with the imx-ldb driver.
Can anyone confirm that the imx-drm
Hi, YT:
On Thu, 2016-05-12 at 19:49 +0800, yt.shen at mediatek.com wrote:
> From: YT Shen
>
> This patch add support for the Mediatek MT2701 DISP subsystem.
> There is only one OVL engine in MT2701, and we have shadow
> register support here.
>
> Signed-off-by: YT Shen
> ---
> @@ -385,12
Ulf Hansson writes:
> On 11 May 2016 at 23:25, Rafael J. Wysocki wrote:
>> On Wed, May 11, 2016 at 10:00 AM, Ulf Hansson
>> wrote:
>>> If the PM domain is powered off when the first device in the domain starts
>>> its system PM prepare phase, genpd prevents any further attempts to power
>>>
blanks or updates of display lists in the
> hardware?
HVS has bits 0:11 of DISPSTATx for the Y line being generated. That
will be in a different clock domain from the PV, but it's probably good
enough, right?
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On Fri, May 13, 2016 at 12:33:36PM +0200, Lothar WaÃmann wrote:
> I'm always very suspicious when seeing code moving of_node's from
> one device to another or assigning of_node's to platform devices that
> weren't instantiated via DT.
It's completely wrong to add an of_node to a device on the
From: Gustavo Padovan
Add Gustavo as maintainer for the Sync File Framework. Sumit is
co-maintainer as he maintains drivers/dma-buf/. It also uses Sumit's
tree as base.
Signed-off-by: Gustavo Padovan
Acked-by: Sumit Semwal
Acked-by: Maarten Lankhorst
---
This patch replaces zpos property handling custom code in rcar DRM
driver with calls to generic DRM code.
Signed-off-by: Benjamin Gaignard
Cc: Daniel Vetter
Cc: Ville Syrjala
Cc: Laurent Pinchart
Cc: Marek Szyprowski
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 2 +-
From: Marek Szyprowski
This patch replaces zpos property handling custom code in Exynos DRM
driver with calls to generic DRM code.
Signed-off-by: Marek Szyprowski
Signed-off-by: Benjamin Gaignard
Cc: Inki Dae
Cc: Daniel Vetter
Cc: Ville Syrjala
Cc: Joonyoung Shim
remove private zpos property and use instead the generic new.
zpos range is now fixed per plane type and normalized before
being using in mixer.
Signed-off-by: Benjamin Gaignard
Cc: Inki Dae
Cc: Daniel Vetter
Cc: Ville Syrjala
Cc: Joonyoung Shim
Cc: Seung-Woo Kim
Cc: Andrzej Hajda
Cc:
From: Marek Szyprowski
This patch adds support for generic plane's zpos property property with
well-defined semantics:
- added zpos properties to plane and plane state structures
- added helpers for normalizing zpos properties of given set of planes
- well defined
version 3:
use kmalloc_array instead of kmalloc.
Correct normalize_zpos computation (comeback to Mareck original code)
version 2:
add a zpos property into drm_plane structure to simplify code.
This allow to get/set zpos value in core and not in drivers code.
Fix various remarks.
version 1:
AGP mode is unstable on PowerPC
Signed-off-by: Mathieu Malaterre
Reviewed-by: Christian König
---
drivers/gpu/drm/radeon/radeon_drv.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c
b/drivers/gpu/drm/radeon/radeon_drv.c
index ccd4ad4..402cf85
Hi Linus,
A bunch of radeon displayport mode setting fixes, and some misc
i915 fixes. There is one revert, the MST audio code in i915 was causing
some oopses, so we've decided just to drop it until next kernel when
we can fix it properly.
Thanks,
Dave.
The following changes since commit
On 05/09/2016 09:38 PM, Eric Anholt wrote:
> Mario Kleiner writes:
>
>> Hi Eric and all,
>>
>> two small fixes against vc4 kms, built and tested agains the
>> Raspberry Pi foundations 4.4.8 kernel tree on RPi2B.
>>
>> I'm tinkering with a Rpi 2B a bit to see if your vc4 work can
>> already make
Hello,
I have the pleasure to announce that the X.org Developer Conference 2016
will be held in Helsinki from September 21 to September 23. The venue is
located at Haaga-Helia university[0], next to the Pasila station.
The official page for the event is http://www.x.org/wiki/Events/XDC2016
while
From: Nicolai Hähnle
Previously, (*device)->businfo.pci would end up misaligned, which results
in undefined behavior.
Signed-off-by: Nicolai Hähnle
---
xf86drm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/xf86drm.c b/xf86drm.c
index
Hi Dave,
I kinda hoped that I could still sneak in Noralf's
drm_simple_display_pipe, since there's intereset by others now (for tilcdc
at least). But it wasn't ready by a hair. Oh well.
Otherwise random stuff plus prep patches from Noralf.
Cheers, Daniel
The following changes since commit
On Thu, May 12, 2016 at 11:15:42PM +0300, Laurent Pinchart wrote:
> Hi Ville,
>
> On Thursday 12 May 2016 22:46:05 Ville Syrjälä wrote:
> > On Thu, May 12, 2016 at 10:20:12PM +0300, Laurent Pinchart wrote:
> > > On Thursday 12 May 2016 14:51:55 Ville Syrjälä wrote:
> > >> On Thu, May 12, 2016
Hi Ville,
On Thursday 12 May 2016 22:46:05 Ville Syrjälä wrote:
> On Thu, May 12, 2016 at 10:20:12PM +0300, Laurent Pinchart wrote:
> > On Thursday 12 May 2016 14:51:55 Ville Syrjälä wrote:
> >> On Thu, May 12, 2016 at 12:28:19PM +0200, Benjamin Gaignard wrote:
> >>> From: Marek Szyprowski
>
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