[PATCH v6 02/12] mm: migrate: support non-lru movable page migration

2016-05-20 Thread Minchan Kim
We have allowed migration for only LRU pages until now and it was enough to make high-order pages. But recently, embedded system(e.g., webOS, android) uses lots of non-movable pages(e.g., zram, GPU memory) so we have seen several reports about troubles of small high-order allocation. For fixing the

[PATCH v6 00/12] Support non-lru page migration

2016-05-20 Thread Minchan Kim
. zsmalloc page migration zsmalloc: page migration support zram: use __GFP_MOVABLE for memory allocation * From v5 * rebase on next-20160520 * move utility functions to compaction.c and export - Sergey * zsmalloc dobule free fix - Sergey * add additional Reviewed-by for zsmalloc - Serg

[RFC v2 5/5] arm: dts: mt2701: Add display subsystem related nodes for MT2701

2016-05-20 Thread yt.s...@mediatek.com
From: YT Shen This patch adds the device nodes for the DISP function blocks for MT2701 Signed-off-by: YT Shen --- arch/arm/boot/dts/mt2701.dtsi | 117 + 1 file changed, 117 insertions(+) diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt

[RFC v2 4/5] drm/mediatek: add shadow register support

2016-05-20 Thread yt.s...@mediatek.com
From: YT Shen We need to acquire mutex before using the resources, and need to release it after finished. So we don't need to write registers in the blanking period. Signed-off-by: YT Shen --- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 75 +++ drivers/gpu/drm/media

[RFC v2 3/5] drm/mediatek: add *driver_data for different hardware settings

2016-05-20 Thread yt.s...@mediatek.com
From: YT Shen There are some hardware settings changed, between MT8173 & MT2701: DISP_OVL address offset changed, color format definition changed. DISP_RDMA fifo size changed. DISP_COLOR offset changed. Signed-off-by: YT Shen --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 49 +

[RFC v2 2/5] drm/mediatke: add support for Mediatek SoC MT2701

2016-05-20 Thread yt.s...@mediatek.com
From: YT Shen This patch add support for the Mediatek MT2701 DISP subsystem. There is only one OVL engine in MT2701. Signed-off-by: YT Shen --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 63 +--- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |2 + drivers/gpu/drm/med

[RFC v2 1/5] drm/mediatek: rename macros, add chip suffix

2016-05-20 Thread yt.s...@mediatek.com
From: YT Shen Add MT8173 suffix for hardware related macros. Signed-off-by: YT Shen --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 62 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/medi

[RFC v2 0/5] MT2701 DRM support

2016-05-20 Thread yt.s...@mediatek.com
From: YT Shen This is MT2701 DRM support RFC, based on MT8173 DRM patch v16. Most codes are the same, except some register changed. For example: - DISP_OVL address offset changed, color format definition changed. - DISP_RDMA fifo size changed. - DISP_COLOR offset changed. We add a new compon

[PATCH V7 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage

2016-05-20 Thread Laxman Dewangan
The IO pins of Tegra SoCs are grouped for common control of IO interface like setting voltage signal levels and power state of the interface. The group is generally referred as IO pads. The power state and voltage control of IO pins can be done at IO pads level. Tegra generation SoC supports the p

[PATCH V7 2/3] soc/tegra: pmc: Correct type of variable for tegra_pmc_readl()

2016-05-20 Thread Laxman Dewangan
The function tegra_pmc_readl() returns the u32 type data and hence change the data type of variable where this data is stored to u32 type. Signed-off-by: Laxman Dewangan Reviewed-by: Jon Hunter --- Changes from V1: -This is new in series as per discussion on V1 series to use u32 for tegra_pmc_r

[PATCH V7 1/3] soc/tegra: pmc: Use BIT macro for register field definition

2016-05-20 Thread Laxman Dewangan
Use BIT macro for register field definition and make constant as U when using in shift operator like (3 << 30) to (3U << 30) Signed-off-by: Laxman Dewangan Acked-by: Jon Hunter Changes from V1: - Remove the indenting of line which is not for BIT macro usage. Changes from V2: - None Changes fro

[PATCH V7 0/3] soc/tegra: Add support for IO pads power and voltage control

2016-05-20 Thread Laxman Dewangan
The IO pins of Tegra SoCs are grouped for common control of IO interface like setting voltage signal levels and power state of the interface. The group is generally referred as IO pads. The power state and voltage control of IO pins can be done at IO pads level. Tegra124 onwards IO pads support t

[Bug 104791] ACPI errors on Lenovo C50-30 (AE_AML_INFINITE_LOOP, argument type mismatch)

2016-05-20 Thread bugzilla-dae...@bugzilla.kernel.org
https://bugzilla.kernel.org/show_bug.cgi?id=104791 --- Comment #8 from Peter Wu --- Apparently the mail is not found on that list, try this one: https://lists.freedesktop.org/archives/nouveau/2016-May/025039.html -- You are receiving this mail because: You are watching the assignee of the bug.

[PATCH 2/2] dma-buf/fence: add fence_array fences v4

2016-05-20 Thread Christian König
Am 20.05.2016 um 16:47 schrieb Gustavo Padovan: > 2016-05-20 Christian König : > >> From: Gustavo Padovan >> >> struct fence_collection inherits from struct fence and carries a >> collection of fences that needs to be waited together. >> >> It is useful to translate a sync_file to a fence to remo

[Bug 104791] ACPI errors on Lenovo C50-30 (AE_AML_INFINITE_LOOP, argument type mismatch)

2016-05-20 Thread bugzilla-dae...@bugzilla.kernel.org
https://bugzilla.kernel.org/show_bug.cgi?id=104791 --- Comment #7 from James --- (In reply to Peter Wu from comment #6) > Proposed patch: > https://lkml.kernel.org/r/1463244575-3515-1-git-send-email-peter at > lekensteyn. > nl Sorry I didn't immediately spot your response. (Bad Google spam fil

[Bug 95510] ((((1800-929-1150))) online helpline number for aol mail

2016-05-20 Thread bugzilla-dae...@freedesktop.org
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[Bug 95510] ((((1800-929-1150))) online helpline number for aol mail

2016-05-20 Thread bugzilla-dae...@freedesktop.org
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[PULL] vmwgfx-next-160520

2016-05-20 Thread Thomas Hellstrom
From: "Thomas Hellstrom" Dave, Small changes, One lockdep warning fix for 4.6, and a host logging infrastructure. The following changes since commit 7c10ddf87472c07eabc206e273dc59f77c700858: Merge branch 'drm-uapi-extern-c-fixes' of https://github.com/evelikov/linux into drm-next (2016-05-1

[PATCH 4/4] drm/amdgpu: add the CI code to enable sclk OD(OverDrive)

2016-05-20 Thread Alex Deucher
From: Eric Huang Reviewed-by: Alex Deucher Signed-off-by: Eric Huang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 40 + drivers/gpu/drm/amd/amdgpu/ci_dpm.h | 1 + 2 files changed, 41 insertions(+) diff --git a/drivers/gpu/drm/amd/

[PATCH 3/4] drm/amdgpu: add the CI code to enable clock level selection

2016-05-20 Thread Alex Deucher
From: Eric Huang Reviewed-by: Alex Deucher Signed-off-by: Eric Huang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 114 1 file changed, 114 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgp

[PATCH 2/4] drm/amdgpu: add the new common pm code to support sclk OD

2016-05-20 Thread Alex Deucher
From: Eric Huang This extends OD (OverDrive) support to the non-Powerplay code paths. Reviewed-by: Alex Deucher Signed-off-by: Eric Huang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 24 +++- 2 fi

[PATCH 1/4] drm/amdgpu: add the new common pm code to select the clock levels

2016-05-20 Thread Alex Deucher
From: Eric Huang This extends dpm clock level selection to the non-powerplay code paths. This interface can be used to select individual clock levels. Reviewed-by: Alex Deucher Signed-off-by: Eric Huang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 ++ drivers/g

[PATCH 0/4] extend sclk Powerplay features to CI dGPUs

2016-05-20 Thread Alex Deucher
This patch set extends independent clock selection and sclk OverDrive (overclocking) to CI dGPUs. Eric Huang (4): drm/amdgpu: add the new common pm code to select the clock levels drm/amdgpu: add the new common pm code to support sclk OD drm/amdgpu: add the CI code to enable clock level sele

[PATCH 6/6] drm/amdgpu/si: reduce gfx ring size

2016-05-20 Thread Alex Deucher
This was already done for other asics. We don't need a very big ring with the scheduler. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/

[PATCH 5/6] drm/amdgpu/si: reduce dma ring size

2016-05-20 Thread Alex Deucher
This was already done for other asics. We don't need a very big ring with the scheduler. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/si_dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_d

[PATCH 4/6] drm/amdgpu/si: use dma instance offset array directly

2016-05-20 Thread Alex Deucher
No need for a local variable. Also, fix a few registers that did not have the per instance offset properly added. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/si_dma.c | 29 ++--- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/d

[PATCH 3/6] drm/amdgpu/si: replace some hardcoded 2s with dma num_instances

2016-05-20 Thread Alex Deucher
Fix up a few cases that were previously missed. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/si_dma.c | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 03c11a1..7e65b64 10064

[PATCH 2/6] drm/amdgpu/si: simplify si_dma_start

2016-05-20 Thread Alex Deucher
Remove the wrapper that was a left over from porting the code into amdgpu. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/si_dma.c | 19 +-- 1 file changed, 1 insertion(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu

[PATCH 1/6] drm/amdgpu/si: stop dma engines on hw fini and suspend

2016-05-20 Thread Alex Deucher
Fixes failure on suspend due to rings not being marked as not ready. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/si_dma.c | 21 + 1 file changed, 21 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 873

[PATCH] drm/i915/ilk: Wait one vblank before enabling audio

2016-05-20 Thread Lyude
We no longer call ilk_audio_codec_enable() while we have vblanks disabled. As such, we can finally fix this and stop the occasional pipe underruns I'm seeing on this Dell OptiPlex 990. Cc: stable at vger.kernel.org Signed-off-by: Lyude --- drivers/gpu/drm/i915/intel_audio.c | 8 ++-- 1 file

[PATCH V6 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage

2016-05-20 Thread Laxman Dewangan
The IO pins of Tegra SoCs are grouped for common control of IO interface like setting voltage signal levels and power state of the interface. The group is generally referred as IO pads. The power state and voltage control of IO pins can be done at IO pads level. Tegra generation SoC supports the p

[PATCH V6 2/3] soc/tegra: pmc: Correct type of variable for tegra_pmc_readl()

2016-05-20 Thread Laxman Dewangan
The function tegra_pmc_readl() returns the u32 type data and hence change the data type of variable where this data is stored to u32 type. Signed-off-by: Laxman Dewangan Reviewed-by: Jon Hunter --- Changes from V1: -This is new in series as per discussion on V1 series to use u32 for tegra_pmc_r

[PATCH V6 1/3] soc/tegra: pmc: Use BIT macro for register field definition

2016-05-20 Thread Laxman Dewangan
Use BIT macro for register field definition and make constant as U when using in shift operator like (3 << 30) to (3U << 30) Signed-off-by: Laxman Dewangan Acked-by: Jon Hunter --- Changes from V1: - Remove the indenting of line which is not for BIT macro usage. Changes from V2: - None Changes

[PATCH V6 0/3] soc/tegra: Add support for IO pads power and voltage control

2016-05-20 Thread Laxman Dewangan
The IO pins of Tegra SoCs are grouped for common control of IO interface like setting voltage signal levels and power state of the interface. The group is generally referred as IO pads. The power state and voltage control of IO pins can be done at IO pads level. Tegra124 onwards IO pads support t

[PATCH 2/3] drm/imx: convey the pixelclk-active and de-active flags from DT to the ipu-di driver

2016-05-20 Thread Philipp Zabel
Hi Lothar, Am Freitag, den 20.05.2016, 15:34 +0200 schrieb Lothar Waßmann: > Currently these flags are lost in the call > drm_display_mode_from_videomode() > > Signed-off-by: Lothar Waßmann thank you for the patches. The other two look fine to me, could you rebase this one on top of: https://

[PATCH 2/4] drm/omapdrm: Add gamma table support to DSS dispc

2016-05-20 Thread Tomi Valkeinen
), but I am happy to add it. > True, I think we can trust omapdrm here =). Tomi -- next part -- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: OpenPGP digital signature URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160520/6fa72a65/attachment.sig>

[PATCH 3/4] drm/omapdrm: Work-a-round for errata i734 (LCD1 Gamma) in DSS dispc

2016-05-20 Thread Tomi Valkeinen
t_ops = { > @@ -4324,6 +4488,8 @@ static int dispc_runtime_resume(struct device *dev) > if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) { > _omap_dispc_initial_config(); > > + dispc_errata_i734_wa(); > + > dispc_restore_context(); > > dispc_restore_gamma_tables(); > diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.c > b/drivers/gpu/drm/omapdrm/dss/dss_features.c > index f77b1c5..3127bd6 100644 > --- a/drivers/gpu/drm/omapdrm/dss/dss_features.c > +++ b/drivers/gpu/drm/omapdrm/dss/dss_features.c > @@ -594,6 +594,7 @@ static const enum dss_feat_id omap4_dss_feat_list[] = { > FEAT_FIFO_MERGE, > FEAT_BURST_2D, > FEAT_GAMMA_TABLE, > + FEAT_GAMMA_I734_BUG, This, too, should be in dispc features. Tomi -- next part -- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: OpenPGP digital signature URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160520/812de47f/attachment.sig>

[PATCH 2/4] drm/omapdrm: Add gamma table support to DSS dispc

2016-05-20 Thread Jyri Sarha
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[PATCH 2/2] dma-buf/fence: add fence_array fences v4

2016-05-20 Thread Christian König
From: Gustavo Padovan struct fence_collection inherits from struct fence and carries a collection of fences that needs to be waited together. It is useful to translate a sync_file to a fence to remove the complexity of dealing with sync_files on DRM drivers. So even if there are many fences in t

[PATCH 1/2] dma-buf/fence: make fence context 64 bit v2

2016-05-20 Thread Christian König
From: Christian König Fence contexts are created on the fly (for example) by the GPU scheduler used in the amdgpu driver as a result of an userspace request. Because of this userspace could in theory force a wrap around of the 32bit context number if it doesn't behave well. Avoid this by increa

[PATCH 1/2] drm/amd/powerplay: fix bugs of checking if dpm is running on Tonga

2016-05-20 Thread Christian König
Please ignore this one, I was on the wrong branch while sending mails. Christian. Am 20.05.2016 um 15:53 schrieb Christian König: > From: Eric Huang > > Fixes OD failures on Tonga. > > Reviewed-by: Alex Deucher > Signed-off-by: Eric Huang > Signed-off-by: Alex Deucher > --- > drivers/gpu/d

[PATCH 2/2] dma-buf/fence: add fence_array fences v4

2016-05-20 Thread Christian König
From: Gustavo Padovan struct fence_collection inherits from struct fence and carries a collection of fences that needs to be waited together. It is useful to translate a sync_file to a fence to remove the complexity of dealing with sync_files on DRM drivers. So even if there are many fences in t

[PATCH 1/2] drm/amd/powerplay: fix bugs of checking if dpm is running on Tonga

2016-05-20 Thread Christian König
From: Eric Huang Fixes OD failures on Tonga. Reviewed-by: Alex Deucher Signed-off-by: Eric Huang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/t

[PATCH 2/4] drm/omapdrm: Add gamma table support to DSS dispc

2016-05-20 Thread Tomi Valkeinen
index 4837442..bc1d812 100644 > --- a/drivers/gpu/drm/omapdrm/dss/dispc.h > +++ b/drivers/gpu/drm/omapdrm/dss/dispc.h > @@ -42,6 +42,11 @@ > #define DISPC_MSTANDBY_CTRL 0x0858 > #define DISPC_GLOBAL_MFLAG_ATTRIBUTE 0x085C > > +#define DISPC_GAMMA_TABLE0 0x0630 > +#define DISPC_GAMMA_TABLE1 0x0634 > +#define DISPC_GAMMA_TABLE2 0x0638 > +#define DISPC_GAMMA_TABLE3 0x0850 > + > /* DISPC overlay registers */ > #define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \ > DISPC_BA0_OFFSET(n)) > diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.c > b/drivers/gpu/drm/omapdrm/dss/dss_features.c > index c886a29..f77b1c5 100644 > --- a/drivers/gpu/drm/omapdrm/dss/dss_features.c > +++ b/drivers/gpu/drm/omapdrm/dss/dss_features.c > @@ -593,6 +593,7 @@ static const enum dss_feat_id omap4_dss_feat_list[] = { > FEAT_ALPHA_FREE_ZORDER, > FEAT_FIFO_MERGE, > FEAT_BURST_2D, > + FEAT_GAMMA_TABLE, > }; The dss_features is deprecated. New features should be added to the respective driver. In this case, dispc.c. See struct dispc_features. Tomi -- next part -- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: OpenPGP digital signature URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160520/c065ae3d/attachment-0001.sig>

[PATCH 2/2] dma-buf/fence: add fence_array fences v4

2016-05-20 Thread Chris Wilson
On Fri, May 20, 2016 at 03:56:11PM +0200, Christian König wrote: > From: Gustavo Padovan > > struct fence_collection inherits from struct fence and carries a > collection of fences that needs to be waited together. > > It is useful to translate a sync_file to a fence to remove the complexity >

[PATCH 3/3] drm/imx: remove dead code

2016-05-20 Thread Lothar Waßmann
The 'mode_valid' flag is never set in this driver. Remove it and the code that depends on it. Signed-off-by: Lothar Waßmann --- drivers/gpu/drm/imx/parallel-display.c | 12 1 file changed, 12 deletions(-) diff --git a/drivers/gpu/drm/imx/parallel-display.c b/drivers/gpu/drm/imx/p

[PATCH 2/3] drm/imx: convey the pixelclk-active and de-active flags from DT to the ipu-di driver

2016-05-20 Thread Lothar Waßmann
Currently these flags are lost in the call drm_display_mode_from_videomode() Signed-off-by: Lothar Waßmann --- drivers/gpu/drm/imx/imx-drm-core.c | 12 +++ drivers/gpu/drm/imx/imx-drm.h | 7 --- drivers/gpu/drm/imx/imx-ldb.c | 37 ++

[PATCH 1/3] drm/imx: imx-ldb: honor 'native-mode' property when selecting video mode from DT

2016-05-20 Thread Lothar Waßmann
This patch allows to select a specific video mode from a list of modes defined in DT by setting the 'native-mode' property appropriately. This change does not affect the behaviour of existing platforms, since they either: - have just one display-timings subnode - have the native-mode propert

[PATCH 0/3] drm/imx: convey the pixelclk-active and de-active flags to the ipu-di driver

2016-05-20 Thread Lothar Waßmann
The 'de-active' and 'pixelclk-active' DT properties are evaluated by of_parse_display_timing() called from of_get_drm_display_mode(), but later lost in the conversion from videomode.flags to drm_display_mode.flags. Use an open coded version of of_get_drm_display_mode() to get access to these flags

[PATCH V5 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage

2016-05-20 Thread Laxman Dewangan
On Friday 20 May 2016 03:32 PM, Jon Hunter wrote: > On 12/05/16 13:21, Laxman Dewangan wrote: > +#define TEGRA_IO_PADS_T124_T210 (TEGRA_IO_PADS_T124 | \ > + TEGRA_IO_PADS_T210) > + > What about T30 and T114? The TRM includes the DPD REQ/STATUS reg

[PATCH 1/4] drm/omapdrm: omap_modeset_init: Separate crtc id and plane id indexing

2016-05-20 Thread Tomi Valkeinen
eaning this up would be to rename that enum so that it can be used in omapdrm. Tomi -- next part -- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: OpenPGP digital signature URL: <https://lists.freedeskto

[PATCH V6 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage

2016-05-20 Thread Jon Hunter
On 20/05/16 14:34, Laxman Dewangan wrote: > > On Friday 20 May 2016 07:02 PM, Jon Hunter wrote: >> On 20/05/16 12:59, Laxman Dewangan wrote: >>> +/* tegra_io_pads_config_info: Tegra IO pads bit config info. >>> + * @dpd_config_bit: DPD configuration bit position. -1 if not >>> supported. >>> + *

[PATCH V6 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage

2016-05-20 Thread Jon Hunter
On 20/05/16 14:34, Laxman Dewangan wrote: > > On Friday 20 May 2016 07:02 PM, Jon Hunter wrote: >> On 20/05/16 12:59, Laxman Dewangan wrote: >>> +/* tegra_io_pads_config_info: Tegra IO pads bit config info. >>> + * @dpd_config_bit: DPD configuration bit position. -1 if not >>> supported. >>> + *

[PATCH V6 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage

2016-05-20 Thread Jon Hunter
On 20/05/16 12:59, Laxman Dewangan wrote: > The IO pins of Tegra SoCs are grouped for common control of IO > interface like setting voltage signal levels and power state of > the interface. The group is generally referred as IO pads. The > power state and voltage control of IO pins can be done at

[v2] drm/imx: Match imx-ipuv3-crtc components using device node in platform data

2016-05-20 Thread Heiko Schocher
Hello Philipp, Am 18.05.2016 um 14:56 schrieb Philipp Zabel: > The component master driver imx-drm-core matches component devices using > their of_node. Since commit 950b410dd1ab ("gpu: ipu-v3: Fix imx-ipuv3-crtc > module autoloading"), the imx-ipuv3-crtc dev->of_node is not set during > probing.

[PATCH] gpu: ipu-v3: display support on the aristainetos2 board broken

2016-05-20 Thread Heiko Schocher
Hello Fabio, Am 20.05.2016 um 13:40 schrieb Fabio Estevam: > Hi Heiko, > > On Fri, May 20, 2016 at 8:15 AM, Heiko Schocher wrote: >> commit 503fe87bd0a8 ("gpu: ipu-v3: Fix imx-ipuv3-crtc module autoloading") >> breaks the aristainetos2 board with the "lg,lg4573" panel. >> >> This reverts the abov

[PATCH] drm: hdlcd: Revamp runtime power management

2016-05-20 Thread Liviu Dudau
Because the HDLCD driver acts as a component master it can end up enabling the runtime PM functionality before the encoders are initialised. This can cause crashes if the component slave never probes (missing module) or if the PM operations kick in before the probe finishes. Move the enabling of t

[Bug 95474] Bioshock Infinite and DiRT Showdown perform very poorly on any GPU with GCN >=1.1

2016-05-20 Thread bugzilla-dae...@freedesktop.org
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[PATCH] gpu: ipu-v3: display support on the aristainetos2 board broken

2016-05-20 Thread Heiko Schocher
commit 503fe87bd0a8 ("gpu: ipu-v3: Fix imx-ipuv3-crtc module autoloading") breaks the aristainetos2 board with the "lg,lg4573" panel. This reverts the above commit. Signed-off-by: Heiko Schocher --- Any hint, how to bring back the display on the aristainetos2 board without reverting this commit

[PATCH] Revert "drm/core: Preserve the framebuffer after removing it."

2016-05-20 Thread Hans de Goede
Hi, On 19-05-16 17:33, Daniel Vetter wrote: > On Thu, May 19, 2016 at 5:15 PM, Hans de Goede wrote: >> This reverts commit 13803132818c ("drm/core: Preserve the framebuffer >> after removing it."). >> >> This commit assumes that going through drm_framebuffer_remove() is not >> necessary because "

[PATCH 2/2] dma-buf/fence: add fence_array fences v4

2016-05-20 Thread Gustavo Padovan
2016-05-20 Christian König : > From: Gustavo Padovan > > struct fence_collection inherits from struct fence and carries a > collection of fences that needs to be waited together. > > It is useful to translate a sync_file to a fence to remove the complexity > of dealing with sync_files on DRM d

[PATCH V5 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage

2016-05-20 Thread Jon Hunter
On 20/05/16 10:59, Laxman Dewangan wrote: > > On Friday 20 May 2016 03:32 PM, Jon Hunter wrote: >> On 12/05/16 13:21, Laxman Dewangan wrote: >> +#define TEGRA_IO_PADS_T124_T210(TEGRA_IO_PADS_T124 |\ >> +TEGRA_IO_PADS_T210) >> + >> What about T30 and T114? The TRM i

[PATCH V5 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage

2016-05-20 Thread Jon Hunter
On 12/05/16 13:21, Laxman Dewangan wrote: > The IO pins of Tegra SoCs are grouped for common control of IO > interface like setting voltage signal levels and power state of > the interface. The group is generally referred as IO pads. The > power state and voltage control of IO pins can be done at

[PATCH 4/4] drm/omapdrm: Implement gamma_lut atomic crtc property

2016-05-20 Thread Jyri Sarha
On 05/20/16 10:05, Daniel Vetter wrote: > On Fri, May 20, 2016 at 09:35:56AM +0300, Jyri Sarha wrote: >> > Implement gamma_lut atomic crtc property, set crtc gamma size to 256 >> > for all crtcs and use drm_atomic_helper_legacy_gamma_set() as >> > gamma_set func. The tv-out crtc has 1024 element ga

[PATCH V5 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage

2016-05-20 Thread Jon Hunter
On 19/05/16 16:54, Jon Hunter wrote: > > On 12/05/16 13:21, Laxman Dewangan wrote: >> The IO pins of Tegra SoCs are grouped for common control of IO >> interface like setting voltage signal levels and power state of >> the interface. The group is generally referred as IO pads. The >> power state

[PATCH 4/4] drm/omapdrm: Implement gamma_lut atomic crtc property

2016-05-20 Thread Daniel Vetter
On Fri, May 20, 2016 at 9:35 AM, Jyri Sarha wrote: > On 05/20/16 10:05, Daniel Vetter wrote: >> On Fri, May 20, 2016 at 09:35:56AM +0300, Jyri Sarha wrote: >>> > Implement gamma_lut atomic crtc property, set crtc gamma size to 256 >>> > for all crtcs and use drm_atomic_helper_legacy_gamma_set() as

Is flicker-free interlaced mode toggling possible to implement?

2016-05-20 Thread Alberto Simón Francés
. Best regards, Alberto Simon -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160520/6b6812bb/attachment.html>

[PATCH V5 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage

2016-05-20 Thread Jon Hunter
On 19/05/16 17:13, Laxman Dewangan wrote: > On Thursday 19 May 2016 09:24 PM, Jon Hunter wrote: >> On 12/05/16 13:21, Laxman Dewangan wrote: >>> The IO pins of Tegra SoCs are grouped for common control of IO >>> interface like setting voltage signal levels and power state of >>> the interface. The

[PATCH v2 2/3] drm/arm: Add support for Mali Display Processors

2016-05-20 Thread Liviu Dudau
On Fri, May 20, 2016 at 08:57:47AM +0200, Daniel Vetter wrote: > On Thu, May 19, 2016 at 04:26:49PM +0100, Liviu Dudau wrote: > > On Mon, Apr 25, 2016 at 03:19:23PM +0100, Liviu Dudau wrote: > > > Add support for the new family of Display Processors from ARM Ltd. > > > This commit adds basic suppor

[PATCH 4/4] drm/omapdrm: Implement gamma_lut atomic crtc property

2016-05-20 Thread Jyri Sarha
Implement gamma_lut atomic crtc property, set crtc gamma size to 256 for all crtcs and use drm_atomic_helper_legacy_gamma_set() as gamma_set func. The tv-out crtc has 1024 element gamma table (with 10bit precision) in HW, but current Xorg server does not accept anything else but 256 elements so tha

[PATCH 3/4] drm/omapdrm: Work-a-round for errata i734 (LCD1 Gamma) in DSS dispc

2016-05-20 Thread Jyri Sarha
Work-a-round for errata i734 in DSS dispc - LCD1 Gamma Correction Is Not Working When GFX Pipe Is Disabled For gamma tables to work on LCD1 the GFX plane has to be used at least once after DSS HW has come out of reset. The work-a-round sets up a minimal LCD setup with GFX plane and waits for one

[PATCH 2/4] drm/omapdrm: Add gamma table support to DSS dispc

2016-05-20 Thread Jyri Sarha
Add gamma table support to DSS dispc. DSS driver initializes the default gamma table at component bind time and holds a copy of all gamma tables in it's internal data structure. Each call to dispc_mgr_set_gamma() updates the internal table and triggers write the HW, if it is enabled. The tables a

[PATCH 1/4] drm/omapdrm: omap_modeset_init: Separate crtc id and plane id indexing

2016-05-20 Thread Jyri Sarha
Separate crtc id and plane id indexing in omap_modeset_init(). The coupling of crtc- and plane-id is hard to follow. Signed-off-by: Jyri Sarha --- drivers/gpu/drm/omapdrm/omap_drv.c | 31 +-- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/

[PATCH 0/4] drm/omapdrm: gamma table support

2016-05-20 Thread Jyri Sarha
Implements gamma tables for OMAP4, OMAP5, and dra7xx SoCs and adds a work-a-round for errata that may break LCD1 channel if gamma tables are in use. The first patch ("drm/omapdrm: omap_modeset_init: Separate crtc id and plane id indexing") is not really a part of the series and can be applied or d

[PATCH 4/4] drm/omapdrm: Implement gamma_lut atomic crtc property

2016-05-20 Thread Daniel Vetter
On Fri, May 20, 2016 at 09:35:56AM +0300, Jyri Sarha wrote: > Implement gamma_lut atomic crtc property, set crtc gamma size to 256 > for all crtcs and use drm_atomic_helper_legacy_gamma_set() as > gamma_set func. The tv-out crtc has 1024 element gamma table (with > 10bit precision) in HW, but curre

[PATCH v2 2/3] drm/arm: Add support for Mali Display Processors

2016-05-20 Thread Daniel Vetter
On Thu, May 19, 2016 at 04:26:49PM +0100, Liviu Dudau wrote: > On Mon, Apr 25, 2016 at 03:19:23PM +0100, Liviu Dudau wrote: > > Add support for the new family of Display Processors from ARM Ltd. > > This commit adds basic support for Mali DP500, DP550 and DP650 > > parts, with only the display engi

[PATCH] gpu: ipu-v3: display support on the aristainetos2 board broken

2016-05-20 Thread Fabio Estevam
Hi Heiko, On Fri, May 20, 2016 at 8:15 AM, Heiko Schocher wrote: > commit 503fe87bd0a8 ("gpu: ipu-v3: Fix imx-ipuv3-crtc module autoloading") > breaks the aristainetos2 board with the "lg,lg4573" panel. > > This reverts the above commit. > > Signed-off-by: Heiko Schocher > > --- > Any hint, how

[PATCH 8/8] drm/amdgpu/gfx8: Enable GFX PG on CZ

2016-05-20 Thread Alex Deucher
From: Tom St Denis Based on Alex's patches this enables GFX PG on CZ. Tested with xonotic-glx/glxgears/supertuxkart and idle desktop. Also read-back registers via umr for verificiation that the bits are truly enabled. Signed-off-by: Tom St Denis Reviewed-by: Alex Deucher Signed-off-by: Alex D

[PATCH 7/8] drm/amdgpu/gfx8: clean up polaris11 PG enable

2016-05-20 Thread Alex Deucher
Fix the logic for enabling/disabling. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 18 +- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 0508cef..494104

[PATCH 6/8] drm/amdgpu/gfx8: add powergating support for CZ/ST

2016-05-20 Thread Alex Deucher
This implements powergating support for CZ/ST asics. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 132 -- 1 file changed, 126 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu

[PATCH 5/8] drm/amdgpu: add new GFX powergating types

2016-05-20 Thread Alex Deucher
Add some new GFX powergating flags. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/amd_shared.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 6080951..147b2eb 100644 --- a/drivers/gpu/

[PATCH 4/8] drm/amdgpu/gfx8: rename some pg functions

2016-05-20 Thread Alex Deucher
So they can be shared with other asics. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 22 -- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 7fcde08.

[PATCH 3/8] drm/amdgpu/gfx8: add state setup for CZ/ST GFX power gating

2016-05-20 Thread Alex Deucher
This sets up the CP jump table and GDS buffer and sets the PG state registers. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 133 -- 1 file changed, 128 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/

[PATCH 2/8] drm/radeon/gfx7: expand cp jt size to handle GDS as well

2016-05-20 Thread Alex Deucher
The size needs to handle the CP JT and GDS. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/cik.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index ba192a3..5c88c1c 100644 --- a/drivers/gpu/drm/radeon/ci

[PATCH 1/8] drm/amdgpu/gfx7: expand cp jt size to handle GDS as well

2016-05-20 Thread Alex Deucher
The size needs to handle the CP JT and GDS. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 7f18a53..d58425e 100644 ---

[PATCH 0/8] Add GFX powergating support for CZ

2016-05-20 Thread Alex Deucher
This patch set adds powergating support for the gfx block on Carrizo. Also fixes a few issues with powergating setup on older asics. Powergating improves idle powersaving. Alex Deucher (7): drm/amdgpu/gfx7: expand cp jt size to handle GDS as well drm/radeon/gfx7: expand cp jt size to handle

Small vc4 kms fixes and some questions.

2016-05-20 Thread Mario Kleiner
ck and mode clock... *vpos = -vblank_lines + (*vpos * mode->crtc_clock / 25); ... under the assumption that the HVS clock is == system clock and that clock is a constant 250 Mhz, based on some numbers from some of the public docs. However, i'm not sure if the 250 Mhz is right, or if this is even constant across Soc's or wrt. power management. That specific code path so far doesn't really improve precision. I'm not sure if i should drop it, or refine it, or how. But maybe my assumptions about HVS composition rate vs. PV scanout rate are wrong there, or the clock value is wrong? thanks, -mario -- next part -- A non-text attachment was scrubbed... Name: 0001-drm-vc4-Implement-precise-vblank-timestamping.patch Type: text/x-patch Size: 13566 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160520/45813d52/attachment-0001.bin>

[PATCH] gpu/nouveau/nouveau_acpi.c: Fix Type Mismatch ACPI warning

2016-05-20 Thread Marcos Souza
; https://github.com/torvalds/linux/blob/46c13450624e36302547a2ac3695f2350fe7ffc3/drivers/acpi/utils.c#L628 Thanks for all the links. I'll read the docs and send a new version of the patch when it makes more sense instead of just replacing random things. > > > > if (!obj) { > > acpi_handle_info(handle, "failed to evaluate _DSM\n"); > > return AE_ERROR; > > -- > > 2.5.5 > > > > ___ > > dri-devel mailing list > > dri-devel at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/dri-devel > -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160520/5416344d/attachment-0001.html>

[PATCH] drm: Nuke ->vblank_disable_allowed

2016-05-20 Thread Laurent Pinchart
Hi Daniel, Thank you for the patch. On Wednesday 18 May 2016 22:29:57 Daniel Vetter wrote: > This was added in > > commit 0a3e67a4caac273a3bfc4ced3da364830b1ab241 > Author: Jesse Barnes > Date: Tue Sep 30 12:14:26 2008 -0700 > > drm: Rework vblank-wait handling to allow interrupt reducti

[Nouveau] [PATCH v4] vga_switcheroo: Add helper for deferred probing

2016-05-20 Thread Emil Velikov
Hi Lukas, On 19 May 2016 at 15:39, Lukas Wunner wrote: > +bool vga_switcheroo_client_probe_defer(struct pci_dev *pdev) > +{ > + if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) { Not sure if we want/need this, yet at least. This changes behaviour which is not what refactoring patches shoul

AMDGPU fail to restore secondary monitor after suspend

2016-05-20 Thread Daniel Mota Leite
rg/archives/dri-devel/attachments/20160520/63e7f636/attachment.sig>