We have allowed migration for only LRU pages until now and it was
enough to make high-order pages. But recently, embedded system(e.g.,
webOS, android) uses lots of non-movable pages(e.g., zram, GPU memory)
so we have seen several reports about troubles of small high-order
allocation. For fixing the
. zsmalloc page migration
zsmalloc: page migration support
zram: use __GFP_MOVABLE for memory allocation
* From v5
* rebase on next-20160520
* move utility functions to compaction.c and export - Sergey
* zsmalloc dobule free fix - Sergey
* add additional Reviewed-by for zsmalloc - Serg
From: YT Shen
This patch adds the device nodes for the DISP function blocks for MT2701
Signed-off-by: YT Shen
---
arch/arm/boot/dts/mt2701.dtsi | 117 +
1 file changed, 117 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt
From: YT Shen
We need to acquire mutex before using the resources,
and need to release it after finished.
So we don't need to write registers in the blanking period.
Signed-off-by: YT Shen
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 75 +++
drivers/gpu/drm/media
From: YT Shen
There are some hardware settings changed, between MT8173 & MT2701:
DISP_OVL address offset changed, color format definition changed.
DISP_RDMA fifo size changed.
DISP_COLOR offset changed.
Signed-off-by: YT Shen
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 49 +
From: YT Shen
This patch add support for the Mediatek MT2701 DISP subsystem.
There is only one OVL engine in MT2701.
Signed-off-by: YT Shen
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 63 +---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |2 +
drivers/gpu/drm/med
From: YT Shen
Add MT8173 suffix for hardware related macros.
Signed-off-by: YT Shen
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 62
1 file changed, 31 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/medi
From: YT Shen
This is MT2701 DRM support RFC, based on MT8173 DRM patch v16.
Most codes are the same, except some register changed.
For example:
- DISP_OVL address offset changed, color format definition changed.
- DISP_RDMA fifo size changed.
- DISP_COLOR offset changed.
We add a new compon
The IO pins of Tegra SoCs are grouped for common control of IO
interface like setting voltage signal levels and power state of
the interface. The group is generally referred as IO pads. The
power state and voltage control of IO pins can be done at IO pads
level.
Tegra generation SoC supports the p
The function tegra_pmc_readl() returns the u32 type data and hence
change the data type of variable where this data is stored to u32
type.
Signed-off-by: Laxman Dewangan
Reviewed-by: Jon Hunter
---
Changes from V1:
-This is new in series as per discussion on V1 series to use u32 for
tegra_pmc_r
Use BIT macro for register field definition and make constant as U
when using in shift operator like (3 << 30) to (3U << 30)
Signed-off-by: Laxman Dewangan
Acked-by: Jon Hunter
Changes from V1:
- Remove the indenting of line which is not for BIT macro usage.
Changes from V2:
- None
Changes fro
The IO pins of Tegra SoCs are grouped for common control of IO interface
like setting voltage signal levels and power state of the interface. The
group is generally referred as IO pads. The power state and voltage control
of IO pins can be done at IO pads level.
Tegra124 onwards IO pads support t
https://bugzilla.kernel.org/show_bug.cgi?id=104791
--- Comment #8 from Peter Wu ---
Apparently the mail is not found on that list, try this one:
https://lists.freedesktop.org/archives/nouveau/2016-May/025039.html
--
You are receiving this mail because:
You are watching the assignee of the bug.
Am 20.05.2016 um 16:47 schrieb Gustavo Padovan:
> 2016-05-20 Christian König :
>
>> From: Gustavo Padovan
>>
>> struct fence_collection inherits from struct fence and carries a
>> collection of fences that needs to be waited together.
>>
>> It is useful to translate a sync_file to a fence to remo
https://bugzilla.kernel.org/show_bug.cgi?id=104791
--- Comment #7 from James ---
(In reply to Peter Wu from comment #6)
> Proposed patch:
> https://lkml.kernel.org/r/1463244575-3515-1-git-send-email-peter at
> lekensteyn.
> nl
Sorry I didn't immediately spot your response. (Bad Google spam fil
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From: "Thomas Hellstrom"
Dave,
Small changes, One lockdep warning fix for 4.6,
and a host logging infrastructure.
The following changes since commit 7c10ddf87472c07eabc206e273dc59f77c700858:
Merge branch 'drm-uapi-extern-c-fixes' of https://github.com/evelikov/linux
into drm-next (2016-05-1
From: Eric Huang
Reviewed-by: Alex Deucher
Signed-off-by: Eric Huang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 40 +
drivers/gpu/drm/amd/amdgpu/ci_dpm.h | 1 +
2 files changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/amd/
From: Eric Huang
Reviewed-by: Alex Deucher
Signed-off-by: Eric Huang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 114
1 file changed, 114 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
b/drivers/gpu/drm/amd/amdgp
From: Eric Huang
This extends OD (OverDrive) support to the non-Powerplay code paths.
Reviewed-by: Alex Deucher
Signed-off-by: Eric Huang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 24 +++-
2 fi
From: Eric Huang
This extends dpm clock level selection to the non-powerplay code paths.
This interface can be used to select individual clock levels.
Reviewed-by: Alex Deucher
Signed-off-by: Eric Huang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 ++
drivers/g
This patch set extends independent clock selection and sclk OverDrive
(overclocking) to CI dGPUs.
Eric Huang (4):
drm/amdgpu: add the new common pm code to select the clock levels
drm/amdgpu: add the new common pm code to support sclk OD
drm/amdgpu: add the CI code to enable clock level sele
This was already done for other asics. We don't need
a very big ring with the scheduler.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/
This was already done for other asics. We don't need
a very big ring with the scheduler.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/si_dma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c
b/drivers/gpu/drm/amd/amdgpu/si_d
No need for a local variable. Also, fix a few registers
that did not have the per instance offset properly added.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/si_dma.c | 29 ++---
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/d
Fix up a few cases that were previously missed.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/si_dma.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c
b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 03c11a1..7e65b64 10064
Remove the wrapper that was a left over from porting the code
into amdgpu.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/si_dma.c | 19 +--
1 file changed, 1 insertion(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c
b/drivers/gpu/drm/amd/amdgpu
Fixes failure on suspend due to rings not being marked
as not ready.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/si_dma.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c
b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 873
We no longer call ilk_audio_codec_enable() while we have vblanks
disabled. As such, we can finally fix this and stop the occasional pipe
underruns I'm seeing on this Dell OptiPlex 990.
Cc: stable at vger.kernel.org
Signed-off-by: Lyude
---
drivers/gpu/drm/i915/intel_audio.c | 8 ++--
1 file
The IO pins of Tegra SoCs are grouped for common control of IO
interface like setting voltage signal levels and power state of
the interface. The group is generally referred as IO pads. The
power state and voltage control of IO pins can be done at IO pads
level.
Tegra generation SoC supports the p
The function tegra_pmc_readl() returns the u32 type data and hence
change the data type of variable where this data is stored to u32
type.
Signed-off-by: Laxman Dewangan
Reviewed-by: Jon Hunter
---
Changes from V1:
-This is new in series as per discussion on V1 series to use u32 for
tegra_pmc_r
Use BIT macro for register field definition and make constant as U
when using in shift operator like (3 << 30) to (3U << 30)
Signed-off-by: Laxman Dewangan
Acked-by: Jon Hunter
---
Changes from V1:
- Remove the indenting of line which is not for BIT macro usage.
Changes from V2:
- None
Changes
The IO pins of Tegra SoCs are grouped for common control of IO interface
like setting voltage signal levels and power state of the interface. The
group is generally referred as IO pads. The power state and voltage control
of IO pins can be done at IO pads level.
Tegra124 onwards IO pads support t
Hi Lothar,
Am Freitag, den 20.05.2016, 15:34 +0200 schrieb Lothar WaÃmann:
> Currently these flags are lost in the call
> drm_display_mode_from_videomode()
>
> Signed-off-by: Lothar WaÃmann
thank you for the patches. The other two look fine to me, could you
rebase this one on top of:
https://
), but I am happy to add it.
>
True, I think we can trust omapdrm here =).
Tomi
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t_ops = {
> @@ -4324,6 +4488,8 @@ static int dispc_runtime_resume(struct device *dev)
> if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
> _omap_dispc_initial_config();
>
> + dispc_errata_i734_wa();
> +
> dispc_restore_context();
>
> dispc_restore_gamma_tables();
> diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.c
> b/drivers/gpu/drm/omapdrm/dss/dss_features.c
> index f77b1c5..3127bd6 100644
> --- a/drivers/gpu/drm/omapdrm/dss/dss_features.c
> +++ b/drivers/gpu/drm/omapdrm/dss/dss_features.c
> @@ -594,6 +594,7 @@ static const enum dss_feat_id omap4_dss_feat_list[] = {
> FEAT_FIFO_MERGE,
> FEAT_BURST_2D,
> FEAT_GAMMA_TABLE,
> + FEAT_GAMMA_I734_BUG,
This, too, should be in dispc features.
Tomi
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From: Gustavo Padovan
struct fence_collection inherits from struct fence and carries a
collection of fences that needs to be waited together.
It is useful to translate a sync_file to a fence to remove the complexity
of dealing with sync_files on DRM drivers. So even if there are many
fences in t
From: Christian König
Fence contexts are created on the fly (for example) by the GPU scheduler used
in the amdgpu driver as a result of an userspace request. Because of this
userspace could in theory force a wrap around of the 32bit context number
if it doesn't behave well.
Avoid this by increa
Please ignore this one, I was on the wrong branch while sending mails.
Christian.
Am 20.05.2016 um 15:53 schrieb Christian König:
> From: Eric Huang
>
> Fixes OD failures on Tonga.
>
> Reviewed-by: Alex Deucher
> Signed-off-by: Eric Huang
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/d
From: Gustavo Padovan
struct fence_collection inherits from struct fence and carries a
collection of fences that needs to be waited together.
It is useful to translate a sync_file to a fence to remove the complexity
of dealing with sync_files on DRM drivers. So even if there are many
fences in t
From: Eric Huang
Fixes OD failures on Tonga.
Reviewed-by: Alex Deucher
Signed-off-by: Eric Huang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/t
index 4837442..bc1d812 100644
> --- a/drivers/gpu/drm/omapdrm/dss/dispc.h
> +++ b/drivers/gpu/drm/omapdrm/dss/dispc.h
> @@ -42,6 +42,11 @@
> #define DISPC_MSTANDBY_CTRL 0x0858
> #define DISPC_GLOBAL_MFLAG_ATTRIBUTE 0x085C
>
> +#define DISPC_GAMMA_TABLE0 0x0630
> +#define DISPC_GAMMA_TABLE1 0x0634
> +#define DISPC_GAMMA_TABLE2 0x0638
> +#define DISPC_GAMMA_TABLE3 0x0850
> +
> /* DISPC overlay registers */
> #define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \
> DISPC_BA0_OFFSET(n))
> diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.c
> b/drivers/gpu/drm/omapdrm/dss/dss_features.c
> index c886a29..f77b1c5 100644
> --- a/drivers/gpu/drm/omapdrm/dss/dss_features.c
> +++ b/drivers/gpu/drm/omapdrm/dss/dss_features.c
> @@ -593,6 +593,7 @@ static const enum dss_feat_id omap4_dss_feat_list[] = {
> FEAT_ALPHA_FREE_ZORDER,
> FEAT_FIFO_MERGE,
> FEAT_BURST_2D,
> + FEAT_GAMMA_TABLE,
> };
The dss_features is deprecated. New features should be added to the
respective driver. In this case, dispc.c. See struct dispc_features.
Tomi
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On Fri, May 20, 2016 at 03:56:11PM +0200, Christian König wrote:
> From: Gustavo Padovan
>
> struct fence_collection inherits from struct fence and carries a
> collection of fences that needs to be waited together.
>
> It is useful to translate a sync_file to a fence to remove the complexity
>
The 'mode_valid' flag is never set in this driver. Remove it and the
code that depends on it.
Signed-off-by: Lothar WaÃmann
---
drivers/gpu/drm/imx/parallel-display.c | 12
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/imx/parallel-display.c
b/drivers/gpu/drm/imx/p
Currently these flags are lost in the call
drm_display_mode_from_videomode()
Signed-off-by: Lothar WaÃmann
---
drivers/gpu/drm/imx/imx-drm-core.c | 12 +++
drivers/gpu/drm/imx/imx-drm.h | 7 ---
drivers/gpu/drm/imx/imx-ldb.c | 37 ++
This patch allows to select a specific video mode from a list of modes
defined in DT by setting the 'native-mode' property appropriately.
This change does not affect the behaviour of existing platforms, since
they either:
- have just one display-timings subnode
- have the native-mode propert
The 'de-active' and 'pixelclk-active' DT properties are evaluated
by of_parse_display_timing() called from of_get_drm_display_mode(),
but later lost in the conversion from videomode.flags to
drm_display_mode.flags.
Use an open coded version of of_get_drm_display_mode() to get access
to these flags
On Friday 20 May 2016 03:32 PM, Jon Hunter wrote:
> On 12/05/16 13:21, Laxman Dewangan wrote:
> +#define TEGRA_IO_PADS_T124_T210 (TEGRA_IO_PADS_T124 | \
> + TEGRA_IO_PADS_T210)
> +
> What about T30 and T114? The TRM includes the DPD REQ/STATUS reg
eaning this up would be to rename that
enum so that it can be used in omapdrm.
Tomi
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On 20/05/16 14:34, Laxman Dewangan wrote:
>
> On Friday 20 May 2016 07:02 PM, Jon Hunter wrote:
>> On 20/05/16 12:59, Laxman Dewangan wrote:
>>> +/* tegra_io_pads_config_info: Tegra IO pads bit config info.
>>> + * @dpd_config_bit: DPD configuration bit position. -1 if not
>>> supported.
>>> + *
On 20/05/16 14:34, Laxman Dewangan wrote:
>
> On Friday 20 May 2016 07:02 PM, Jon Hunter wrote:
>> On 20/05/16 12:59, Laxman Dewangan wrote:
>>> +/* tegra_io_pads_config_info: Tegra IO pads bit config info.
>>> + * @dpd_config_bit: DPD configuration bit position. -1 if not
>>> supported.
>>> + *
On 20/05/16 12:59, Laxman Dewangan wrote:
> The IO pins of Tegra SoCs are grouped for common control of IO
> interface like setting voltage signal levels and power state of
> the interface. The group is generally referred as IO pads. The
> power state and voltage control of IO pins can be done at
Hello Philipp,
Am 18.05.2016 um 14:56 schrieb Philipp Zabel:
> The component master driver imx-drm-core matches component devices using
> their of_node. Since commit 950b410dd1ab ("gpu: ipu-v3: Fix imx-ipuv3-crtc
> module autoloading"), the imx-ipuv3-crtc dev->of_node is not set during
> probing.
Hello Fabio,
Am 20.05.2016 um 13:40 schrieb Fabio Estevam:
> Hi Heiko,
>
> On Fri, May 20, 2016 at 8:15 AM, Heiko Schocher wrote:
>> commit 503fe87bd0a8 ("gpu: ipu-v3: Fix imx-ipuv3-crtc module autoloading")
>> breaks the aristainetos2 board with the "lg,lg4573" panel.
>>
>> This reverts the abov
Because the HDLCD driver acts as a component master it can end
up enabling the runtime PM functionality before the encoders
are initialised. This can cause crashes if the component slave
never probes (missing module) or if the PM operations kick in
before the probe finishes.
Move the enabling of t
re receiving this mail because:
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commit 503fe87bd0a8 ("gpu: ipu-v3: Fix imx-ipuv3-crtc module autoloading")
breaks the aristainetos2 board with the "lg,lg4573" panel.
This reverts the above commit.
Signed-off-by: Heiko Schocher
---
Any hint, how to bring back the display on the aristainetos2
board without reverting this commit
Hi,
On 19-05-16 17:33, Daniel Vetter wrote:
> On Thu, May 19, 2016 at 5:15 PM, Hans de Goede wrote:
>> This reverts commit 13803132818c ("drm/core: Preserve the framebuffer
>> after removing it.").
>>
>> This commit assumes that going through drm_framebuffer_remove() is not
>> necessary because "
2016-05-20 Christian König :
> From: Gustavo Padovan
>
> struct fence_collection inherits from struct fence and carries a
> collection of fences that needs to be waited together.
>
> It is useful to translate a sync_file to a fence to remove the complexity
> of dealing with sync_files on DRM d
On 20/05/16 10:59, Laxman Dewangan wrote:
>
> On Friday 20 May 2016 03:32 PM, Jon Hunter wrote:
>> On 12/05/16 13:21, Laxman Dewangan wrote:
>> +#define TEGRA_IO_PADS_T124_T210(TEGRA_IO_PADS_T124 |\
>> +TEGRA_IO_PADS_T210)
>> +
>> What about T30 and T114? The TRM i
On 12/05/16 13:21, Laxman Dewangan wrote:
> The IO pins of Tegra SoCs are grouped for common control of IO
> interface like setting voltage signal levels and power state of
> the interface. The group is generally referred as IO pads. The
> power state and voltage control of IO pins can be done at
On 05/20/16 10:05, Daniel Vetter wrote:
> On Fri, May 20, 2016 at 09:35:56AM +0300, Jyri Sarha wrote:
>> > Implement gamma_lut atomic crtc property, set crtc gamma size to 256
>> > for all crtcs and use drm_atomic_helper_legacy_gamma_set() as
>> > gamma_set func. The tv-out crtc has 1024 element ga
On 19/05/16 16:54, Jon Hunter wrote:
>
> On 12/05/16 13:21, Laxman Dewangan wrote:
>> The IO pins of Tegra SoCs are grouped for common control of IO
>> interface like setting voltage signal levels and power state of
>> the interface. The group is generally referred as IO pads. The
>> power state
On Fri, May 20, 2016 at 9:35 AM, Jyri Sarha wrote:
> On 05/20/16 10:05, Daniel Vetter wrote:
>> On Fri, May 20, 2016 at 09:35:56AM +0300, Jyri Sarha wrote:
>>> > Implement gamma_lut atomic crtc property, set crtc gamma size to 256
>>> > for all crtcs and use drm_atomic_helper_legacy_gamma_set() as
.
Best regards,
Alberto Simon
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On 19/05/16 17:13, Laxman Dewangan wrote:
> On Thursday 19 May 2016 09:24 PM, Jon Hunter wrote:
>> On 12/05/16 13:21, Laxman Dewangan wrote:
>>> The IO pins of Tegra SoCs are grouped for common control of IO
>>> interface like setting voltage signal levels and power state of
>>> the interface. The
On Fri, May 20, 2016 at 08:57:47AM +0200, Daniel Vetter wrote:
> On Thu, May 19, 2016 at 04:26:49PM +0100, Liviu Dudau wrote:
> > On Mon, Apr 25, 2016 at 03:19:23PM +0100, Liviu Dudau wrote:
> > > Add support for the new family of Display Processors from ARM Ltd.
> > > This commit adds basic suppor
Implement gamma_lut atomic crtc property, set crtc gamma size to 256
for all crtcs and use drm_atomic_helper_legacy_gamma_set() as
gamma_set func. The tv-out crtc has 1024 element gamma table (with
10bit precision) in HW, but current Xorg server does not accept
anything else but 256 elements so tha
Work-a-round for errata i734 in DSS dispc
- LCD1 Gamma Correction Is Not Working When GFX Pipe Is Disabled
For gamma tables to work on LCD1 the GFX plane has to be used at least
once after DSS HW has come out of reset. The work-a-round sets up a
minimal LCD setup with GFX plane and waits for one
Add gamma table support to DSS dispc.
DSS driver initializes the default gamma table at component bind time
and holds a copy of all gamma tables in it's internal data structure.
Each call to dispc_mgr_set_gamma() updates the internal table and
triggers write the HW, if it is enabled. The tables a
Separate crtc id and plane id indexing in omap_modeset_init(). The
coupling of crtc- and plane-id is hard to follow.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/omapdrm/omap_drv.c | 31 +--
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/
Implements gamma tables for OMAP4, OMAP5, and dra7xx SoCs and adds a
work-a-round for errata that may break LCD1 channel if gamma tables
are in use.
The first patch ("drm/omapdrm: omap_modeset_init: Separate crtc id and
plane id indexing") is not really a part of the series and can be
applied or d
On Fri, May 20, 2016 at 09:35:56AM +0300, Jyri Sarha wrote:
> Implement gamma_lut atomic crtc property, set crtc gamma size to 256
> for all crtcs and use drm_atomic_helper_legacy_gamma_set() as
> gamma_set func. The tv-out crtc has 1024 element gamma table (with
> 10bit precision) in HW, but curre
On Thu, May 19, 2016 at 04:26:49PM +0100, Liviu Dudau wrote:
> On Mon, Apr 25, 2016 at 03:19:23PM +0100, Liviu Dudau wrote:
> > Add support for the new family of Display Processors from ARM Ltd.
> > This commit adds basic support for Mali DP500, DP550 and DP650
> > parts, with only the display engi
Hi Heiko,
On Fri, May 20, 2016 at 8:15 AM, Heiko Schocher wrote:
> commit 503fe87bd0a8 ("gpu: ipu-v3: Fix imx-ipuv3-crtc module autoloading")
> breaks the aristainetos2 board with the "lg,lg4573" panel.
>
> This reverts the above commit.
>
> Signed-off-by: Heiko Schocher
>
> ---
> Any hint, how
From: Tom St Denis
Based on Alex's patches this enables GFX PG on CZ.
Tested with xonotic-glx/glxgears/supertuxkart and idle desktop.
Also read-back registers via umr for verificiation that the bits
are truly enabled.
Signed-off-by: Tom St Denis
Reviewed-by: Alex Deucher
Signed-off-by: Alex D
Fix the logic for enabling/disabling.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 0508cef..494104
This implements powergating support for CZ/ST asics.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 132 --
1 file changed, 126 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu
Add some new GFX powergating flags.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/include/amd_shared.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
b/drivers/gpu/drm/amd/include/amd_shared.h
index 6080951..147b2eb 100644
--- a/drivers/gpu/
So they can be shared with other asics.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 7fcde08.
This sets up the CP jump table and GDS buffer and sets the
PG state registers.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 133 --
1 file changed, 128 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/
The size needs to handle the CP JT and GDS.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index ba192a3..5c88c1c 100644
--- a/drivers/gpu/drm/radeon/ci
The size needs to handle the CP JT and GDS.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 7f18a53..d58425e 100644
---
This patch set adds powergating support for the gfx block
on Carrizo. Also fixes a few issues with powergating setup
on older asics. Powergating improves idle powersaving.
Alex Deucher (7):
drm/amdgpu/gfx7: expand cp jt size to handle GDS as well
drm/radeon/gfx7: expand cp jt size to handle
ck and mode clock...
*vpos = -vblank_lines + (*vpos * mode->crtc_clock / 25);
... under the assumption that the HVS clock is == system clock and that
clock is a constant 250 Mhz, based on some numbers from some of the
public docs. However, i'm not sure if the 250 Mhz is right, or if this
is even constant across Soc's or wrt. power management. That specific
code path so far doesn't really improve precision. I'm not sure if i
should drop it, or refine it, or how. But maybe my assumptions about HVS
composition rate vs. PV scanout rate are wrong there, or the clock value
is wrong?
thanks,
-mario
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; https://github.com/torvalds/linux/blob/46c13450624e36302547a2ac3695f2350fe7ffc3/drivers/acpi/utils.c#L628
Thanks for all the links. I'll read the docs and send a new version of the
patch when it makes more sense instead of just replacing random things.
>
>
> > if (!obj) {
> > acpi_handle_info(handle, "failed to evaluate _DSM\n");
> > return AE_ERROR;
> > --
> > 2.5.5
> >
> > ___
> > dri-devel mailing list
> > dri-devel at lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
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Hi Daniel,
Thank you for the patch.
On Wednesday 18 May 2016 22:29:57 Daniel Vetter wrote:
> This was added in
>
> commit 0a3e67a4caac273a3bfc4ced3da364830b1ab241
> Author: Jesse Barnes
> Date: Tue Sep 30 12:14:26 2008 -0700
>
> drm: Rework vblank-wait handling to allow interrupt reducti
Hi Lukas,
On 19 May 2016 at 15:39, Lukas Wunner wrote:
> +bool vga_switcheroo_client_probe_defer(struct pci_dev *pdev)
> +{
> + if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
Not sure if we want/need this, yet at least. This changes behaviour
which is not what refactoring patches shoul
rg/archives/dri-devel/attachments/20160520/63e7f636/attachment.sig>
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