i915_driver_open() is equivalent to i915_gem_open(). Replace the
i915_driver_open with the direct use of i915_gem_open().
Signed-off-by: Masahiro Yamada
---
drivers/gpu/drm/i915/i915_drv.c | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i9
Remove unneeded variables and assignments.
Signed-off-by: Masahiro Yamada
---
drivers/gpu/drm/qxl/qxl_draw.c| 7 ++-
drivers/gpu/drm/qxl/qxl_release.c | 7 ++-
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/qxl/qxl_draw.c b/drivers/gpu/drm/qxl/qxl_dr
Remove unneeded variables and assignments.
Signed-off-by: Masahiro Yamada
---
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 20
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
b/drivers/gpu/drm/bridge/a
Remove unneeded variables and assignments.
Signed-off-by: Masahiro Yamada
---
drivers/gpu/drm/radeon/cik.c | 6 +-
drivers/gpu/drm/radeon/r100.c | 6 +-
drivers/gpu/drm/radeon/r600.c | 6 +-
3 files changed, 3 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.
Remove unneeded variables and assignments.
Signed-off-by: Masahiro Yamada
---
drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 6 +-
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 6 +-
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 6 +-
3 files changed, 3 insertions(+), 15 deletions(-)
diff --
Changes in v2:
- Split per-driver
- Remove i915_driver_open()
- Fix dce_virtual_hw_init() as well
Masahiro Yamada (5):
drm/amdgpu: squash lines for simple wrapper functions
drm/radeon: squash lines for simple wrapper functions
drm/bridge: squash lines for simple wrapper functions
drm
On 9/14/2016 3:14 AM, Stephen Boyd wrote:
> On 09/13/2016 08:21 AM, Archit Taneja wrote:
>> APQ8064 contains a MDP4 based display controller. It contains a HDMI, LVDS
>> and 2 DSI outputs.
>>
>> Add display DT nodes for MDP4, HDMI TX and HDMI PHY. MDP4 based display
>> blocks have a flat device h
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After changes introduced by last patches, there is no useful data stored
in vop_plane_state struct. Let's remove it and make the driver use
generic plane state alone.
Signed-off-by: Tomasz Figa
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 94 +
1 file changed, 1
This patch makes the driver send the pending vblank event in next vblank
following the commit, relying on vblank signalling improvements done in
previous patches. This gives us vblank events that always represent the
real moment of changes hitting on the screen (which was the case only
for complete
Originally we needed to enable vblank for any atomic commit to kick the
PSR machine, but that was changed and we no longer need to do so from
a vblank interrupt. Let's return to original behavior of enabling
vblank only if it is really necessary.
This essentially reverts commit 5b6804034ae9 ("drm/
Currently the driver uses a custom function to wait for flip to complete
after an atomic commit. It was needed before because of two problems:
- there is no hardware vblank counter, so the original helper would
have a race condition with the vblank interrupt,
- the driver didn't support unrefe
Currently the driver waits for vblank and then unreferences old
framebuffers from atomic commit code path. This is however breaking the
legacy cursor API, which requires the updates to be fully asynchronous.
Instead of just adding a special case for cursor, we can have actually
smaller amount of co
Since VOP does not have a hardware vblank count register, the ongoing
commit might be racing with a requested vblank interrupt, which would
increment the software vblank counter before the changes being committed
actually happen.
To avoid this, we can extend .atomic_flush(), so after it sets cfg_d
Current code implements prepare_fb and cleanup_fb callbacks only to
grab/release fb references, which is already done by atomic framework
when creating/destryoing plane state. Let's remove these
unused bits.
Signed-off-by: Tomasz Figa
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 18
The enable register only masks the raw status bits to signal CPU
interrupt only for enabled interrupts. The status bits are activated
regardless of the enable register. This means that we might have an old
interrupt event queued, which we are not interested in. To avoid getting
a spurious interrupt
The display controller found on Rockchip SoCs supported by Rockchip DRM
driver (VOP) is a bit problematic, because it does not provide hardware
vblank counter. Because vblank interrupt is used to feed the software
counter, the driver had custom code to wait for flip completion to avoid
race between
Hi Philipp,
On 08/29/2016 06:50 PM, Rob Herring wrote:
> On Wed, Aug 24, 2016 at 08:46:37AM +0300, Vladimir Zapolskiy wrote:
>> The change adds support of internal HDMI I2C master controller, this
>> subdevice is used by default, if "ddc-i2c-bus" DT property is omitted.
>>
>> The main purpose of t
eiving this mail because:
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On Pi0/1/2, we use an external GPIO line for hotplug detection, since
the HDMI_HOTPLUG register isn't connected to anything. However, with
the Pi3 the HPD GPIO line has moved off to a GPIO expander that will
be tricky to get to (the firmware is constantly polling the expander
using i2c0, so we'll
On Wed, Sep 14, 2016 at 11:04:01AM -0300, Gustavo Padovan wrote:
> 2016-09-14 Chris Wilson :
> > I think there still seems to be a memory leak when calling
> > sync_file_set_fence() here with i == 1.
>
> I think that is something we discussed already, we don't hold an extra
> ref there for i == 1
Hi Philipp,
On 09/06/2016 02:26 AM, Philipp Zabel wrote:
> Hi Steve,
>
> Am Mittwoch, den 17.08.2016, 17:50 -0700 schrieb Steve Longerbeam:
>> This patch implements complete image conversion support to ipu-ic,
>> with tiling to support scaling to and from images up to 4096x4096.
>> Image rotation
On Tue, Sep 13, 2016 at 11:06:16AM -0700, Bjorn Andersson wrote:
> > I hate to send a ping,
>
> Sorry about that.
>
> > but do you think we can merge this fdma series? It has gone
> > through quite a few review rounds now.
> >
>
> I think the remoteproc part looks good.
yeah I was waiting for
Hi Chris and Gustavo,
On Mon, Aug 29, 2016 at 07:16:13PM +0100, Chris Wilson wrote:
> If we being polled with a timeout of zero, a nonblocking busy query,
> we don't need to install any fence callbacks as we will not be waiting.
> As we only install the callback once, the overhead comes from the a
When we merge several fences, if all of them are signaled already, we
still keep one of them. So instead of using add_fence(), which will not
increase the refcount of signaled fences, we should explicitly call
fence_get() for the fence we are keeping.
This patch fixes a kernel panic that can be tr
trunk with llvm-svn
trunk. It's working with mesa-git trunk with llvm-3.8.1
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Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl()
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planes; i++) {
> seq_printf(m, " %d: offset=%d pitch=%d, obj: ",
> i, fb->offsets[i], fb->pitches[i]);
> drm_gem_cma_describe(fb_cma->obj[i], m);
This change doesn't seem to improve the function. Afaics, only the num
planes is retrieved and used.
Tomi
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size
to inform userspace.
i915 perf moved to taking an array of u64 properties and no longer writes
back a size member in the param struct like perf.
Thanks,
- Robert
>
> Regards,
> Emil
>
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Hi Robert,
I think I've spotted one interesting, yet trivial bit.
On 14 September 2016 at 15:19, Robert Bragg wrote:
> Adds base i915 perf infrastructure for Gen performance metrics.
>
> This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
> properties to configure a stream o
rm/radeon/radeon_drv.h
>> @@ -119,4 +119,9 @@
>> long radeon_drm_ioctl(struct file *filp,
>> unsigned int cmd, unsigned long arg);
>> +#if defined(CONFIG_DEBUG_FS)
>> +int radeon_debugfs_init(struct drm_minor *minor);
>> +void radeon_debugfs_cleanup(struct drm_minor *minor);
>> +#endif
>> +
>> #endif/* __RADEON_DRV_H__ */
>>
>
>
>
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Hi, YT:
On Wed, 2016-09-14 at 15:22 +0800, YT Shen wrote:
> Hi CK,
>
> On Wed, 2016-09-14 at 14:39 +0800, CK Hu wrote:
> > Hi, YT:
> >
> > On Wed, 2016-09-14 at 14:19 +0800, YT Shen wrote:
> > > Hi CK,
> > >
> > > On Tue, 2016-09-13 at 17:25 +0800, CK Hu wrote:
> > > > Hi, YT:
> > > >
> > > >
Hi CK,
On Wed, 2016-09-14 at 14:39 +0800, CK Hu wrote:
> Hi, YT:
>
> On Wed, 2016-09-14 at 14:19 +0800, YT Shen wrote:
> > Hi CK,
> >
> > On Tue, 2016-09-13 at 17:25 +0800, CK Hu wrote:
> > > Hi, YT:
> > >
> > > On Mon, 2016-09-12 at 18:16 +0800, YT Shen wrote:
> > > > Hi CK,
> > > >
> > > > O
These should be the last vc4 fixes for 4.8.
The following changes since commit 552416c146fadc67cd9b53ef7adf88d3381c43a6:
drm/vc4: Fix oops when userspace hands in a bad BO. (2016-08-19 19:17:39
-0700)
are available in the git repository at:
https://github.com/anholt/linux tags/drm-vc4-fixe
In particular this tries to capture for posterity some of the early
challenges we had with using the core perf infrastructure in case we
ever want to revisit adapting perf for device metrics.
Cc: Chris Wilson
Signed-off-by: Robert Bragg
---
drivers/gpu/drm/i915/i915_perf.c | 163 +++
This adds 'compute', 'compute extended', 'memory reads', 'memory writes'
and 'sampler balance' metric sets for Haswell.
The code is auto generated from an XML description of metric sets,
currently maintained in gputop, ref:
https://github.com/rib/gputop
> gputop-data/oa-*.xml
> scripts/i915-pe
The minimal sampling period is now configurable via a
dev.i915.oa_min_timer_exponent sysctl parameter.
Following the precedent set by perf, the default is the minimum that
won't (on its own) exceed the default kernel.perf_event_max_sample_rate
default of 10 samples/s.
Signed-off-by: Robert Br
Consistent with the kernel.perf_event_paranoid sysctl option that can
allow non-root users to access system wide cpu metrics, this can
optionally allow non-root users to access system wide OA counter metrics
from Gen graphics hardware.
Signed-off-by: Robert Bragg
---
drivers/gpu/drm/i915/i915_dr
Each metric set is given a sysfs entry like:
/sys/class/drm/card0/metrics//id
This allows userspace to enumerate the specific sets that are available
for the current system. The 'id' file contains an unsigned integer that
can be used to open the associated metric set via
DRM_IOCTL_I915_PERF_OPEN.
Gen graphics hardware can be set up to periodically write snapshots of
performance counters into a circular buffer via its Observation
Architecture and this patch exposes that capability to userspace via the
i915 perf interface.
Cc: Chris Wilson
Signed-off-by: Robert Bragg
Signed-off-by: Zhenyu
Adds a static OA unit, MUX + B Counter configuration for basic render
metrics on Haswell. This is auto generated from an XML
description of metric sets, currently maintained in gputop, ref:
https://github.com/rib/gputop
> gputop-data/oa-*.xml
> scripts/i915-perf-kernelgen.py
$ make -C gpu
Being able to program OACONTROL from a non-privileged batch buffer is
not sufficient to be able to configure the OA unit. This was originally
allowed to help enable Mesa to expose OA counters via the
INTEL_performance_query extension, but the current implementation based
on programming OACONTROL vi
check_cmd() is checking whether a command adheres to certain
restrictions that ensure it's safe to execute within a privileged batch
buffer. Returning false implies a privilege problem, not that the
command is invalid.
The distinction makes the difference between allowing the buffer to be
executed
OACONTROL changes quite a bit for gen8, with some bits split out into a
per-context OACTXCONTROL register. Rename now before adding more gen7 OA
registers
Signed-off-by: Robert Bragg
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 4 ++--
drivers/gpu/drm/i915/i915_reg.h| 2 +-
2 files chang
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl()
This just rebases my i915 perf series on a recent drm-intel-nightly.
Considering now that this series has been reviewed a number of times by Chris,
and I think I've responded to his feedback: I wonder if this series is ready
to be added to drm-intel-nightly soon?
I think most of the effort for th
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87ee8..4e79d6159856 100644
> --- a/include/drm/drm_fourcc.h
> +++ b/include/drm/drm_fourcc.h
> @@ -25,6 +25,25 @@
> #include
> #include
>
> +/**
> + * struct drm_format_info - information about a DRM format
> + * @format: 4CC format identifier (DRM_FORMAT_*)
> + * @depth: color depth (number of bits per pixel excluding padding bits)
Depth is zero for yuv formats. Maybe that should be made clear here.
Tomi
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Hi, YT:
On Wed, 2016-09-14 at 14:19 +0800, YT Shen wrote:
> Hi CK,
>
> On Tue, 2016-09-13 at 17:25 +0800, CK Hu wrote:
> > Hi, YT:
> >
> > On Mon, 2016-09-12 at 18:16 +0800, YT Shen wrote:
> > > Hi CK,
> > >
> > > On Wed, 2016-09-07 at 10:33 +0800, CK Hu wrote:
> > > > Hi, YT:
> > > >
> > > >
.
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Hi CK,
On Tue, 2016-09-13 at 17:25 +0800, CK Hu wrote:
> Hi, YT:
>
> On Mon, 2016-09-12 at 18:16 +0800, YT Shen wrote:
> > Hi CK,
> >
> > On Wed, 2016-09-07 at 10:33 +0800, CK Hu wrote:
> > > Hi, YT:
> > >
> > > On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote:
> > > > From: shaoming chen
> >
On Wed, 14 Sep 2016, Jani Nikula wrote:
> On Wed, 14 Sep 2016, Pavel Machek wrote:
>> For the "sometimes need xrandr after resume": I don't think I can
>> bisect that. It only happens sometimes :-(. But there's something
>> helpful in the logs:
>
>> [ 1856.218863] [drm:drm_edid_block_valid] *ERRO
We get 2 warnings when building kernel with W=1:
drivers/gpu/drm/radeon/radeon_device.c:1961:5: warning: no previous prototype
for 'radeon_debugfs_init' [-Wmissing-prototypes]
drivers/gpu/drm/radeon/radeon_device.c:1966:6: warning: no previous prototype
for 'radeon_debugfs_cleanup' [-Wmissing-pro
because:
You are the assignee for the bug.
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Hi Peter
On 09/05/2016 03:16 PM, Peter Griffin wrote:
> This patch enables the uniperif players 2 & 3 for b2120 boards
> and also adds the "simple-audio-card" device node to interconnect
> the SoC sound device and the codec.
>
> Signed-off-by: Arnaud Pouliquen
> Signed-off-by: Peter Griffin
> -
Hi Peter
On 09/05/2016 03:16 PM, Peter Griffin wrote:
> This patch adds the DT node for the uniperif reader
> IP block found on STiH407 family silicon.
>
> Signed-off-by: Arnaud Pouliquen
> Signed-off-by: Peter Griffin
> ---
> arch/arm/boot/dts/stih407-family.dtsi | 28
Hi Peter
On 09/05/2016 03:16 PM, Peter Griffin wrote:
> This patch adds the DT nodes for the uniperif player
> IP blocks found on STiH407 family silicon.
>
> Signed-off-by: Arnaud Pouliquen
> Signed-off-by: Peter Griffin
> ---
> arch/arm/boot/dts/stih407-family.dtsi | 80
> +++
Hi Peter
On 09/05/2016 03:16 PM, Peter Griffin wrote:
> This patch adds the dt node for the internal audio
> codec IP.
>
> Signed-off-by: Arnaud Pouliquen
> Signed-off-by: Peter Griffin
> ---
> arch/arm/boot/dts/stih407-family.dtsi | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git
Hi Peter
On 09/05/2016 03:16 PM, Peter Griffin wrote:
> This patch adds the pinctrl config for the spidf out
> pins used by the sasg codec IP.
>
> Signed-off-by: Arnaud Pouliquen
> Signed-off-by: Peter Griffin
> Acked-by: Lee Jones
> ---
> arch/arm/boot/dts/stih407-pinctrl.dtsi | 8
>
Hi Peter
On 09/05/2016 03:16 PM, Peter Griffin wrote:
> This patch adds the pinctrl config for the i2s_in pins
> used by the uniperif reader IP.
>
> Signed-off-by: Arnaud Pouliquen
> Signed-off-by: Peter Griffin
> Acked-by: Lee Jones
> ---
> arch/arm/boot/dts/stih407-pinctrl.dtsi | 24 +++
Hi Peter
On 09/05/2016 03:16 PM, Peter Griffin wrote:
> This patch adds the pinctrl config for the i2s_out pins
> used by the uniperif player IP.
>
> Signed-off-by: Arnaud Pouliquen
> Signed-off-by: Peter Griffin
> Acked-by: Lee Jones
> ---
> arch/arm/boot/dts/stih407-pinctrl.dtsi | 23 ++
Hi Peter
On 09/05/2016 03:16 PM, Peter Griffin wrote:
> These nodes are required to get the fdma driver working
> on STiH407 based silicon.
>
> Signed-off-by: Peter Griffin
> Acked-by: Lee Jones
> ---
> arch/arm/boot/dts/stih407-family.dtsi | 52
> +++
> 1 file
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Hi, YT:
On Mon, 2016-09-12 at 20:01 +0800, YT Shen wrote:
> This patch update enable/disable flow of DSI module and MIPI TX module.
> Original flow works on there is a bridge chip: DSI -> bridge -> panel.
> In this case: DSI -> panel, the DSI sub driver flow should be updated.
> We need to initial
When a plane is going to be enabled we re-evaluate the possible crtcs
for the associated drm plane. Only the crtc on which the plane should be
displayed is considered possible until the plane is disabled.
Indeed STI hardware does not allow to dynamically change
the plane's crtc/mixer assignment whe
2016-09-14 Rafael Antognolli :
> On Wed, Sep 14, 2016 at 11:04:01AM -0300, Gustavo Padovan wrote:
> > 2016-09-14 Chris Wilson :
> >
> > > On Tue, Sep 13, 2016 at 04:24:27PM -0700, Rafael Antognolli wrote:
> > > > The refcount of a fence should be increased whenever it is added to a
> > > > merge
Am Mittwoch, 14. September 2016, 12:17:53 CEST schrieb Jani Nikula:
> On Wed, 14 Sep 2016, Pavel Machek wrote:
> > For the "sometimes need xrandr after resume": I don't think I can
> > bisect that. It only happens sometimes :-(. But there's something
> > helpful in the logs:
> >
> > [ 1856.218863
https://bugzilla.kernel.org/show_bug.cgi?id=153121
--- Comment #37 from Kontantin Ivanov ---
I'm always ready to help with this bug. Actually, UVD is not important for me.
But the card I want to use. May be there is some documentation how to work with
similar problems... ?
--
You are receiving
https://bugzilla.kernel.org/show_bug.cgi?id=153121
Kontantin Ivanov changed:
What|Removed |Added
Kernel Version|4.8.0-040800rc2 |4.8.0-040800rc5
--
You are receiving
Hi Dave,
Am Montag, den 29.08.2016, 17:44 +0200 schrieb Daniel Vetter:
> On Mon, Aug 29, 2016 at 4:59 PM, Philipp Zabel
> wrote:
> > Am Montag, den 29.08.2016, 12:53 +0200 schrieb Philipp Zabel:
> >> Am Freitag, den 26.08.2016, 15:30 +0800 schrieb Liu Ying:
> >> > This patch adds active plane re
On Wed, 14 Sep 2016, Pavel Machek wrote:
> Intel folks, any ideas? Can you reproduce it?
It's possible (but not confirmed yet) we've seen this in our CI, but has
slipped through because it's sporadic.
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
On Tue, Sep 13, 2016 at 5:20 PM, Kristian H. Kristensen
wrote:
> Similar to struct drm_update_draw, struct drm_mode_fb_cmd2 has an
> unaligned 64 bit field (modifier). This get packed differently between
> 32 bit and 64 bit modes on architectures that can handle unaligned 64
> bit access (X86 and
drivers/gpu/drm/amd/amdgpu/../dal/amdgpu_dm/amdgpu_dm_types.c:827:59-60:
Unneeded semicolon
drivers/gpu/drm/amd/amdgpu/../dal/amdgpu_dm/amdgpu_dm_types.c:828:55-56:
Unneeded semicolon
drivers/gpu/drm/amd/amdgpu/../dal/amdgpu_dm/amdgpu_dm_types.c:829:57-58:
Unneeded semicolon
drivers/gpu/drm/amd/
tree: git://people.freedesktop.org/~agd5f/linux.git amd-staging-4.7
head: af8331c5eae54c760bd990e9c96966436451fec7
commit: a0dec5cf512edb0ba5f0b34d5b83d911a890fd5c [367/1327] drm/amdgpu: Use dal
driver for CZ
coccinelle warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/amd/amdgpu/../da
On Mon, 20 Jun 2016, James Bottomley
wrote:
> On Fri, 2016-06-17 at 16:06 -0700, James Bottomley wrote:
>> On Fri, 2016-06-17 at 16:34 +0300, Jani Nikula wrote:
>> > On Fri, 17 Jun 2016, Daniel Vetter wrote:
>> > > On Thu, Jun 16, 2016 at 03:42:12PM -0700, James Bottomley wrote:
>> > > > On Thu,
On Sun, 28 Aug 2016, Andrea Arcangeli wrote:
> I was bitten by this bug all last week while running latest kernels on
> my laptop at KVMForum.
>
> I then found the bug was also reported here:
>
> https://bugzilla.kernel.org/show_bug.cgi?id=151731
Fixed by
commit ea54ff4008892b46c7a3e6bc8ab8aaec9
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On Wed, 14 Sep 2016, Pavel Machek wrote:
> For the "sometimes need xrandr after resume": I don't think I can
> bisect that. It only happens sometimes :-(. But there's something
> helpful in the logs:
> [ 1856.218863] [drm:drm_edid_block_valid] *ERROR* EDID checksum is
> invalid, remainder is 130
On Tue, Sep 13, 2016 at 11:04:37PM +0200, Pavel Machek wrote:
> Hi!
>
> > I have
> >
> > 00:02.0 VGA compatible controller: Intel Corporation 4 Series Chipset
> > Integrated Graphics Controller (rev 03)
> >
> > In previous kernels, resume worked ok. With 4.8-rc1, I quite often (1
> > in 10 resum
Add New Vision Display 7.0" 800 RGB x 480 TFT LCD panel
Signed-off-by: Fabien Lahoudere
Acked-by: Rob Herring
---
.../devicetree/bindings/display/panel/nvd,9128.txt | 7 ++
.../devicetree/bindings/vendor-prefixes.txt| 1 +
drivers/gpu/drm/panel/panel-simple.c | 26 ++
On Tue, Sep 13, 2016 at 04:24:27PM -0700, Rafael Antognolli wrote:
> The refcount of a fence should be increased whenever it is added to a merged
> fence, since it will later be decreased when the merged fence is destroyed.
> Failing to do so will cause the original fence to be freed if the merged
2016-09-14 Chris Wilson :
> On Tue, Sep 13, 2016 at 04:24:27PM -0700, Rafael Antognolli wrote:
> > The refcount of a fence should be increased whenever it is added to a merged
> > fence, since it will later be decreased when the merged fence is destroyed.
> > Failing to do so will cause the origin
On Wed, 14 Sep 2016, Jani Nikula wrote:
> On Wed, 14 Sep 2016, Pavel Machek wrote:
>> Hi!
>>
>>> I have
>>>
>>> 00:02.0 VGA compatible controller: Intel Corporation 4 Series Chipset
>>> Integrated Graphics Controller (rev 03)
>>>
>>> In previous kernels, resume worked ok. With 4.8-rc1, I quite
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On Wed, 14 Sep 2016, Pavel Machek wrote:
> Hi!
>
>> I have
>>
>> 00:02.0 VGA compatible controller: Intel Corporation 4 Series Chipset
>> Integrated Graphics Controller (rev 03)
>>
>> In previous kernels, resume worked ok. With 4.8-rc1, I quite often (1
>> in 10 resumes?) get in state where prim
SiI8620 transmitter converts eTMDS/HDMI signal to MHL 3.0.
It is controlled via I2C bus. Its interaction with other
devices in video pipeline is performed mainly on HW level.
The only interaction it does on device driver level is
filtering-out unsupported video modes, it exposes drm_bridge
interfac
SiI8620 transmitter converts eTMDS/HDMI signal to MHL 3.0. It is controlled
via I2C bus.
Signed-off-by: Andrzej Hajda
Acked-by: Rob Herring
---
.../bindings/video/bridge/sil-sii8620.txt | 33 ++
1 file changed, 33 insertions(+)
create mode 100644
Documentation/dev
This header adds definitions specific to MHL protocol.
Signed-off-by: Andrzej Hajda
---
include/linux/mhl.h | 292
1 file changed, 292 insertions(+)
create mode 100644 include/linux/mhl.h
diff --git a/include/linux/mhl.h b/include/linux/mhl.
Hi,
This is 2nd RESEND of the patchset from Jan 2016.
There are no changes beside more informative log message about discovered dongle
and sink.
This patchset adds MHL bridge driver for Silicon Image SiI8620 chip.
The chip is quite powerful, supports MHL versions up to 3.0. It is present
in multi
Signed-off-by: Vincent Abriou
---
drivers/gpu/drm/sti/sti_hdmi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sti/sti_hdmi.c b/drivers/gpu/drm/sti/sti_hdmi.c
index c6aa291..d850dda 100644
--- a/drivers/gpu/drm/sti/sti_hdmi.c
+++ b/drivers/gpu/drm/sti/sti_hdmi.c
@@ -1054,6 +
On Wed 2016-09-14 10:38:18, Jani Nikula wrote:
> On Wed, 14 Sep 2016, Pavel Machek wrote:
> > Hi!
> >
> >> I have
> >>
> >> 00:02.0 VGA compatible controller: Intel Corporation 4 Series Chipset
> >> Integrated Graphics Controller (rev 03)
> >>
> >> In previous kernels, resume worked ok. With 4.8
re visually a little corrupted, that means,
the color of some pixel changed.
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On Tue 2016-09-13 22:38:45, Martin Steigerwald wrote:
> Hi.
>
> Am Dienstag, 13. September 2016, 22:23:50 CEST schrieb Pavel Machek:
> > I have
> >
> > 00:02.0 VGA compatible controller: Intel Corporation 4 Series Chipset
> > Integrated Graphics Controller (rev 03)
>
> 00:02.0 VGA compatible co
make the problem visibly disappear? If not, it sounds like it
might be a kernel driver issue.
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