As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15
must be programmed.
Enable bit 12 for programmable header packet.
Enable bit 15 for Y cordinate support.
v2: (Rodrigo)
- move CHICKEN_TRANS_EDP bit set logic right after setup_vsc
v3:(Rodrigo)
- initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of
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gave me a working SDDM again.
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|RESOLVED
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On Sat, Jan 07, 2017 at 11:42:04PM +0530, vathsala nagaraju wrote:
> As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15
> must be programmed.
> Enable bit 12 for programmable header packet.
> Enable bit 15 for Y cordinate support.
>
> v2: (Rodrigo)
> - move CHICKEN_TRANS_EDP bit set logic right after setu
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e.
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Extend the DSI PHY/PLL drivers to support the DSI 14nm PHY/PLL
found on 8x96.
These are picked up from the downstream driver. The PHY part is similar
to the other DSI PHYs. The PLL driver requires some trickery so that
one DSI PLL can drive both the DSIs (i.e, dual DSI mode).
In the case of dual
From: Hai Li
The 14nm DSI PHY on 8x96 (called PHY v2 downstream) requires a different
set of calculations for computing D-PHY timing params. Create a
timing_calc_v2 func for the newer v2 PHYs.
Signed-off-by: Hai Li
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 117 +
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/dsi/dsi.xml.h | 252 ++
1 file changed, 252 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h
b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index 4958594..234b3b3 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.x
From: Hai Li
Since DSI PHY has been a separate platform device, it should not
depend on the resources in host to be functional. This change is
to trigger PHY operations in manager, instead of host, so that
host and PHY can be completely separated.
Signed-off-by: Hai Li
Signed-off-by: Archit Tan
In case of dual DSI, some registers in PHY1 have been programmed
during PLL0 clock's set_rate. The PHY1 reset called by host1 later
will silently reset those PHY1 registers. This change is to reset
and enable both PHYs before any PLL clock operation.
[Originally worked on by Hai Li . Fixed up
by A
From: Hai Li
For some new types of DSI PHY, more settings depend on
use cases controlled by DSI manager. This change allows
DSI manager to setup PHY with a use case.
Signed-off-by: Hai Li
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/dsi/dsi.h | 8 +++
drivers/gpu/drm/msm/
From: Hai Li
The DSI host is required to configure more timings calculated
in PHY. By introducing a shared structure, this change allows
more timing information passed from PHY to host.
Signed-off-by: Hai Li
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/dsi/dsi.h | 13 +
Create an init() op for dsi_phy which sets up things specific to
a given DSI PHY.
The dsi_phy driver probe expects every DSI version to get a
"dsi_phy_regulator" mmio base. This isn't the case for 8x96.
Creating an init() op will allow us to accommodate such
differences.
Signed-off-by: Archit Tan
Add 8x96 DSI data in dsi_cfg. The downstream kernel's dsi_host driver
enables core_mmss_clk. We're seeing some branch clock warnings on
8x96 when enabling this. There doesn't seem to be any negative effect
with not enabling this clock, so use it once we figure out why we
get the warnings.
Signed-o
The driver returns an error if a DSI DT node is populated, but no device
is connected to it or if the data-lane map isn't present. Ideally, such
a DSI node shouldn't be probed at all (i.e, its status should be set to
"disabled in DT"), but there isn't any harm in registering the DSI device
even if
This set adds 8x96 PHY/PLL with Dual DSI mode supported too.
Dual DSI on 8x96 requires the DSI host/manager drivers to propagate
some usecase info to the PHY/PLL drivers. Hai Li had worked on
some patches in the past to implement this.
Tested on 8996 MTP Dual DSI panel, and with a LeMaker panel (
r the bug.
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From: Shawn Guo
Add a bit more document for function drm_crtc_from_index() to cross
link it with drm_crtc_from_index(), and explain that the function is
useful in vblank code.
While at it, add cross link comment for drm_plane_from_index() as well.
Signed-off-by: Shawn Guo
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Add DSI PHY 14nm domains for DSI PHY common, DSI PHY lane and
DSI PLL registers. Used in MSM8996.
Signed-off-by: Archit Taneja
---
rnndb/dsi/dsi.xml | 128 ++
1 file changed, 128 insertions(+)
diff --git a/rnndb/dsi/dsi.xml b/rnndb/dsi/dsi.xml
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re.
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s corectly
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https://bugzilla.kernel.org/show_bug.cgi?id=191281
--- Comment #2 from fin4478 at hotmail.com ---
Created attachment 250711
--> https://bugzilla.kernel.org/attachment.cgi?id=250711&action=edit
dmesg output with RX460
I have same errors with Gigabyte RX460 and
~agd5f/linux/log/drivers/gpu/drm/am
: .config.gz
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vel/attachments/20170107/ef410c2d/attachment.html>
Removing MMU configuration flag from DRM make few automatic
build failed when they answer yes to all flags.
Add asm/vga.h file on Blackfin architecture to not broke compilation.
Signed-off-by: Benjamin Gaignard
---
arch/blackfin/include/asm/vga.h | 1 +
drivers/gpu/drm/Kconfig
but GPU
shows same picture as on moment of freeze).
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get back to working mesa commit and reproduce the problem with
Xephyr now.
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Hi Eric,
could you please resend this patch [1], because it's still not applied in Linux
4.10-rc2.
Thanks
Stefan
[1] - https://patchwork.kernel.org/patch/9369793/
On Sat, Jan 7, 2017 at 9:57 AM, Benjamin Gaignard
wrote:
> Some SoC without MMU have display driver where a drm/kms driver
> could be implemented.
>
> Before doing such kind of thing drm/kms must allow to use mmuless devices.
> This patch propose to remove MMU configuration flag.
>
> For all drive
Some SoC without MMU have display driver where a drm/kms driver
could be implemented.
Before doing such kind of thing drm/kms must allow to use mmuless devices.
This patch propose to remove MMU configuration flag.
For all drivers selecting DRM_TTM add a dependency on MMU.
For blackfin architectu
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As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15
must be programmed.
Enable bit 12 for programmable header packet.
Enable bit 15 for Y cordinate support.
v2: (Rodrigo)
- move CHICKEN_TRANS_EDP bit set logic right after setup_vsc
v3:(Rodrigo)
- initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of
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On 04 January, 2017 21:39 CET, Rob Herring wrote:
> On Tue, Jan 3, 2017 at 5:34 PM, Peter Senna Tschudin
> wrote:
> > Hi Rob,
> >
> > Thank you for the review.
> >
> > On 03 January, 2017 23:51 CET, Rob Herring wrote:
> >
> >> On Sun, Jan 01, 2017 at 09:24:29PM +0100, Peter Senna Tschudin wr
Program EDP_PSR_DEBUG_CTL (PSR_MASK) to enable system
to go to deep sleep while in psr2.PSR2_STATUS bit 31:28
should report value 8 , if system enters deep sleep state.
Also, EDP_FRAMES_BEFORE_SU_ENTRY is set 1 , if not set,
flickering is observed on psr2 panel.
v2: (Ilia Mirkin)
- Remove duplica
As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15
must be programmed.
Enable bit 12 for programmable header packet.
Enable bit 15 for Y cordinate support.
v2: (Rodrigo)
- move CHICKEN_TRANS_EDP bit set logic right after setup_vsc
v3:(Rodrigo)
- initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of
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