On Thu, 04 May 2017, SF Markus Elfring wrote:
> From: Markus Elfring
> Date: Thu, 4 May 2017 13:40:53 +0200
>
> Do not use curly brackets at some source code places
> where a single statement should be sufficient.
We only tend to do
On Thu, 04 May 2017, Chris Wilson wrote:
> On Thu, May 04, 2017 at 06:54:16PM +0200, SF Markus Elfring wrote:
>> From: Markus Elfring
>> Date: Thu, 4 May 2017 13:20:47 +0200
>>
>> Some strings which did not contain data format
On Thu, 04 May 2017, SF Markus Elfring wrote:
> From: Markus Elfring
> Date: Thu, 4 May 2017 14:04:38 +0200
>
> Use space characters at some source code places according to
> the Linux coding style convention.
LGTM. Frankly the only
On Thu, 04 May 2017, SF Markus Elfring wrote:
> From: Markus Elfring
> Date: Thu, 4 May 2017 13:52:19 +0200
> MIME-Version: 1.0
> Content-Type: text/plain; charset=UTF-8
> Content-Transfer-Encoding: 8bit
>
> The script “checkpatch.pl”
On Thu, May 04, 2017 at 09:12:32PM +0100, Chris Wilson wrote:
> On Thu, May 04, 2017 at 06:59:23PM +0200, SF Markus Elfring wrote:
> > From: Markus Elfring
> > Date: Thu, 4 May 2017 14:15:00 +0200
> >
> > The script "checkpatch.pl" pointed information out like the
On Thu, 2017-05-04 at 21:25 +0100, Chris Wilson wrote:
> On Thu, May 04, 2017 at 11:45:48AM -0700, Laura Abbott wrote:
> >
> > Enable the GEM dma-buf import interfaces in addition to the export
> > interfaces. This lets vgem be used as a test source for other allocators
> > (e.g. Ion).
> >
> >
Hi Linus,
Small supplementary pull request. I didn't want anyone saying we snuck
this in in a the middle of a big pile of changes, so here is a clearly
separate pull request documenting the code of conduct introduced for
freedesktop.org and how it relates to dri-devel community.
Dave.
The
Hi Linus,
I missed a pull request from Thierry, this stuff has been in
linux-next for a while anyways.
It does contain a branch from the iommu tree, but Thierry said it
should be fine.
Dave.
The following changes since commit 8b03d1ed2c43a2ba5ef3381322ee4515b97381bf:
Merge branch
https://bugs.freedesktop.org/show_bug.cgi?id=100892
Marek Olšák changed:
What|Removed |Added
Resolution|--- |FIXED
As we are going to add support for the Allwinner DE2 engine in sun4i-drm
driver, we will finally have two types of display engines -- the DE1
backend and the DE2 mixer. They both do some display blending and feed
graphics data to TCON, so I choose to call them both "engine" here.
Abstract the
The "Display Engine 2.0" in Allwinner newer SoCs contains a clock
management unit for its subunits, like the DE CCU in A80.
Add a sunxi-ng style driver for it.
Signed-off-by: Icenowy Zheng
---
Changes in v5:
- Removed dt-bindings headers (they're now in patch 1).
Changes in v4:
Hi Ville,
On 04-05-2017 15:32, Ville Syrjälä wrote:
> On Thu, May 04, 2017 at 03:11:39PM +0100, Jose Abreu wrote:
>> This changes the connector probe helper function to use the new
>> encoder->mode_valid() and crtc->mode_valid() helper callbacks to
>> validate the modes.
>>
>> The new callbacks
As we are going to add support for the Allwinner DE2 Mixer in sun4i-drm
driver, we will finally have two types of layers.
Each layer is bound to a drm_plane that is CRTC-specific, so we create
them when initializing CRTC (calling sun4i_layers_init, which will be
generalized in next patch). The
Allwinner have a new "Display Engine 2.0" in their new SoCs, which comes
with mixers to do graphic processing and feed data to TCON, like the old
backends and frontends.
Add support for the mixer on Allwinner V3s SoC; it's the simplest one.
Currently a lot of functions are still missing -- more
Allwinner "Display Engine 2.0" contains some clock controls in it.
In order to add them as clock drivers, we need a device tree binding.
Add the binding here.
Also add the device tree binding headers.
Signed-off-by: Icenowy Zheng
Acked-by: Rob Herring
---
This series is a follow up from the discussion at [1]. We start by
introducing crtc->mode_valid(), encoder->mode_valid() and
bridge->mode_valid() callbacks which will be used in followup
patches.
Next, at 2/5 we modify the connector probe helper so that only modes
which are supported by a given
Thanks Neil.
On Thu, 2017-05-04 at 09:55 +0200, Neil Armstrong wrote:
> On 04/25/2017 04:06 AM, hean.loong@intel.com wrote:
> >
> > From: "Ong, Hean Loong"
> >
> > Device tree binding for Intel FPGA Video and Image
> > Processing Suite. The binding involved would
On 05/04/2017 01:53 PM, agheorghe wrote:
The vsp2 hw supports changing of the alpha of pixels that match a color
key, this patch adds support for this feature in order to be used by
the rcar-du driver.
The colorkey is interpreted different depending of the pixel format:
* RGB - all
Allwinner V3s SoC features a "Display Engine 2.0" with only one TCON
which have RGB LCD output.
Add device nodes for it as well as the TCON.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 87
1 file changed, 87
在 2017-05-04 21:05,Maxime Ripard 写道:
On Thu, May 04, 2017 at 07:48:53PM +0800, Icenowy Zheng wrote:
Allwinner have a new "Display Engine 2.0" in their new SoCs, which
comes
with mixers to do graphic processing and feed data to TCON, like the
old
backends and frontends.
Add support for the
On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> Even though that mux is undocumented, it seems like it needs to be set to 1
> when using composite, and 0 when using HDMI.
>
> Signed-off-by: Maxime Ripard
Acked-by:
On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> The muxing can actually happen on both channels on some SoCs, so it makes
> more sense to just move it out of the sun4i_tcon1_mode_set function and
> create a separate function that needs to be called by the
The "Display Engine 2.0" in Allwinner newer SoCs contains a clock
management unit for its subunits, like the DE CCU in A80.
Add a sunxi-ng style driver for it.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/Kconfig | 5 +
drivers/clk/sunxi-ng/Makefile|
Christian König writes:
> Am 27.04.2017 um 18:17 schrieb Nikola Pajkovsky:
>> This is super simple elimination of else branch and I should
>> probably even use unlikely in
>>
>> if (ring->count_dw < count_dw) {
>>
>> However, amdgpu_ring_write() has similar if
在 2017-05-04 21:05,Maxime Ripard 写道:
On Thu, May 04, 2017 at 07:48:53PM +0800, Icenowy Zheng wrote:
Allwinner have a new "Display Engine 2.0" in their new SoCs, which
comes
with mixers to do graphic processing and feed data to TCON, like the
old
backends and frontends.
Add support for the
Hi Daniel,
On 03-05-2017 16:00, Daniel Vetter wrote:
> On Wed, May 03, 2017 at 03:16:13PM +0100, Jose Abreu wrote:
>> Hi Daniel,
>>
>>
>> On 03-05-2017 07:19, Daniel Vetter wrote:
>>> On Tue, May 2, 2017 at 11:29 AM, Jose Abreu wrote:
On 02-05-2017 09:48, Daniel
在 2017-05-05 00:57,icen...@aosc.io 写道:
在 2017-05-05 00:50,icen...@aosc.io 写道:
在 2017-05-04 21:05,Maxime Ripard 写道:
On Thu, May 04, 2017 at 07:48:53PM +0800, Icenowy Zheng wrote:
Allwinner have a new "Display Engine 2.0" in their new SoCs, which
comes
with mixers to do graphic processing and
A 480x272 QiaoDian QD43003C0-40-7LED panel is available from Lichee Pi.
This commit connects this panel to Lichee Pi Zero.
Lichee Pi also provides a 800x480 panel without accurate model number,
so do not merge this patch. It will finally come as device tree overlay.
Signed-off-by: Icenowy Zheng
On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> The A10s Olinuxino has an HDMI connector. Make sure we can use it.
>
> Acked-by: Chen-Yu Tsai
> Signed-off-by: Maxime Ripard
> ---
>
I'm sorry that some patch from this version is wrongly sent
without decorations.
This patchset is the initial patchset for Allwinner DE2 support.
It contains the support of clocks in DE2 and the mixers in DE2.
The SoC used to develop this patchset is V3s, as V3s is the simplest
one of the SoCs
As we are going to add support for the Allwinner DE2 Mixer in sun4i-drm
driver, we will finally have two types of layers.
Each layer is bound to a drm_plane that is CRTC-specific, so we create
them when initializing CRTC (calling sun4i_layers_init, which will be
generalized in next patch). The
Hi Daniel,
On 03-05-2017 07:19, Daniel Vetter wrote:
> On Tue, May 2, 2017 at 11:29 AM, Jose Abreu wrote:
>> On 02-05-2017 09:48, Daniel Vetter wrote:
>>> On Wed, Apr 26, 2017 at 11:48:34AM +0100, Jose Abreu wrote:
Some crtc's may have restrictions in the mode they
On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> The A10s has an HDMI controller connected to the second TCON channel. Add
> it to our DT.
>
> Since the TV Encoder was the only channel 1 user so far, also add the
> property now that we have several users.
>
Some panel will default to zero brightness when turning the
panel off and on again. This patch restores last brightness
level back when panel is turning back on.
Signed-off-by: Puthikorn Voravootivat
---
drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 1 +
1 file changed, 1
On 05/04/2017 11:42 AM, Ville Syrjälä wrote:
> On Thu, May 04, 2017 at 09:26:09AM -0600, Jens Axboe wrote:
>> Hi,
>>
>> Running current -git on my laptop (20FB, X1 Carbon gen4, skylake), I get
>> a lot of the below warnings. Things seem to work fine (in fact it seems
>> faster in general use than
On Wed, 2017-05-03 at 13:34 -0700, Eric Anholt wrote:
> hean.loong@intel.com writes:
>
> >
> > From: "Ong, Hean Loong"
> >
> > Driver for Intel FPGA Video and Image Processing
> > Suite Frame Buffer II. The driver only supports the Intel
> > Arria10 devkit and its
Introduce a new helper function which calls mode_valid() callback
for all bridges in an encoder chain.
Signed-off-by: Jose Abreu
Cc: Carlos Palminha
Cc: Alexey Brodkin
Cc: Ville Syrjälä
Cc:
On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> Both TCON channels need to have the resolution doubled, since the size the
> hardware is going to use is whatever we put in the register divided by two.
>
> However, we handle it differently for the two
Allwinner V3s SoC features a set of pins that have functionality of RGB
LCD, the pins are at different pin ban than other SoCs.
Add pinctrl node for them.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 9 +
1 file changed, 9 insertions(+)
diff
This changes the connector probe helper function to use the new
encoder->mode_valid() and crtc->mode_valid() helper callbacks to
validate the modes.
The new callbacks are optional so the behaviour remains the same
if they are not implemented. If they are, then the code loops
through all the
Allwinner V3s SoC have a display engine which have a different pipeline
with older SoCs.
Add document for it (new compatibles and the new "mixer" part).
Signed-off-by: Icenowy Zheng
Acked-by: Rob Herring
---
.../bindings/display/sunxi/sun4i-drm.txt
Hi Ville,
On 04-05-2017 15:40, Ville Syrjälä wrote:
> On Thu, May 04, 2017 at 03:11:41PM +0100, Jose Abreu wrote:
>> This patches makes use of the new mode_valid() callbacks introduced
>> previously to validate the full video pipeline when modesetting.
>>
>> This calls the
This patch adds the following definition
- Bit mask for EDP_PWMGEN_BIT_COUNT and min/max cap
register which only use bit 0:4
- Base frequency (27 MHz) for backlight PWM frequency
generator.
Signed-off-by: Puthikorn Voravootivat
---
include/drm/drm_dp_helper.h | 2 ++
1
On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> The current function name is a bit confusing, and doesn't really allow to
> create an explicit function to reverse the operation.
>
> We also for now change the parent rate through a pointer, while we don't
>
Allwinner V3s SoC features a TCON without channel 1.
Add support for it.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 3 ++-
drivers/gpu/drm/sun4i/sun4i_tcon.c | 5 +
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git
This patches makes use of the new mode_valid() callbacks introduced
previously to validate the full video pipeline when modesetting.
This calls the connector->mode_valid(), encoder->mode_valid(),
bridge->mode_valid() and crtc->mode_valid() so that we can
make sure that the mode will be accepted
Allwinner V3s SoC have a display engine which have a different pipeline
with older SoCs.
Add document for it (new compatibles and the new "mixer" part).
Signed-off-by: Icenowy Zheng
Acked-by: Rob Herring
---
Changes in v4:
- Removed the refactor at TCON
On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> divider_round_rate already evaluates changing the parent rate if
^^^ Might want to update this, as you are now using the new function
you added in patch 1.
> CLK_SET_RATE_PARENT is set. Now that we
On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> The earlier Allwinner SoCs (A10, A10s, A20, A31) have an embedded HDMI
> controller.
>
> That HDMI controller is able to do audio and CEC, but those have been left
> out for now.
>
> Signed-off-by: Maxime
alpha:allmodconfig fails to build as follows.
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1006:2: error:
expected identifier before '(' token
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1011:28: error:
'NGG_BUF_MAX' undeclared here
The problem is not really the enum definition of NGG_BUF_MAX but
else branch is pointless if it's right at the end of function and use
unlikely() on err path.
Signed-off-by: Nikola Pajkovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 45 +++--
1 file changed, 23 insertions(+), 22 deletions(-)
diff --git
Now that we have a callback to check if crtc supports a given mode
we can use it in arcpgu so that we restrict the number of probbed
modes to the ones we can actually display.
This is specially useful because arcpgu crtc is responsible to set
a clock value in the commit() stage but unfortunatelly
On Wed, 2017-05-03 at 13:28 -0700, Eric Anholt wrote:
> hean.loong@intel.com writes:
>
> >
> > From: Ong Hean Loong
> >
> > Hi,
> >
> > The new Intel Arria10 SOC FPGA devkit has a Display Port IP
> > component
> > which requires a new driver. This is a virtual
Read desired PWM frequency from panel vbt and calculate the
value for divider in DPCD address 0x724 and 0x728 to match
that frequency as close as possible.
Signed-off-by: Puthikorn Voravootivat
---
drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 71
Add option to allow choosing how to adjust brightness if
panel supports both PWM pin and AUX channel.
Signed-off-by: Puthikorn Voravootivat
---
drivers/gpu/drm/i915/i915_params.c| 6 --
drivers/gpu/drm/i915/i915_params.h| 2 +-
On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> The video PLLs are used directly by the HDMI controller. Export them so
> that we can use them in our DT node.
>
> Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
This patch set contain 9 patches.
- First five patches fix bug in the driver and allow choosing which
way to adjust brightness if both PWM pin and AUX are supported
- Next patch adds enable DBC by default
- Next patch makes the driver restore last brightness level after
turning display off and
This patch enables dynamic backlight by default for eDP
panel that supports this feature via DPCD register and
set minimum / maximum brightness to 0% and 100% of the
normal brightness.
Signed-off-by: Puthikorn Voravootivat
---
drivers/gpu/drm/i915/intel_dp_aux_backlight.c |
On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> Currently, the parent rate given back to the clock framework in our
> request is the original parent rate we calculated before trying to round
> the rate of our clock.
>
> This works fine unless our clock
On Tue, Mar 7, 2017 at 4:56 PM, Maxime Ripard
wrote:
> One of the possible output of the display pipeline, on the SoCs that have
> it, is the HDMI controller.
>
> Add a binding for it.
>
> Signed-off-by: Maxime Ripard
> ---
>
Allwinner "Display Engine 2.0" contains some clock controls in it.
In order to add them as clock drivers, we need a device tree binding.
Add the binding here.
Also add the device tree binding headers.
Signed-off-by: Icenowy Zheng
Acked-by: Rob Herring
---
On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> It appears that the total vertical resolution needs to be doubled when
> we're not in interlaced. Make sure that is the case.
I think the total vertical resolution needs to be doubled in all cases.
It just
intel_dp_aux_backlight driver should check for the
DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP before enable the driver.
Signed-off-by: Puthikorn Voravootivat
---
drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff
As sun4i-backend is now a dedicated module, add an Kconfig option for
it to make it optional, since some build may only use other engines.
Signed-off-by: Icenowy Zheng
---
Splited out patch.
drivers/gpu/drm/sun4i/Kconfig | 10 ++
drivers/gpu/drm/sun4i/Makefile | 2 +-
This adds a new callback to crtc, encoder and bridge helper functions
called mode_valid(). This callback shall be implemented if the
corresponding component has some sort of restriction in the modes
that can be displayed. A NULL callback implicates that the component
can display all the modes.
On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> The current code only rely on the parent to change its rate in the case
> where CLK_SET_RATE_PARENT is set.
>
> However, some clock rates might be obtained only through a modification of
> the parent and the
Allwinner V3s features the new "Display Engine 2.0", which can now also
be driven with our subdrivers in sun4i-drm.
Add the compatible string for in sun4i_drv.c, in order to make the
display engine and its components probed.
Signed-off-by: Icenowy Zheng
---
Hi Daniel,
On 04-05-2017 11:21, Jose Abreu wrote:
> Hi Daniel,
>
>
> On 03-05-2017 16:00, Daniel Vetter wrote:
>> On Wed, May 03, 2017 at 03:16:13PM +0100, Jose Abreu wrote:
>>> Hi Daniel,
>>>
>>>
>>> On 03-05-2017 07:19, Daniel Vetter wrote:
On Tue, May 2, 2017 at 11:29 AM, Jose Abreu
Currently the direct call from CRTC code to layer code has disappeared,
instead the layer's init function is called via the backend's ops.
Add a dedicated module for sun4i-backend and sun4i-layer, and drop the
EXPORT_SYMBOL from backend code to layer code.
Signed-off-by: Icenowy Zheng
There are some panel that
(1) does not support display backlight enable via AUX
(2) support display backlight adjustment via AUX
(3) support display backlight enable via eDP BL_ENABLE pin
The current driver required that (1) must be support to enable (2).
This patch drops that requirement.
在 2017-05-05 00:50,icen...@aosc.io 写道:
在 2017-05-04 21:05,Maxime Ripard 写道:
On Thu, May 04, 2017 at 07:48:53PM +0800, Icenowy Zheng wrote:
Allwinner have a new "Display Engine 2.0" in their new SoCs, which
comes
with mixers to do graphic processing and feed data to TCON, like the
old
On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> The generic connectors such as hdmi-connector doesn't have any driver in,
> so if they are added to the component list, we will be waiting forever for
> a non-existing driver to probe.
>
> Add a list of the
On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> The clocks might need to modify their parent clocks. In order to make that
> possible, give them access to the parent clock being evaluated, and to a
> pointer to the parent rate so that they can modify it if
On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> The pre-divider retrieval code was merged into the function to apply the
> current pre-divider onto the parent clock rate so that we can use that
> adjusted value to do our factors computation.
>
> However,
On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> So far, divider_round_rate only considers the parent clock returned by
> clk_hw_get_parent.
>
> This works fine on clocks that have a single parents, this doesn't work on
> muxes, since we will only consider
intel_dp_aux_enable_backlight() assumed that the register
BACKLIGHT_BRIGHTNESS_CONTROL_MODE can only has value 01
(DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET) when initialize.
This patch fixed that by handling all cases of that register.
Signed-off-by: Puthikorn Voravootivat
---
We should set backlight mode register before set register to
enable the backlight.
Signed-off-by: Puthikorn Voravootivat
---
drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
https://bugs.freedesktop.org/show_bug.cgi?id=100936
--- Comment #1 from Marek Olšák ---
Yeah I noticed that Unigine Heaven looks very gay now. :) This Samuel's patch
should fix it: "st/glsl_to_tgsi: fix the DCE pass in presence of loops"
--
You are receiving this mail
https://bugs.freedesktop.org/show_bug.cgi?id=100892
Greg White changed:
What|Removed |Added
Priority|medium |highest
--
You are
On Thu, May 04, 2017 at 02:52:09PM -0600, Daniel Drake wrote:
> On Thu, May 4, 2017 at 2:37 PM, Ville Syrjälä
> wrote:
> > Please check if commit bb1d132935c2 ("drm/i915/vbt: split out defaults
> > that are set when there is no VBT") fixes things for you.
>
> I
On Thu, May 04, 2017 at 10:48:10PM +0200, SF Markus Elfring wrote:
> >> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> >> @@ -1529,8 +1529,8 @@ static int gen6_drpc_info(struct seq_file *m)
> >>
> >>forcewake_count =
> >> READ_ONCE(dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count);
>
https://bugs.freedesktop.org/show_bug.cgi?id=100937
Bug ID: 100937
Summary: Mesa fails to build with GCC 4.8
Product: Mesa
Version: git
Hardware: Other
OS: All
Status: NEW
Severity: normal
On Thu, May 4, 2017 at 2:37 PM, Ville Syrjälä
wrote:
> Please check if commit bb1d132935c2 ("drm/i915/vbt: split out defaults
> that are set when there is no VBT") fixes things for you.
I think this is not going to help. This would only make a difference
when there
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -1529,8 +1529,8 @@ static int gen6_drpc_info(struct seq_file *m)
>>
>> forcewake_count =
>> READ_ONCE(dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count);
>> if (forcewake_count) {
>> -seq_puts(m, "RC information
On Thu, May 04, 2017 at 02:21:26PM -0600, Daniel Drake wrote:
> Hi,
>
> Numerous Asus desktops and All-in-one computers (e.g. D520MT) have a
> regression on Linux 4.9 where the VGA output is shown all-white.
>
> This is a regression caused by:
>
> commit 0ce140d45a8398b501934ac289aef0eb7f47c596
On Thu, May 04, 2017 at 11:45:48AM -0700, Laura Abbott wrote:
>
> Enable the GEM dma-buf import interfaces in addition to the export
> interfaces. This lets vgem be used as a test source for other allocators
> (e.g. Ion).
>
> Reviewed-by: Chris Wilson
> Signed-off-by:
On Thu, May 04, 2017 at 11:45:46AM -0700, Laura Abbott wrote:
>
> The vgem driver is currently registered independent of any actual
> device. Some usage of the dmabuf APIs require an actual device structure
> to do anything. Register a dummy platform device for use with dmabuf.
>
> Reviewed-by:
Hi,
Numerous Asus desktops and All-in-one computers (e.g. D520MT) have a
regression on Linux 4.9 where the VGA output is shown all-white.
This is a regression caused by:
commit 0ce140d45a8398b501934ac289aef0eb7f47c596
Author: Ville Syrjälä
Date: Tue Oct 11
On Thu, May 04, 2017 at 11:45:47AM -0700, Laura Abbott wrote:
>
> The existing drm_gem_prime_import function uses the underlying
> struct device of a drm_device for attaching to a dma_buf. Some drivers
> (notably vgem) may not have an underlying device structure. Offer
> an alternate function to
On Thu, May 04, 2017 at 06:59:23PM +0200, SF Markus Elfring wrote:
> From: Markus Elfring
> Date: Thu, 4 May 2017 14:15:00 +0200
>
> The script "checkpatch.pl" pointed information out like the following.
>
> WARNING: quoted string split across lines
>
> Thus fix
On Thu, May 04, 2017 at 06:54:16PM +0200, SF Markus Elfring wrote:
> From: Markus Elfring
> Date: Thu, 4 May 2017 13:20:47 +0200
>
> Some strings which did not contain data format specifications should be put
> into a sequence. Thus use the corresponding function
https://bugzilla.kernel.org/show_bug.cgi?id=195659
--- Comment #1 from Michal Suchánek (msucha...@suse.de) ---
Created attachment 256205
--> https://bugzilla.kernel.org/attachment.cgi?id=256205=edit
kernel log excerpt
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You are receiving this mail because:
You are watching the assignee of
https://bugzilla.kernel.org/show_bug.cgi?id=195659
Bug ID: 195659
Summary: nouveau fence error
Product: Drivers
Version: 2.5
Kernel Version: 4.10
Hardware: All
OS: Linux
Tree: Mainline
Status: NEW
https://bugs.freedesktop.org/show_bug.cgi?id=100936
Bug ID: 100936
Summary: Radeonsi rendering corruption in unigine heaven
(regression bissected)
Product: Mesa
Version: git
Hardware: All
OS: Linux (All)
The existing drm_gem_prime_import function uses the underlying
struct device of a drm_device for attaching to a dma_buf. Some drivers
(notably vgem) may not have an underlying device structure. Offer
an alternate function to attach using any available device structure.
Signed-off-by: Laura
Enable the GEM dma-buf import interfaces in addition to the export
interfaces. This lets vgem be used as a test source for other allocators
(e.g. Ion).
Reviewed-by: Chris Wilson
Signed-off-by: Laura Abbott
---
v4: Use new drm_gem_prime_import_dev
Hi,
This v4 of the series to add dma_buf import functions for vgem. This version
primarily focuses on adding a new approach for an alternate dma_buf attach
after platformdev was removed.
Thanks,
Laura
Laura Abbott (3):
drm/vgem: Add a dummy platform device
drm/prime: Introduce
The vgem driver is currently registered independent of any actual
device. Some usage of the dmabuf APIs require an actual device structure
to do anything. Register a dummy platform device for use with dmabuf.
Reviewed-by: Chris Wilson
Signed-off-by: Laura Abbott
Pekka Paalanen writes:
> Ooh, a much much larger scope than I assumed. Nice.
Well, it's more out of a sense of fear than future planning. If all we
ever use it for is as a list of monitors that the desktop should ignore,
that'd be fine.
> That means you need an explicit
On 4 May 2017 at 17:39, Adam Jackson wrote:
> AC_HEADER_MAJOR only defines MAJOR_IN_SYSMACROS if major() is _not_
> defined by alone. It is, but it warns, and that's ugly.
> To fix this, push -Werror into CFLAGS when invoking AC_HEADER_MAJOR so
> the warning makes the
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