This patch convert meson stmmac glue driver to use all xxxsetbits_le32
functions.
Signed-off-by: Corentin Labbe
Reviewed-by: Neil Armstrong
---
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 56 ---
1 file changed, 22 insertions(+), 34 deletions(-)
diff --git a/drivers/net/et
This patch convert meson DRM driver to use all xxxsetbits_le32 functions.
Signed-off-by: Corentin Labbe
Reviewed-by: Neil Armstrong
Tested-by: Neil Armstrong
---
drivers/gpu/drm/meson/meson_crtc.c | 14 +++---
drivers/gpu/drm/meson/meson_dw_hdmi.c | 33 +++--
drivers/gpu/drm/mes
This patch adds support for the Armadeus ST0700 Adapt. It comes with a
Santek ST0700I5Y-RBSLW 7.0" WVGA (800x480) TFT and an adapter board so
that it can be connected on the TFT header of Armadeus Dev boards.
Signed-off-by: Sébastien Szymanski
---
.../display/panel/armadeus,st0700-adapt.txt
Since setbits32/clrbits32 work on be32, it's better to remove ambiguity on
the used data type.
Signed-off-by: Corentin Labbe
---
arch/powerpc/include/asm/fsl_lbc.h| 2 +-
arch/powerpc/include/asm/io.h | 4 +-
arch/powerpc/platforms/44x/canyonlands.c | 4 +-
ar
Hello
This patchset adds a new set of functions which are open-coded in lot of
place.
Basicly the pattern is always the same, "read, modify a bit, write"
some driver and the powerpc arch already have thoses pattern them as functions.
(like ahci_sunxi.c or dwmac-meson8b)
The first patch rename so
On Wed, 24 Oct 2018 07:35:48 +, Corentin Labbe wrote:
> This patch adds setbits_le32/clrbits_le32/clrsetbits_le32 and
> setbits_le64/clrbits_le64/clrsetbits_le64 in linux/setbits.h header.
>
> Signed-off-by: Corentin Labbe
Did you have a look at all the functions defined in bitfield.h?
(incl
This patch add a spatch which convert all open coded of
setbits_le32/clrbits_le32/clrsetbits_le32
and their 64 bits counterparts.
Note that 64 and 32_relaxed are generated via
cp scripts/coccinelle/misc/setbits32.cocci
scripts/coccinelle/misc/setbits32_relaxed.cocci
sed -i 's,readl,readl_relaxed
This patch convert dwmac-sun8i driver to use all xxxsetbits_le32 functions.
Signed-off-by: Corentin Labbe
---
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 62 +--
1 file changed, 16 insertions(+), 46 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
To make use of the new eLCDIF DRM driver OF graph description is
required. Describe the display using OF graph nodes.
Signed-off-by: Sébastien Szymanski
---
arch/arm/boot/dts/imx6ul-opos6uldev.dts | 37 ++---
1 file changed, 16 insertions(+), 21 deletions(-)
diff --g
This patch adds setbits_le32/clrbits_le32/clrsetbits_le32 and
setbits_le64/clrbits_le64/clrsetbits_le64 in linux/setbits.h header.
Signed-off-by: Corentin Labbe
---
include/linux/setbits.h | 84 +
1 file changed, 84 insertions(+)
create mode 100644 includ
This patch converts ahci_sunxi to use xxxsetbits_le32 functions
Signed-off-by: Corentin Labbe
---
drivers/ata/ahci_sunxi.c | 62 +++-
1 file changed, 17 insertions(+), 45 deletions(-)
diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
index 9117
Am 25.10.18 um 03:28 schrieb Zhou, David(ChunMing):
Reviewed-by: Chunming Zhou
NAK, GFP_ATOMIC should be avoided.
The correct solution is to move the allocation out of the spinlock or
drop the lock and reacquire.
Christian.
-Original Message-
From: Julia Lawall
Sent: Thursday,
Op 24-10-18 om 19:17 schreef Matt Roper:
> On Tue, Oct 23, 2018 at 01:39:10PM +0200, Maarten Lankhorst wrote:
>>
>> Op 02-10-18 om 13:15 schreef Stanislav Lisovskiy:
>>> PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
>>> specification.
>>>
>>> v2: Edited commit message, removed r
https://bugs.freedesktop.org/show_bug.cgi?id=108521
--- Comment #12 from Robert Strube ---
Created attachment 142187
--> https://bugs.freedesktop.org/attachment.cgi?id=142187&action=edit
dmesg log booting system *without* eGPU
So I decided to do a sanity check and completely remove the eGPU fr
https://bugs.freedesktop.org/show_bug.cgi?id=108521
--- Comment #11 from Robert Strube ---
I disabled a bunch of devices in the BIOS (sound, SD card reader, etc.) and I
confirmed that they are no longer showing up in lspci, but I'm still getting
the same error.
I also found one suggestion to pas
https://bugs.freedesktop.org/show_bug.cgi?id=108521
--- Comment #10 from Alex Deucher ---
(In reply to Robert Strube from comment #9)
> Any suggestion for how I can increase the MMIO space for the BARs on the
> Thunderbolt bridges? Should I try to disable additional devices in the BIOS,
> etc.?
https://bugs.freedesktop.org/show_bug.cgi?id=108521
--- Comment #9 from Robert Strube ---
Any suggestion for how I can increase the MMIO space for the BARs on the
Thunderbolt bridges? Should I try to disable additional devices in the BIOS,
etc.? I'm a little out of my element here.
Thanks!
Rob
https://bugs.freedesktop.org/show_bug.cgi?id=108521
--- Comment #8 from Alex Deucher ---
There does not seem to be enough MMIO space for the BARs on the thunderbolt
bridges:
[0.436946] pci :04:00.0: BAR 13: no space for [io size 0x4000]
[0.436947] pci :04:00.0: BAR 13: failed to
Reviewed-by: Chunming Zhou
> -Original Message-
> From: Julia Lawall
> Sent: Thursday, October 25, 2018 2:57 AM
> To: Zhou, David(ChunMing)
> Cc: kbuild-...@01.org; intel-...@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org; Christian König
> ; Gustavo Padovan
> ; Maarten Lankh
https://bugs.freedesktop.org/show_bug.cgi?id=108096
--- Comment #12 from Dieter Nützel ---
(In reply to Alex Deucher from comment #11)
> Can you bisect 4.19?
Well, I'll try that, too.
I'm currently trying amd-staging-drm-next, again.
Have some trouble with 4.19 final on my main home server (32 b
https://bugs.freedesktop.org/show_bug.cgi?id=108521
--- Comment #7 from Robert Strube ---
Thanks for the suggestions! I took your advice and commented out the Vega M
device IDs located here: /drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
These are the lines of code that I commented out.
/* VEGAM */
{0
https://bugs.freedesktop.org/show_bug.cgi?id=108521
--- Comment #6 from Robert Strube ---
Created attachment 142182
--> https://bugs.freedesktop.org/attachment.cgi?id=142182&action=edit
dmesg log booting system with eGPU (Vega M device IDs removed in kernel)
--
You are receiving this mail bec
https://bugs.freedesktop.org/show_bug.cgi?id=108096
--- Comment #11 from Alex Deucher ---
Can you bisect 4.19?
--
You are receiving this mail because:
You are the assignee for the bug.___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://
https://bugs.freedesktop.org/show_bug.cgi?id=108464
--- Comment #7 from Alex Deucher ---
(In reply to Duncan Roe from comment #6)
> (In reply to Duncan Roe from comment #3)
> > halt is fine btw, it's only reboot that breaks.
> > Do you want extra debug turned on for dmesg?
>
> At Linux 19.0-rc8,
Gah, the more I think about this the more I realize this was never the correct
approach to begin with. I wrote this patch a long time ago when I wasn't
nearly as experienced, so that's not terribly surprising.
So: the thing is this isn't actually a problem that's specific to MST. Pretty
much all o
On Fri, Oct 12, 2018 at 11:42:32AM -0700, Radhakrishna Sripada wrote:
> At times 12bpc HDMI cannot be driven due to faulty cables, dongles
> level shifters etc. To workaround them we may need to drive the output
> at a lower bpc. Currently the user space does not have a way to limit
> the bpc. The
On Wed, 2018-10-24 at 18:09 -0400, Lyude Paul wrote:
> Since there's going to be quite a number of changes I need to make to
> this I'm
> just going to make the changes myself! I'll make sure to Cc you with
> the
> respin
Sounds good, thanks for picking it up!
Juston
https://bugs.freedesktop.org/show_bug.cgi?id=108464
--- Comment #6 from Duncan Roe ---
(In reply to Duncan Roe from comment #3)
> halt is fine btw, it's only reboot that breaks.
> Do you want extra debug turned on for dmesg?
At Linux 19.0-rc8, power button / halt command also fails. The backligh
On Thu, Oct 11, 2018, 1:19 PM Abhinav Kumar wrote:
> Fix the dsi clock names in the DSI 10nm PLL driver to
> match the names in the dispcc driver as those are
> according to the clock plan of the chipset.
>
> Changes in v2:
> - Update the clock diagram with the new clock name
>
> Signed-off-by: A
On Wed, 2018-10-24 at 15:28 -0700, Manasi Navare wrote:
> DSC can be supported per DP connector. This patch adds a per connector
> debugfs node to expose DSC support capability by the kernel.
> The same node can be used from userspace to force DSC enable.
>
> v2:
> * Use kstrtobool_from_user to av
DSC can be supported per DP connector. This patch adds a per connector
debugfs node to expose DSC support capability by the kernel.
The same node can be used from userspace to force DSC enable.
v2:
* Use kstrtobool_from_user to avoid explicit error checking (Lyude)
* Rebase on drm-tip (Manasi)
Cc
On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.
v3:
* Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville)
* Move it around TRANSCODER power domain defs (Ville)
v2:
* Fix the power well mismatch CI er
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc params
* Add a condition to disable only if
dsc state co
DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.
v2:
* Rebase ond drm-tip
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Man
This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.
DSC params like the enable, compressed bpp, slice count and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the remaining
From: "Srivatsa, Anusha"
DSC has some Rate Control values that remain constant
across all configurations. These are as per the DSC
standard.
v3:
* Define them in drm_dsc.h as they are
DSC constants (Manasi)
v2:
* Add DP_DSC_ prefix (Jani Nikula)
Cc: dri-devel@lists.freedesktop.org
Cc: Manasi Na
From: Gaurav K Singh
This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of intel_dp as an argument (Manasi)
* Use the compression_enable flag
Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.
v3:
* Use cpu_transcoder instead of encoder->type (Ville)
According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP payload
After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the
This patch defines the DP DSC receiver capability size that gives
total number of DP DSC DPCD registers.
This also adds a missing #defines for DP DSC support missed in the
commit id (ab6a46ea6842ce "Add DPCD definitions for DP 1.4 DSC feature")
v3:
* MIN_SLICE_WIDTH = 2560 (Anusha)
* Define DP_DSC
From: "Srivatsa, Anusha"
Add defines for DSS_CTL registers.
These registers specify the big joiner, splitter,
overlap pixels and info regarding display stream
compression enabled on left or right branch.
v3 (From Manasi):
- Change the hex values to lower case (Madhav)
- Use BIT macro (Manasi)
v2
A separate power well 2 (PG2) is required for VDSC on eDP transcoder
whereas all other transcoders use the power wells associated with the
transcoders for VDSC.
This patch adds a helper to obtain correct power domain depending on
transcoder being used and enables/disables the power wells during
VDS
Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.
v2:
* Rebase on drm-tip (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewe
From: Gaurav K Singh
This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder
v6: (From Manasi)
* Add a bit mask for RANGE_BPG_OFFSET for 6 bits(Manasi)
v5 (From Manasi)
* Add the RC constants as per the spec
v4 (From Manasi)
* Add the DSC_MUX_WO
DP 1.4 spec defines DP secondary data packet for DSC
picture parameter set. This patch defines its payload size
according to the DP 1.4 specification.
Signed-off-by: Manasi Navare
Cc: dri-devel@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Revi
From: Gaurav K Singh
This patches does the following:
1. This patch defines all the DSC parameters as per the VESA
DSC specification. These are stored in the encoder and used
to compute the PPS parameters to be sent to the Sink.
2. Compute all the DSC parameters which are derived from DSC
state
DSC is supported on eDP starting GEN 10 display (on GLK) and on DP starting
GEN 11.
This patch implements the discovery phase of DSC. On hotplug,
source reads the DSC DPCD register set (0x00060 - 0x0006F) to
read the decompression capabilities of the sink device.
This entire block of registers is c
This patch adds helpers for calculating the maximum compressed BPP
supported with small joiner.
This also adds a helper for calculating the slice count in case
of small joiner.
These are inside intel_dp since they take into account hardware
limitations.
v6:
* Take mode_clock and mode_hdisplay as i
Currently the driver will only enable DSC if a certain mode
does not fit the available link BW. However IGT/userspace
can force DSC enable through dsc support debugfs node to
test the DSC functionality if supported by the panel.
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-b
DSC specification defines linebuf_depth which contains the
line buffer bit depth used to generate the bitstream.
These values are defined as per Table 4.1 in DSC 1.2 spec
v2 (From Manasi):
* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula
C
When DSC is supported we need to validate the modes based on the
maximum supported compressed BPP and maximum supported slice count.
This allows us to allow the modes with pixel clock greater than the
available link BW as long as it meets the compressed BPP
and slice count requirements.
v3:
* Use
Basic DSC parameters and DSC configuration data needs to be computed
for each of the requested mode during atomic check. This is
required since for certain modes, valid DSC parameters and config
data might not be computed in which case compression cannot be
enabled for that mode.
For that reason we
From: Gaurav K Singh
This computation of RC params happens in the atomic commit phase
during compute_config() to validate if display stream compression
can be enabled for the requested mode.
v6 (From Manasi):
* Use 9 instead of 0x9 for consistency (Anusha)
v5 (From Manasi):
* Fix dim checkpatch
If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.
v3:
* Rebase
v2:
* Add warning for DSC and PSR2 enabled together (DK)
Cc: Rodrigo Vivi
C
From: Anusha Srivatsa
Add the newly added slice_row_per_frame parameter
in the Picture Parameter Set registers.
This defines the number of vertically stacked slices
in a frame.
Credits to Manasi for noticing bSpec change.
Suggested-by: Manasi Navare
Cc: Manasi Navare
Signed-off-by: Anusha Sri
This patch adds inline functions and helpers for obtaining
DP sink's supported DSC parameters like DSC sink support,
eDP compressed BPP supported, maximum slice count supported
by the sink devices, DSC line buffer bit depth supported on DP sink,
DSC sink maximum color depth by parsing corresponding
VESA has developed an industry standard Display Stream Compression(DSC)
for interoperable, visually lossless compression over display links to
address the needs for higher resolution displays.
This patch series enables DSC on Gen 10 eDP and Gen 11 eDP/DP panels.
This implementation is based on VES
Thought this was going to be an easy review until I realized that there's
multiple problems in nouveau this would cause issues with, even if we didn't
pay attention to the -EINVAL that gets returned. The suspend/resume order in
nouveau needs some fixing up to prevent this patch from causing timeout
https://bugs.freedesktop.org/show_bug.cgi?id=108260
Sebastian Parborg changed:
What|Removed |Added
CC||darkdefe...@gmail.com
--- Comment #
https://bugs.freedesktop.org/show_bug.cgi?id=108521
--- Comment #5 from Alex Deucher ---
If you can get any of the other methods to work you can remove the vegam device
id from the driver. That said, I doubt it will make a difference. Usually the
problem with thunderbolt is that pci BAR resourc
On Wed, Oct 24, 2018 at 7:08 PM Maxime Ripard wrote:
>
> On Tue, Oct 23, 2018 at 09:20:30PM +0530, Jagan Teki wrote:
> > Bananapi S070WV20-CT16 ICN6211 is 800x480, 4-lane MIPI-DSI to RGB bridge
> > panel,
> > the same panel PCB comes with parallel RBG which is supported via
> > panel-simple drive
On Wed, Oct 24, 2018 at 7:12 PM Maxime Ripard wrote:
> On Tue, Oct 23, 2018 at 09:20:35PM +0530, Jagan Teki wrote:
> > This patch add support for Bananapi S070WV20-CT16 DSI panel to
> > BPI-M64 board.
> >
> > DSI panel connected via board DSI port with,
> > - DC1SW as AVDD supply
> > - DCDC1 as DV
On Wed, Oct 24, 2018 at 3:31 PM Alex Deucher wrote:
>
> On Wed, Oct 24, 2018 at 2:26 PM Sean Paul wrote:
> >
> > From: Sean Paul
> >
> > Fixes the following warnings:
> > ../drivers/gpu/drm/drm_connector.c:305: warning: Excess function parameter
> > 'dev' description in 'drm_connector_attach_ed
https://bugs.freedesktop.org/show_bug.cgi?id=106175
--- Comment #29 from tempel.jul...@gmail.com ---
I gave it a try again: Unfortunately, there are no improvements to report with
latest 4.21-wip vs. the status of some months ago.
I really wonder how you can have trouble reproducing. This is not m
https://bugs.freedesktop.org/show_bug.cgi?id=106374
Alex Deucher changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
https://bugs.freedesktop.org/show_bug.cgi?id=106374
--- Comment #5 from tempel.jul...@gmail.com ---
It got implemented into 4.21 WIP kernel:
https://cgit.freedesktop.org/~agd5f/linux/commit/?h=drm-next-4.21-wip&id=f7becf9a0803030ae125189823328e2d62b90f7b
I can confirm it works, big thanks @ Josep
https://bugzilla.kernel.org/show_bug.cgi?id=201505
Alex Deucher (alexdeuc...@gmail.com) changed:
What|Removed |Added
CC||alexdeuc...@gmail.c
On Wed, Oct 24, 2018 at 2:26 PM Sean Paul wrote:
>
> From: Sean Paul
>
> Fixes the following warnings:
> ../drivers/gpu/drm/drm_connector.c:305: warning: Excess function parameter
> 'dev' description in 'drm_connector_attach_edid_property'
> ../drivers/gpu/drm/drm_connector.c:306: warning: Exces
The containing function is called with a spin_lock held, so GFP_KERNEL
can't be used.
julia
-- Forwarded message --
Date: Tue, 23 Oct 2018 17:14:25 +0800
From: kbuild test robot
To: kbu...@01.org
Cc: Julia Lawall
Subject: [PATCH] drm: fix call_kern.cocci warnings
CC: kbuild-...
I was going to start working on making the vc4 driver work with
tinydrm panels, but it turned out tinydrm didn't have the panel I had
previously bought. So, last night I ported the fbtft staging
driver over to DRM.
It seems to work (with DT at
https://github.com/anholt/linux/commits/drm-misc-next
I want to sort out support for tinydrm in vc4, so I needed to get a
tinydrm-appropriate panel working and this is what I had on hand.
This is derived from a combination of ili9341.c from tinydrm and
fb_hx8357d.c from staging's fbtft. The register header is copied
directly from staging's fbtft, on
If the clipped dirty region's x/y happened to align to 256, we would
have set the top 8 bits wrong. Noticed by inspection, not by
reproducing a bug.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/tinydrm/mipi-dbi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/
This adds a new binding for Himax HX8357D display panels. It includes
a compatible string for one display (more can be added in the future).
The YX350HV15 panel[1] is found in the Adafruit PiTFT 3.5" Touch
Screen for Raspberry Pi.
[1]
https://learn.adafruit.com/adafruit-pitft-3-dot-5-touch-scree
Hi,
On Wed, Oct 24, 2018 at 11:32 AM wrote:
>
> On 2018-10-20 01:49, Douglas Anderson wrote:
> > Let's solve the mystery of commit bf1178c98930 ("drm/bridge:
> > ti-sn65dsi86: Add mystery delay to enable()"). Specifically the
> > reason we needed that mystery delay is that we weren't paying
> >
On 2018-10-20 01:49, Douglas Anderson wrote:
Let's solve the mystery of commit bf1178c98930 ("drm/bridge:
ti-sn65dsi86: Add mystery delay to enable()"). Specifically the
reason we needed that mystery delay is that we weren't paying
attention to HPD.
Looking at the datasheet for the same panel t
From: Sean Paul
Fixes the following warnings:
../drivers/gpu/drm/drm_connector.c:305: warning: Excess function parameter
'dev' description in 'drm_connector_attach_edid_property'
../drivers/gpu/drm/drm_connector.c:306: warning: Excess function parameter
'dev' description in 'drm_connector_attac
https://bugs.freedesktop.org/show_bug.cgi?id=108542
Bug ID: 108542
Summary: hdmi issues with kernel 4.18
Product: DRI
Version: unspecified
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
Severity: nor
On Tue, Oct 23, 2018 at 09:20:32PM +0530, Jagan Teki wrote:
> A64 manual say PLL_MIPI rates are 500MHz to 1.4GHz, but
> using minimum 500MHz can't release the clock and which
> is not working.
>
> So use working minimum rate as 300MHz which is tested on
> Bananapi DSI panel.
I'm not quite sure wha
On Tue, Oct 23, 2018 at 09:20:35PM +0530, Jagan Teki wrote:
> This patch add support for Bananapi S070WV20-CT16 DSI panel to
> BPI-M64 board.
>
> DSI panel connected via board DSI port with,
> - DC1SW as AVDD supply
> - DCDC1 as DVDD supply
> - PD6 gpio for reset pin
> - PD5 gpio for backlight ena
On Tue, Oct 23, 2018 at 09:20:34PM +0530, Jagan Teki wrote:
> The A64 has a MIPI-DSI block which is similar to A31
> without mod clock.
>
> So, add dsi node with A64 compatible, dphy node with
> A31 compatible and finally connect dsi to tcon0 to
> make proper DSI pipeline.
>
> Signed-off-by: Jaga
On Tue, Oct 23, 2018 at 09:20:33PM +0530, Jagan Teki wrote:
> The MIPI DSI PHY HDMI controller on Allwinner A64 is similar
> on the one on A31.
>
> Add A64 compatible and append A31 compatible as fallback.
>
> Signed-off-by: Jagan Teki
> ---
> Changes for v2:
> - new patch
>
> Documentation/de
On Tue, Oct 23, 2018 at 09:20:30PM +0530, Jagan Teki wrote:
> Bananapi S070WV20-CT16 ICN6211 is 800x480, 4-lane MIPI-DSI to RGB bridge
> panel,
> the same panel PCB comes with parallel RBG which is supported via
> panel-simple driver with "bananapi,s070wv20-ct16" compatible.
>
> But this binding
On Tue, Oct 23, 2018 at 09:20:24PM +0530, Jagan Teki wrote:
> The MIPI DSI controller on Allwinner A64 is similar to
> Allwinner A31 without support of DSI mod clock(CLK_DSI_SCLK)
>
> So, alter has_mod_clk bool via driver data for respective
> SoC's compatible.
>
> Signed-off-by: Jagan Teki
> --
On Tue, Oct 23, 2018 at 09:20:22PM +0530, Jagan Teki wrote:
> Some NKM PLLs doesn't work well when their output clock rate is set below
> certain rate.
>
> So, add support for minimal rate for relevant PLLs.
>
> Signed-off-by: Jagan Teki
> ---
> Changes for v2:
> - new patch
>
> drivers/clk/su
From: Navare, Manasi D
Sent: Friday, October 05, 2018 4:23 PM
To: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
Cc: Navare, Manasi D; Jani Nikula; Ville Syrjala; Srivatsa, Anusha
Subject: [PATCH v5 28/28] drm/i915/dsc: Force DSC enable if
https://bugs.freedesktop.org/show_bug.cgi?id=108317
--- Comment #16 from John Galt ---
I thought I tested this before, and it turns out I had written R600DEBUG
instead :(.
R600_DEBUG=nohyperz works around this issue.
--
You are receiving this mail because:
You are the assignee for the bug.
Hi,
Le mercredi 24 octobre 2018 à 17:47 +0100, Maxime Ripard a écrit :
> On Tue, Oct 23, 2018 at 11:33:10AM +0200, Paul Kocialkowski wrote:
> > Hi,
> >
> > Le mercredi 10 octobre 2018 à 16:57 +0200, Maxime Ripard a écrit :
> > > On Wed, Oct 10, 2018 at 01:41:31PM +0200, Paul Kocialkowski wrote:
>
On Tue, Oct 23, 2018 at 01:39:10PM +0200, Maarten Lankhorst wrote:
>
>
> Op 02-10-18 om 13:15 schreef Stanislav Lisovskiy:
> > PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
> > specification.
> >
> > v2: Edited commit message, removed redundant whitespaces.
> >
> > v3: Fixed f
Start using drm_gpu_scheduler.ready isntead.
v3:
Add helper function to run ring test and set
sched.ready flag status accordingly, clean explicit
sched.ready sets from the IP specific files.
v4: Add kerneldoc and rebase.
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Christian König
---
driver
Problem:
A particular scheduler may become unsuable (underlying HW) after
some event (e.g. GPU reset). If it's later chosen by
the get free sched. policy a command will fail to be
submitted.
Fix:
Add a driver specific callback to report the sched status so
rq with bad sched can be avoided in favor
On Wednesday, 2018-10-24 17:53:51 +0100, Eric Engestrom wrote:
> Fixes the tests on ARM, but more importantly this makes it much easier
> to maintain.
BTW I have a wip to replace all of those with a python script that will
be more thorough in its checks, but until that lands this is already
a good
On Tue, Oct 23, 2018 at 12:08:17PM +0200, Paul Kocialkowski wrote:
> Hi,
>
> Le mercredi 10 octobre 2018 à 16:58 +0200, Maxime Ripard a écrit :
> > On Wed, Oct 10, 2018 at 01:41:32PM +0200, Paul Kocialkowski wrote:
> > > This adds support for the 3.5" LCD panel from Lemaker, sold for use with
> >
Signed-off-by: Eric Engestrom
---
.gitlab-ci.yml | 60 ++
1 file changed, 60 insertions(+)
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index a0edfdff43d24743586d..cbac993dd8227421be50 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -157,3 +157
Fixes the tests on ARM, but more importantly this makes it much easier
to maintain.
Signed-off-by: Eric Engestrom
---
amdgpu/amdgpu-symbol-check | 7 +--
etnaviv/etnaviv-symbol-check | 7 +--
exynos/exynos-symbol-check | 7 +--
freedreno/freedreno-symbol-check | 7
On Tue, Oct 23, 2018 at 11:33:10AM +0200, Paul Kocialkowski wrote:
> Hi,
>
> Le mercredi 10 octobre 2018 à 16:57 +0200, Maxime Ripard a écrit :
> > On Wed, Oct 10, 2018 at 01:41:31PM +0200, Paul Kocialkowski wrote:
> > > Some panels need an active-low data enable (DE) signal for the RGB
> > > inte
Hi Sravanthi,
On Wed, Oct 10, 2018 at 02:54:33PM +0530, Sravanthi Kollukuduru wrote:
> The interconnect framework is designed to provide a
> standard kernel interface to control the settings of
> the interconnects on a SoC.
>
> The interconnect API uses a consumer/provider-based model,
> where th
On Wed, 2018-10-24 at 10:57 +0200, Daniel Vetter wrote:
> On Tue, Oct 23, 2018 at 07:19:23PM -0700, Juston Li wrote:
> >
> > Signed-off-by: Juston Li
>
> For formality, does this also imply a reviewed-by tag?
I'm quite new to drm so I'll withhold a reviewed-by tag and ask that
someone else take
https://bugzilla.kernel.org/show_bug.cgi?id=201505
--- Comment #3 from Jan Ziak (http://atom-symbol.net)
(0xe2.0x9a.0...@gmail.com) ---
Created attachment 279137
--> https://bugzilla.kernel.org/attachment.cgi?id=279137&action=edit
dmesg with resume-from-suspend
dmesg with resume-from-suspend.
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