On Mon, 2018-11-12 at 16:01 +0100, Maarten Lankhorst wrote:
> We already have __drm_atomic_helper_connector_reset() and
> __drm_atomic_helper_plane_reset(), extend this to crtc as well.
>
> Most drivers already have a gpu reset hook, correct it.
> Nouveau already implemented its own __drm_atomic_h
Hi Helen,
On Tue, Nov 20, 2018 at 4:08 AM Helen Koike wrote:
>
> From: Enric Balletbo i Serra
>
> Add support to async updates of cursors by using the new atomic
> interface for that.
>
> Signed-off-by: Enric Balletbo i Serra
> [updated for upstream]
> Signed-off-by: Helen Koike
>
> ---
> Hell
Boris Brezillon writes:
> On Thu, 15 Nov 2018 12:49:11 -0800
> Eric Anholt wrote:
>
>> Boris Brezillon writes:
>>
>> > vc4_plane_atomic_async_check() was only based on the
>> > state->{crtc,src}_{w,h} which was fine since scaling was not allowed on
>> > the cursor plane.
>> >
>> > We are about
Boris Brezillon writes:
> On Thu, 15 Nov 2018 12:39:42 -0800
> Eric Anholt wrote:
>
>> Boris Brezillon writes:
>>
>> > We are about to use vc4_plane_mode_set() in the async check path, and
>> > async updates require that LBM size stay the same since they reuse the
>> > LBM from the previous st
Boris Brezillon writes:
> On Thu, 15 Nov 2018 12:41:36 -0800
> Eric Anholt wrote:
>
>> Boris Brezillon writes:
>>
>> > We are about to use vc4_plane_mode_set() in the async check path, but
>> > async check can decide that async update is not possible and force the
>> > driver to fallback to a
I have wanted this code in Mir, so it's plausibly useful elsewhere,
particularly if the DRM device major number is going to become
dynamic.
Signed-off-by: Christopher James Halse Rogers
---
xf86drm.c | 2 +-
xf86drm.h | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/xf86dr
Hi,
On Tue, 2018-11-20 at 12:05 +0800, CK Hu wrote:
> Hi, Matthias:
>
> On Mon, 2018-11-19 at 10:26 +0100, Matthias Brugger wrote:
> >
> > On 19/11/2018 06:38, CK Hu wrote:
> > > Hi, Matthias:
> > >
> > > On Fri, 2018-11-16 at 13:54 +0100, matthias@kernel.org wrote:
> > >> From: Matthias Br
Hi, Matthias:
On Mon, 2018-11-19 at 10:26 +0100, Matthias Brugger wrote:
>
> On 19/11/2018 06:38, CK Hu wrote:
> > Hi, Matthias:
> >
> > On Fri, 2018-11-16 at 13:54 +0100, matthias@kernel.org wrote:
> >> From: Matthias Brugger
> >>
> >> It can happen that the mmsys clock drivers aren't prob
https://bugs.freedesktop.org/show_bug.cgi?id=108806
Michael Lindman changed:
What|Removed |Added
Hardware|Other |x86-64 (AMD64)
OS|All
https://bugs.freedesktop.org/show_bug.cgi?id=108806
Bug ID: 108806
Summary: AMDGPU Failed to read EDID from display
Product: DRI
Version: unspecified
Hardware: Other
OS: All
Status: NEW
Severity: normal
We can't use drmSetMaster to query whether or not a drm fd is master
because it requires CAP_SYS_ADMIN, even if the fd *is* a master fd.
Pick DRM_IOCTL_MODE_ATTACHMODE as a long-deprecated ioctl that is
DRM_MASTER but not DRM_ROOT_ONLY as the probe by which we can detect
whether or not the fd is m
The hardware requires the HDSR and VDSR registers to be set to 1 or
higher. This translates to a minimum combined horizontal sync and back
porch of 20 pixels and a minimum vertical back porch of 3 lines. Reject
modes that fail those requirements.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/d
https://bugs.freedesktop.org/show_bug.cgi?id=108781
--- Comment #6 from jamespharve...@gmail.com ---
Alex Deucher, unfortunately the patch on bug 108704 has no effect.
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Hi Greg,
Today's linux-next merge of the staging tree got a conflict in:
drivers/staging/vboxvideo/vbox_ttm.c
between commits:
a64f784bb14a ("drm/ttm: initialize globals during device init (v2)")
from the drm tree and commit:
cd76c287a52f ("staging: vboxvideo: Cleanup the comments")
fr
On Mon, Nov 19, 2018 at 10:19:42PM +0200, Ville Syrjälä wrote:
> On Tue, Nov 13, 2018 at 05:52:30PM -0800, Manasi Navare wrote:
> > From: Anusha Srivatsa
> >
> > If the panel supports FEC, the driver has to
> > set the FEC_READY bit in the dpcd register:
> > FEC_CONFIGURATION.
> >
> > This has t
https://bugs.freedesktop.org/show_bug.cgi?id=106175
--- Comment #53 from bmil...@gmail.com ---
(In reply to rropid from comment #45)
> (In reply to bmilreu from comment #43)
> > If devs want an easy test case, use these links for reproducing it in
> > chromium:
> >
> > https://www.vsynctester.com
On Tue, 2018-11-13 at 22:07 +0200, Jani Nikula wrote:
> On Thu, 08 Nov 2018, Daniel Vetter wrote:
> > On Thu, Nov 08, 2018 at 08:42:52PM +, Souza, Jose wrote:
> > > On Thu, 2018-11-08 at 09:31 +0100, Daniel Vetter wrote:
> > > > On Wed, Nov 07, 2018 at 04:23:52PM -0800, José Roberto de Souza
>
https://bugs.freedesktop.org/show_bug.cgi?id=106175
--- Comment #52 from Brandon Wright ---
Ok, I think I understand what's going on. Forgive me if this sounds stupid, I'm
looking at the DRM code for the first time.
The old KMS interface uses what's flagged as "legacy" cursor updates. These are
Starting with 4.20-rc1 I'm seeing the LCD screen briefly turn mostly purple
on devices with a DSI panel (seen on 2 different devices with a DSI panel).
This happens both with and without fastboot=1. This is caused by
commit 516a49cc1946 ("drm/i915: Fix assert_plane() warning on bootup with
externa
On Mon, Nov 19, 2018 at 10:09:33AM -0800, Rodrigo Vivi wrote:
> On Sun, Nov 18, 2018 at 08:44:30PM +1100, Jonathan Gray wrote:
> > On Wed, Oct 31, 2018 at 08:43:03AM +, Chris Wilson wrote:
> > > Quoting Jonathan Gray (2018-10-31 00:56:12)
> > > > Chris Wilson said Intel is willing to change the
On Mon, Nov 19, 2018 at 10:27:44PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 15, 2018 at 05:39:42PM -0800, Manasi Navare wrote:
> > On Tue, Nov 13, 2018 at 05:52:28PM -0800, Manasi Navare wrote:
> > > DSC can be supported per DP connector. This patch adds a per connector
> > > debugfs node to expos
On Mon, Nov 19, 2018 at 10:33:37PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 19, 2018 at 12:10:47PM -0800, Manasi Navare wrote:
> > On Mon, Nov 19, 2018 at 09:43:38PM +0200, Ville Syrjälä wrote:
> > > On Tue, Nov 13, 2018 at 05:52:09PM -0800, Manasi Navare wrote:
> > > > DSC DPCD color depth regist
Thanks for the comments, please some my answers below:
On Mon, Nov 19, 2018 at 10:11:04PM +0200, Ville Syrjälä wrote:
> On Tue, Nov 13, 2018 at 05:52:16PM -0800, Manasi Navare wrote:
> > DSC params like the enable, compressed bpp, slice count and
> > dsc_split are added to the intel_crtc_state. Th
https://bugs.freedesktop.org/show_bug.cgi?id=106175
--- Comment #51 from Alex Deucher ---
DC uses the atomic KMS interface, the old code uses the legacy KMS interface.
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Hi Maxime,
On Tue, Nov 06, 2018 at 03:54:20PM +0100, Maxime Ripard wrote:
> Cadence has designed a D-PHY that can be used by the, currently in tree,
> DSI bridge (DRM), CSI Transceiver and CSI Receiver (v4l2) drivers.
>
> Only the DSI driver has an ad-hoc driver for that phy at the moment, while
https://bugs.freedesktop.org/show_bug.cgi?id=106175
--- Comment #50 from Brandon Wright ---
> I have this issue too, disabling page flipping fixes it for me on my vega10.
> It started with 4.16rc1 IIRC
Negative. I checked back as far as the DC/DAL was integrated (4.15) and it's
been there from
On Mon, Nov 19, 2018 at 12:10:47PM -0800, Manasi Navare wrote:
> On Mon, Nov 19, 2018 at 09:43:38PM +0200, Ville Syrjälä wrote:
> > On Tue, Nov 13, 2018 at 05:52:09PM -0800, Manasi Navare wrote:
> > > DSC DPCD color depth register advertises its color depth capabilities
> > > by setting each of the
On Thu, Nov 15, 2018 at 05:39:42PM -0800, Manasi Navare wrote:
> On Tue, Nov 13, 2018 at 05:52:28PM -0800, Manasi Navare wrote:
> > DSC can be supported per DP connector. This patch adds a per connector
> > debugfs node to expose DSC support capability by the kernel.
> > The same node can be used f
On Tue, Nov 13, 2018 at 05:52:30PM -0800, Manasi Navare wrote:
> From: Anusha Srivatsa
>
> If the panel supports FEC, the driver has to
> set the FEC_READY bit in the dpcd register:
> FEC_CONFIGURATION.
>
> This has to happen before link training.
>
> v2: s/intel_dp_set_fec_ready/intel_dp_sink_
On Tue, Nov 13, 2018 at 05:52:22PM -0800, Manasi Navare wrote:
> After encoder->pre_enable() hook, after link training sequence is
> completed, PPS registers for DSC encoder are configured using the
> DSC state parameters in intel_crtc_state as part of DSC enabling
> routine in the source. DSC enab
Hi ayaka,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on rockchip/for-next]
[also build test ERROR on v4.20-rc3 next-20181119]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci
On 2018-11-16 10:42, Sean Paul wrote:
From: Sean Paul
Each time it's called we're holding the crtc modeset lock, so it's
redundant.
Changes in v2:
- None
Signed-off-by: Sean Paul
Reviewed-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 11 ---
drivers/gpu/d
On 2018-11-16 10:42, Sean Paul wrote:
From: Sean Paul
It's just for debugfs output, we don't need it
Changes in v2:
- None
Cc: Jeykumar Sankaran
Signed-off-by: Sean Paul
Reviewed-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 6 --
drivers/gpu/drm/msm/disp/
On 2018-11-16 10:42, Sean Paul wrote:
From: Sean Paul
Instead of assigning/clearing the crtc on vblank enable/disable, we can
just assign and clear the crtc on modeset. That allows us to just
toggle
the encoder's vblank interrupts on vblank_enable.
So why is this important? Previously the dr
On 2018-11-16 10:42, Sean Paul wrote:
From: Sean Paul
The drm_crtc_vblank_on/off calls in enable/disable guarantee that we
won't call this function when crtc is not enabled.
Changes in v2:
- None
Signed-off-by: Sean Paul
Reviewed-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/
On 2018-11-16 10:42, Sean Paul wrote:
From: Sean Paul
Matches dpu_crtc_enable and we'll need the old state in a future patch
Changes in v2:
- None
Signed-off-by: Sean Paul
Reviewed-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 5 +++--
1 file changed, 3 insertion
On 2018-11-16 10:42, Sean Paul wrote:
From: Sean Paul
The indirection of registering a callback and opaque pointer isn't
reall
useful when there's only one callsite. So instead of having the
vblank_cb registration, just give encoder a crtc and let it directly
call the vblank handler.
In a la
On Tue, Nov 13, 2018 at 05:52:16PM -0800, Manasi Navare wrote:
> DSC params like the enable, compressed bpp, slice count and
> dsc_split are added to the intel_crtc_state. These parameters
> are set based on the requested mode and available link parameters
> during the pipe configuration in atomic
On 2018-11-16 10:42, Sean Paul wrote:
From: Sean Paul
I think the intention here was to protect the enc->crtc access, but
that's insufficient to avoid enc->crtc changing. Fortunately we're
already holding the modeset lock when this is called (from
atomic_check), so remove the crtc_lock and add
On 2018-11-16 10:42, Sean Paul wrote:
From: Sean Paul
There are 4 times that _dpu_crtc_vblank_enable_no_lock() is called:
1- crtc enable
2- crtc disable
3- crtc vblank enable
4- crtc vblank disable
When we enable or disable the crtc, we call drm_crtc_vblank_on and
drm_crtc_vblank_off respecti
On Mon, Nov 19, 2018 at 09:43:38PM +0200, Ville Syrjälä wrote:
> On Tue, Nov 13, 2018 at 05:52:09PM -0800, Manasi Navare wrote:
> > DSC DPCD color depth register advertises its color depth capabilities
> > by setting each of the bits that corresponding to a specific color
> > depth. This patch defi
On 2018-11-16 13:14, Sean Paul wrote:
On Fri, Nov 16, 2018 at 12:05:09PM -0800, Jeykumar Sankaran wrote:
On 2018-11-16 10:42, Sean Paul wrote:
> From: Sean Paul
>
> It's for legacy drivers, for atomic drivers crtc->state->encoder_mask
> should be used to map encoder to crtc.
>
> Changes in v2:
-Original Message-
From: Lyude Paul
Sent: November 16, 2018 6:25 PM
To: amd-...@lists.freedesktop.org
Cc: Wentland, Harry ; Li, Sun peng (Leo)
; Deucher, Alexander ; Koenig,
Christian ; Zhou, David(ChunMing)
; David Airlie ; Zuo, Jerry
; Li, Roman ; Cheng, Tony
; Daniel Vetter ; S, S
On 2018-11-16 10:42, Sean Paul wrote:
From: Sean Paul
Now that runtime resume is handled in encoder, we don't need to worry
about crtc_lock recursion when calling pm_runtime_(get|put). So drop
the
lock drops in _dpu_crtc_vblank_enable_no_lock().
Changes in v2:
- None
Signed-off-by: Sean Pau
On Tue, Nov 13, 2018 at 05:52:09PM -0800, Manasi Navare wrote:
> DSC DPCD color depth register advertises its color depth capabilities
> by setting each of the bits that corresponding to a specific color
> depth. This patch defines those specific color depths and adds
> a helper to return an array
On 2018-11-16 10:42, Sean Paul wrote:
From: Sean Paul
Instead of registering through dpu_power_handle just to get a call on
runtime_resume, call the crtc function directly.
Changes in v2:
- None
Signed-off-by: Sean Paul
Reviewed-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/d
https://bugs.freedesktop.org/show_bug.cgi?id=108671
--- Comment #11 from Alex Deucher ---
(In reply to Alex Deucher from comment #10)
> Possibly a duplicate of bug 108704. Does the patch there help?
Nevermind, you have a vega10.
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https://bugs.freedesktop.org/show_bug.cgi?id=108671
--- Comment #10 from Alex Deucher ---
Possibly a duplicate of bug 108704. Does the patch there help?
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On Mon, Nov 19, 2018 at 7:03 AM Christian König
wrote:
>
> Am 19.11.18 um 12:55 schrieb Takashi Iwai:
> > Due to lack of MODULE_FIRMWARE() with hainan_mc.bin, the driver
> > doesn't work properly in initrd. Let's add it.
> >
> > Bugzilla: https://bugzilla.suse.com/show_bug.cgi?id=1116239
> > Fixe
On Mon, Nov 19, 2018 at 2:17 PM Brajeswar Ghosh
wrote:
>
> Remove gca/gfx_8_0_enum.h which is included more than once
>
> Signed-off-by: Brajeswar Ghosh
Applied. thanks!
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm
On Sun, Nov 18, 2018 at 11:12 AM Matthias Brugger
wrote:
>
>
>
> On 11/17/18 12:15 AM, Rob Herring wrote:
> > On Fri, Nov 16, 2018 at 01:54:45PM +0100, matthias@kernel.org wrote:
> >> From: Matthias Brugger
> >>
> >> On SoCs with no publical available HW or no working graphic stack
> >> we ch
https://bugs.freedesktop.org/show_bug.cgi?id=108778
Alex Deucher changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=108778
--- Comment #6 from Alex Deucher ---
(In reply to Garth Theisen from comment #5)
> Reviewing my 4.18.18 log, the dce110_link_encoder_construct is present, but
> not 'amdgpu: [powerplay] Failed to retrieve minimum clocks.'.
Those are harmless.
https://bugs.freedesktop.org/show_bug.cgi?id=108704
Alex Deucher changed:
What|Removed |Added
CC||garththei...@hotmail.com
--- Comment #4
On Mon, 19 Nov 2018 18:59:04 +
Fabrizio Castro wrote:
> Hello Boris,
>
> > From: Boris Brezillon
> > Sent: 19 November 2018 16:55
> > Subject: Re: [PATCH v3] drm/bridge/sii902x: Add missing dependency on
> > I2C_MUX
> >
> > Hi Fabrizio,
> >
> > On Mon, 19 Nov 2018 13:26:18 +
> > Fabriz
Sure, I'll do it.
-Original Message-
From: Lyude Paul
Sent: November 19, 2018 1:52 PM
To: Zuo, Jerry ; amd-...@lists.freedesktop.org
Cc: Wentland, Harry ; Li, Sun peng (Leo)
; Deucher, Alexander ; Koenig,
Christian ; Zhou, David(ChunMing)
; David Airlie ; Li, Roman
; S, Shirish ; Dan
Cool! If it did actually fix those problems, would you mind making sure this
gets Cc'd to stable when it gets pushed upstream?
On Mon, 2018-11-19 at 15:00 +, Zuo, Jerry wrote:
> Reviewed-by: Jerry (Fangzhi) Zuo
>
> The change fixed MST + SST daisy chain and S3 scenarios. The issue shows
> hu
On 2018-11-16 13:37, Sean Paul wrote:
On Fri, Nov 16, 2018 at 04:35:26PM -0500, Sean Paul wrote:
On Fri, Nov 16, 2018 at 11:22:21AM -0800, Jeykumar Sankaran wrote:
> Add encoder interface to release dpu encoder
> on mode_init failures in kms.
>
> Signed-off-by: Jeykumar Sankaran
> ---
> driver
On 2018-11-16 13:35, Sean Paul wrote:
On Fri, Nov 16, 2018 at 11:22:21AM -0800, Jeykumar Sankaran wrote:
Add encoder interface to release dpu encoder
on mode_init failures in kms.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 12 ++--
drivers/gpu/d
https://bugs.freedesktop.org/show_bug.cgi?id=108729
Vedran Miletić changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
On 2018-11-16 12:02, Sean Paul wrote:
On Thu, Nov 08, 2018 at 02:00:51PM -0800, Jeykumar Sankaran wrote:
On 2018-10-30 09:00, Sean Paul wrote:
> From: Sean Paul
>
> This patch sprinkles a few async/legacy_cursor_update checks
> through commit to ensure that cursor updates aren't blocked on vsyn
https://bugs.freedesktop.org/show_bug.cgi?id=108778
--- Comment #5 from Garth Theisen ---
Reviewing my 4.18.18 log, the dce110_link_encoder_construct is present, but not
'amdgpu: [powerplay] Failed to retrieve minimum clocks.'.
[3.314952] [drm] amdgpu: 8192M of VRAM memory ready
[3.31495
https://bugs.freedesktop.org/show_bug.cgi?id=108778
--- Comment #4 from Garth Theisen ---
After applying the patch 4.19.2 boots without the Init failure.
There seems to be some additional issues present in the dmesg log after the
patch ... but this might be occurring for the 4.18.x series also.
https://bugzilla.kernel.org/show_bug.cgi?id=200695
Claude Heiland-Allen (cla...@mathr.co.uk) changed:
What|Removed |Added
Kernel Version|4.17.19, 4.18.0-rc7,|4.17.19, 4.18.
On Sun, Nov 18, 2018 at 08:44:30PM +1100, Jonathan Gray wrote:
> On Wed, Oct 31, 2018 at 08:43:03AM +, Chris Wilson wrote:
> > Quoting Jonathan Gray (2018-10-31 00:56:12)
> > > Chris Wilson said Intel is willing to change the license of these files
> > > to MIT.
> > >
> > > Signed-off-by: Jona
https://bugs.freedesktop.org/show_bug.cgi?id=108781
--- Comment #5 from m...@mgoodwin.net ---
I can add that I also hit this on a R9 290 Reference card:
01:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI]
Hawaii PRO [Radeon R9 290/390] (prog-if 00 [VGA controller])
S
Hi Maxime,
On Tue, Nov 06, 2018 at 03:54:18PM +0100, Maxime Ripard wrote:
> Now that our MIPI D-PHY driver has been converted to the phy framework,
> let's move it into the drivers/phy directory.
>
> Signed-off-by: Maxime Ripard
> ---
> drivers/gpu/drm/sun4i/Kconfig | 10 +-
> dr
Hi Fabrizio,
On Mon, 19 Nov 2018 13:26:18 +
Fabrizio Castro wrote:
> kbuild test robot reports:
>
> >> ERROR: "i2c_mux_add_adapter" [drivers/gpu/drm/bridge/sii902x.ko]
> undefined!
> >> ERROR: "i2c_mux_alloc" [drivers/gpu/drm/bridge/sii902x.ko]
> undefined!
> >> ERROR: "i2c_mux_del_adap
https://bugs.freedesktop.org/show_bug.cgi?id=106175
--- Comment #49 from Brandon Wright ---
I'm going to speculate that maybe the hardware cursor updates are triggering an
update to the vsync timestamp counter or msc that's incorrect and throwing off
the timing.
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You are receiving this mail b
Hi Matt,
On Thu, Nov 15, 2018 at 02:13:45PM -0800, Matt Roper wrote:
>Some display controllers can be programmed to present non-black colors
>for pixels not covered by any plane (or pixels covered by the
>transparent regions of higher planes). Compositors that want a UI with
>a solid color backgr
https://bugs.freedesktop.org/show_bug.cgi?id=106175
--- Comment #48 from tempel.jul...@gmail.com ---
With amdgpu.dc=0, TearFree works as expected for me (no tearing without
compositor, scrolling in Firefox windowed is free of stutter, no issues with
compositor vsync either).
I think we should lea
https://bugs.freedesktop.org/show_bug.cgi?id=108780
--- Comment #1 from Alex Deucher ---
Fixed here:
https://patchwork.freedesktop.org/patch/262616/
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dr
https://bugzilla.kernel.org/show_bug.cgi?id=201727
Alex Deucher (alexdeuc...@gmail.com) changed:
What|Removed |Added
CC||alexdeuc...@gmail.c
https://bugs.freedesktop.org/show_bug.cgi?id=106175
--- Comment #47 from Michel Dänzer ---
FWIW, note that TearFree can be toggled at runtime using the RandR output
property of the same name. At its default value "auto", TearFree is
automatically enabled for an output using rotation / scaling / o
https://bugs.freedesktop.org/show_bug.cgi?id=106175
--- Comment #46 from Brandon Wright ---
I've never run TearFree, so that's not the case here. My Xorg config is similar
to yours, just amdgpu and DRI 3. I did have an extra section to use evdev
instead of libinput, but I tried removing that and
Ping.
Benoit
Benoit Parrot wrote on Fri [2018-Oct-12 15:16:55 -0500]:
> This patch series adds virtual-plane support to omapdrm driver to allow the
> use
> of display wider than 2048 pixels.
>
> In order to do so we introduce the concept of hw_overlay which can then be
> dynamically allocated
https://bugs.freedesktop.org/show_bug.cgi?id=108794
Bug ID: 108794
Summary: Inconsistent behavior with Separable Shaders
(ARB_separate_shader_objects)
Product: Mesa
Version: unspecified
Hardware: x86-64 (AMD64)
https://bugs.freedesktop.org/show_bug.cgi?id=108781
--- Comment #4 from Alex Deucher ---
Possibly the same issue as bug 108704. Does the patch there help?
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Reviewed-by: Jerry (Fangzhi) Zuo
The change fixed MST + SST daisy chain and S3 scenarios. The issue shows huge
delay in MST + SST daisy chain, and soft hang in S3 resume.
The aux sequence is changed by failed iteration search in
drm_connector_for_each_possible_encoder().
The failure of search
https://bugs.freedesktop.org/show_bug.cgi?id=108778
--- Comment #3 from Alex Deucher ---
Possibly the same issue as bug 108704. Does the patch there help?
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Render like lima will attach a fence to the framebuffer
dma_buf, display like sun4i should wait it finish before
show the framebuffer. Otherwise tearing will be observed.
Signed-off-by: Qiang Yu
---
drivers/gpu/drm/sun4i/sun4i_layer.c| 2 ++
drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 2 ++
dri
Am Dienstag, 6. November 2018, 16:37:05 CET schrieb Damian Kos:
> Some of the functions (like cdn_dp_dpcd_read, cdn_dp_get_edid_block)
> allow to read 64KiB, but the cdn_dp_mailbox_read_receive, that is
> used by them, can read only up to 255 bytes at once. Normally, it's
> not a big issue as DPCD
https://bugs.freedesktop.org/show_bug.cgi?id=105113
--- Comment #8 from Maciej S. Szmigiero ---
(In reply to Jan Vesely from comment #7)
> (In reply to Maciej S. Szmigiero from comment #6)
> > There are really two issues at play here:
> > 1) If the LLVM-generated code cannot be run properly then
Hi Maxime,
On Tue, Nov 06, 2018 at 03:54:15PM +0100, Maxime Ripard wrote:
> Now that we have some infrastructure for it, allow the MIPI D-PHY phy's to
> be configured through the generic functions through a custom structure
> added to the generic union.
>
> The parameters added here are the ones
https://bugs.freedesktop.org/show_bug.cgi?id=108760
--- Comment #4 from Alex Deucher ---
upstream is the open stack.
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ht
Hi Maxime,
Apologies for the delayed review. Please see my comments below.
On Tue, Nov 06, 2018 at 03:54:16PM +0100, Maxime Ripard wrote:
> The MIPI D-PHY spec defines default values and boundaries for most of the
> parameters it defines. Introduce helpers to help drivers get meaningful
> values
https://bugs.freedesktop.org/show_bug.cgi?id=108625
--- Comment #16 from Christian König ---
(In reply to Carsten Haitzler from comment #15)
> Makes it work. Of course this isn't a brilliant patch, but indeed there is
> something up with the way write combined memory is handled on ARM here.
Well
On Mon, 19 Nov 2018 13:09:16 +
Fabrizio Castro wrote:
> Hi Boris,
>
> > From: Boris Brezillon
> > Sent: 19 November 2018 12:51
> > Subject: Re: [PATCH] drm/bridge: Fix 0-day build error
> >
> > Hi Fabrizio,
> >
> > The prefix should be "drm/bridge/sii902x:" and I'd prefer a short
> > explan
https://bugs.freedesktop.org/show_bug.cgi?id=108625
--- Comment #15 from Carsten Haitzler ---
And lo and behold:
--- ./include/drm/drm_cache.h~ 2018-08-12 21:41:04.0 +0100
+++ ./include/drm/drm_cache.h 2018-11-16 11:06:16.976842816 +
@@ -48,7 +48,7 @@
#elif defined(CONFIG_MIPS) &
https://bugs.freedesktop.org/show_bug.cgi?id=108767
Lakshmi changed:
What|Removed |Added
Assignee|dri-devel@lists.freedesktop |petri.latv...@intel.com
|.o
Hi Fabrizio,
The prefix should be "drm/bridge/sii902x:" and I'd prefer a short
explanation of what is problematic in the subject rather than "Fix
0-day build error". Maybe something like
"drm/bridge/sii902x: Add missing dependency on I2C_MUX"
On Mon, 19 Nov 2018 12:44:23 +
Fabrizio Castro w
https://bugzilla.kernel.org/show_bug.cgi?id=201727
--- Comment #9 from Michal Herko (misko.he...@gmail.com) ---
> What is your BIOS setting for the stolen VRAM?
I can't find any such settings in bios. I really do not have any options
regarding video.
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On Thu, Nov 15, 2018 at 11:16:23PM +0100, Fernando Ramos wrote:
> This patch unifies the naming of DRM functions for reference counting as
> requested on Documentation/gpu/todo.rst
>
> Signed-off-by: Fernando Ramos
> ---
> drivers/gpu/drm/arc/arcpgu_drv.c | 4 ++--
> drivers/gpu/drm/
Hi!
> > > @@ -217,6 +239,9 @@ static irqreturn_t omap_irq_handler(int irq, void
> > > *arg)
> > >
> > > if (irqstatus &
> > > priv->dispc_ops->mgr_get_sync_lost_irq(priv->dispc, channel))
> > > omap_crtc_error_irq(crtc, irqstatus);
> > > +
> > > + if (irqsta
Am 19.11.18 um 12:55 schrieb Takashi Iwai:
Due to lack of MODULE_FIRMWARE() with hainan_mc.bin, the driver
doesn't work properly in initrd. Let's add it.
Bugzilla: https://bugzilla.suse.com/show_bug.cgi?id=1116239
Fixes: 8eaf2b1faaf4 ("drm/amdgpu: switch firmware path for SI parts")
Cc:
Signed
Due to lack of MODULE_FIRMWARE() with hainan_mc.bin, the driver
doesn't work properly in initrd. Let's add it.
Bugzilla: https://bugzilla.suse.com/show_bug.cgi?id=1116239
Fixes: 8eaf2b1faaf4 ("drm/amdgpu: switch firmware path for SI parts")
Cc:
Signed-off-by: Takashi Iwai
---
drivers/gpu/drm/a
https://bugs.freedesktop.org/show_bug.cgi?id=108760
--- Comment #3 from Chen Xi ---
Alex, Thanks a lot for your quick response!
Hai is taking leave. I will follow up the issue when he takes leave.
Could you please be more specific about the "upstream driver" mentioned in your
comment? so we co
https://bugzilla.kernel.org/show_bug.cgi?id=201727
--- Comment #8 from Michal Herko (misko.he...@gmail.com) ---
Created attachment 279521
--> https://bugzilla.kernel.org/attachment.cgi?id=279521&action=edit
revert of 284dec
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https://bugzilla.kernel.org/show_bug.cgi?id=201727
--- Comment #7 from Michal Herko (misko.he...@gmail.com) ---
Everything works after a revert. There was a conflict, i am attaching a diff of
the revert.
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https://bugzilla.kernel.org/show_bug.cgi?id=201727
--- Comment #6 from Christian König (christian.koe...@amd.com) ---
Currently GTT is only used for PD/PT as last resort when there is so few stolen
memory assigned to the APU that it won't work at all otherwise.
The faulting address looks suspicio
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