Hi Linus,
New Years fixes! Mostly amdgpu with a light smattering of arm
graphics, and two AGP warning fixes.
Quiet as expected, hopefully we don't get a post holiday rush.
Dave.
drm-fixes-2020-01-03:
drm fixes for 5.5-rc5
agp:
- two unused variable removed
amdgpu:
- ATPX regression fix
- SMU
https://bugzilla.kernel.org/show_bug.cgi?id=206017
--- Comment #4 from udo (udo...@xs4all.nl) ---
But 5.4.x is not really stable; it crashes easily within a day where 5.3.18 can
stay up for a few days.
--
You are receiving this mail because:
You are watching the assignee of the bug.
[Why]
According to DP spec, it should shift left 4 digits for NO_STOP_BIT
in REMOTE_I2C_READ message. Not 5 digits.
In current code, NO_STOP_BIT is always set to zero which means I2C
master is always generating a I2C stop at the end of each I2C write
transaction while handling REMOTE_I2C_READ
On Wed, Jan 1, 2020 at 2:39 AM Qiang Yu wrote:
>
> drm_sched_job_timedout works with drm_sched_stop as a pair,
> so we'd better use the drm_sched_fault helper to make the
> error and timeout handling go the same path.
>
> This also fixes application hang when task error.
>
> Signed-off-by: Qiang
Hi, Yongqiang:
On Fri, 2020-01-03 at 11:12 +0800, Yongqiang Niu wrote:
> there will be more sout case in the future,
> make the sout function format same mtk_ddp_sel_in
>
Reviewed-by: CK Hu
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 24
Hi, Yongqiang:
On Fri, 2020-01-03 at 11:12 +0800, Yongqiang Niu wrote:
> move dsi/dpi select input into mtk_ddp_sel_in
> DPI_SEL_IN_BLS is zero, it is same with hardware default setting,
> DISP_REG_CONFIG_DPI_SEL no need set when bls connect with
> dpi0
I think you have done two things in this
Hi, Yongqiang:
This 'RESEND v6' is different with v6, so I think you should call this
v7.
Regards,
CK
On Fri, 2020-01-03 at 11:12 +0800, Yongqiang Niu wrote:
> This series are based on 5.5-rc1 and provid 17 patch
> to support mediatek SOC MT8183
>
> Change since v5
> - fix reviewed issue in v5
Hi, Yongqiang:
On Fri, 2020-01-03 at 11:12 +0800, Yongqiang Niu wrote:
> Update device tree binding documention for rdma_fifo_size
>
> Signed-off-by: Yongqiang Niu
> ---
> .../devicetree/bindings/display/mediatek/mediatek,disp.txt | 13
> +
> 1 file changed, 13 insertions(+)
>
>
From: Sean Paul
[ Upstream commit 268de6530aa18fe5773062367fd119f0045f6e88 ]
Spec says[1] Allocated_PBN is 16 bits
[1]- DisplayPort 1.2 Spec, Section 2.11.9.8, Table 2-98
Fixes: ad7f8a1f9ced ("drm/helper: add Displayport multi-stream helper (v0.6)")
Cc: Lyude Paul
Cc: Todd Previte
Cc: Dave
From: Sean Paul
[ Upstream commit 268de6530aa18fe5773062367fd119f0045f6e88 ]
Spec says[1] Allocated_PBN is 16 bits
[1]- DisplayPort 1.2 Spec, Section 2.11.9.8, Table 2-98
Fixes: ad7f8a1f9ced ("drm/helper: add Displayport multi-stream helper (v0.6)")
Cc: Lyude Paul
Cc: Todd Previte
Cc: Dave
Document the remaining DRM_ logging functions.
As the logging functions are now all properly
listed drop the few specific kernel-doc markers
so we keep the relevant parts in the documentation.
Signed-off-by: Sam Ravnborg
Cc: Jani Nikula
Cc: Sean Paul
Cc: Daniel Vetter
---
This is the documentation I have missed when I looked for help
how to do proper logging. Hopefully it can help others.
v2:
- Add parameters to the logging functions in the doc
- Drop notes on other types of logging
Signed-off-by: Sam Ravnborg
Cc: Jani Nikula
Cc: Sean Paul
Cc: Daniel
Add kernel-doc for the drm_ and DRM_ logging
functions.
This is the documentation that I missed when I started to use
the logging functions.
Version 1 of this patchset included drm_ variants of the existing
logging functions - but they are left out for now.
The idea is that we should try to use
Hi Rodrigo,
Thank you for the review.
On 02-01-2020 19:17, Rodrigo Vivi wrote:
On Mon, Dec 16, 2019 at 12:51:57PM +0100, Hans de Goede wrote:
From: Derek Basehore
Not every platform needs quirk detection for panel orientation, so
split the drm_connector_init_panel_orientation_property into
On Mon, Dec 16, 2019 at 12:51:57PM +0100, Hans de Goede wrote:
> From: Derek Basehore
>
> Not every platform needs quirk detection for panel orientation, so
> split the drm_connector_init_panel_orientation_property into two
> functions. One for platforms without the need for quirks, and the
>
Hi Miquel
On Tue, Dec 24, 2019 at 03:21:34PM +0100, Miquel Raynal wrote:
> The panel common bindings provide a gpios-reset property. Let's
> support it in the simple driver.
>
> Two fields are added to the panel description structure: the time to
> assert the reset and the time to wait right
On Thu, Jan 2, 2020 at 8:26 AM Maxime Ripard wrote:
>
> The Allwinner SoCs have a display engine composed of several controllers
> assembled differently depending on the SoC, the number and type of output
> they have, and the additional features they provide. A number of those are
> supported in
On Thu, Jan 2, 2020 at 9:17 PM Maxime Ripard wrote:
>
> On Thu, Jan 02, 2020 at 09:10:31PM +0530, Jagan Teki wrote:
> > On Thu, Jan 2, 2020 at 4:24 PM Maxime Ripard wrote:
> > >
> > > On Tue, Dec 31, 2019 at 06:35:21PM +0530, Jagan Teki wrote:
> > > > TCON LCD0, LCD1 in allwinner R40, are used
Hi Lee.
> > > ("drm/atmel-hlcdc: allow selecting a higher pixel-clock than requested")
> > >
> > > Claudiu Beznea (5):
> > > drm: atmel-hlcdc: use double rate for pixel clock only if supported
> > > drm: atmel-hlcdc: enable clock before configuring timing engine
> >
> > > mfd:
On Thu, 02 Jan 2020, Sam Ravnborg wrote:
> Hi Lee.
>
> How do de handle the two mfd related patches?
>
> > I have few fixes for atmel-hlcdc driver in this series as well
> > as two reverts.
> > Revert "drm: atmel-hlcdc: enable sys_clk during initalization." is
> > due to the fix in in patch
On 2019-07-26 1:37 p.m., David (Dingchen) Zhang wrote:
> From: Dingchen Zhang
>
> to terminate the while-loop in drm_dp_aux_crc_work when
> drm_dp_start/stop_crc are called in the hook to set crc source.
>
> v3: set crc->opened to false without checking (Nick)
> v2: Move spin_lock around entire
On Thu, Jan 02, 2020 at 09:10:31PM +0530, Jagan Teki wrote:
> On Thu, Jan 2, 2020 at 4:24 PM Maxime Ripard wrote:
> >
> > On Tue, Dec 31, 2019 at 06:35:21PM +0530, Jagan Teki wrote:
> > > TCON LCD0, LCD1 in allwinner R40, are used for managing
> > > LCD interfaces like RGB, LVDS and DSI.
> > >
>
On Thu, Jan 2, 2020 at 4:33 PM Maxime Ripard wrote:
>
> On Tue, Dec 31, 2019 at 06:35:25PM +0530, Jagan Teki wrote:
> > The MIPI DSI PHY controller on Allwinner R40 is similar
> > on the one on A31.
> >
> > Add R40 compatible and append A31 compatible as fallback.
> >
> > Signed-off-by: Jagan
https://bugzilla.kernel.org/show_bug.cgi?id=205049
--- Comment #17 from Pierre-Eric Pelloux-Prayer
(pierre-eric.pelloux-pra...@amd.com) ---
This bug has been fixed in Mesa, but is not part of a release yet.
So the 3 possible fixes are:
- compile Mesa from git
- or find a package for your
On Thu, Jan 2, 2020 at 4:24 PM Maxime Ripard wrote:
>
> On Tue, Dec 31, 2019 at 06:35:21PM +0530, Jagan Teki wrote:
> > TCON LCD0, LCD1 in allwinner R40, are used for managing
> > LCD interfaces like RGB, LVDS and DSI.
> >
> > Like TCON TV0, TV1 these LCD0, LCD1 are also managed via
> > tcon top.
https://bugzilla.kernel.org/show_bug.cgi?id=205049
--- Comment #16 from le...@onet.pl ---
https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2836
Could somebody please provide a clear set of instructions on what can actually
be done with this link? It just seems to contain a heap of forum
On 2019-12-02 4:47 p.m., Thomas Anderson wrote:
> For high-res (8K) or HFR (4K120) displays, using uncompressed pixel
> formats like YCbCr444 would exceed the bandwidth of HDMI 2.0, so the
> "interesting" modes would be disabled, leaving only low-res or low
> framerate modes.
>
> This change
Den 30.12.2019 14.06, skrev Geert Uytterhoeven:
> When configuring the frame memory window, the last column and row
> numbers are written to the column resp. page address registers. These
> numbers are thus one less than the actual window width resp. height.
>
> While this is handled
Hi Geert.
On Thu, Jan 02, 2020 at 03:12:44PM +0100, Geert Uytterhoeven wrote:
> Document support for the Okaya RH128128T display, which is a 128x128
> 1.44" TFT display driven by a Sitronix ST7715R TFT Controller/Driver.
>
> ST7715R and ST7735R are very similar. Their major difference is that
>
If the resolution of the TFT display is smaller than the maximum
resolution supported by the display controller, the display may be
connected to the driver output arrays with a horizontal and/or vertical
offset, leading to a shifted image.
Add support for specifying these offsets.
Signed-off-by:
Hi all,
This patch series adds support for the Okaya RH128128T LCD to the
existing ST7735R driver. This is a 128x128 1.4" TFT display driven by a
Sitronix ST7715R TFT Controller/Driver. It is used on the "lcd-pmod"
display module that is shipped with Renesas RSK+RZA1 development boards,
Document support for the Okaya RH128128T display, which is a 128x128
1.44" TFT display driven by a Sitronix ST7715R TFT Controller/Driver.
ST7715R and ST7735R are very similar. Their major difference is that
the former is restricted to displays of up to 132x132 pixels, while the
latter supports
Add support for the Okaya RH128128T display to the st7735r driver.
The RH128128T is a 128x128 1.44" TFT display driven by a Sitronix
ST7715R TFT Controller/Driver. The latter is very similar to the
ST7735R, and can be handled by the existing st7735r driver.
Signed-off-by: Geert Uytterhoeven
Use the ddc pointer provided by the generic connector.
Signed-off-by: Andrzej Pietrasiewicz
Acked-by: Sam Ravnborg
Reviewed-by: Emil Velikov
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c
The series completes the process of adding ddc symlink in connector's
sysfs directory: of the initial submission only the below patches are
still pending, hence this resend. Rebased onto drm-misc-next as of
2020-01-02.
Andrzej Pietrasiewicz (4):
drm/tegra: Provide ddc symlink in output
Use the ddc pointer provided by the generic connector.
Signed-off-by: Andrzej Pietrasiewicz
Acked-by: Sam Ravnborg
Reviewed-by: Emil Velikov
---
drivers/gpu/drm/zte/zx_vga.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/zte/zx_vga.c
Use the ddc pointer provided by the generic connector.
Signed-off-by: Andrzej Pietrasiewicz
Acked-by: Sam Ravnborg
Reviewed-by: Emil Velikov
---
drivers/gpu/drm/zte/zx_hdmi.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/zte/zx_hdmi.c
Use the ddc pointer provided by the generic connector.
Signed-off-by: Andrzej Pietrasiewicz
Acked-by: Sam Ravnborg
Reviewed-by: Emil Velikov
---
drivers/gpu/drm/tegra/hdmi.c | 7 ---
drivers/gpu/drm/tegra/sor.c | 7 ---
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git
drm-misc-next-2020-01-02:
drm-misc-next for v5.6:
UAPI Changes:
- Commandline parser: Add support for panel orientation, and per-mode options.
- Fix IOCTL naming for dma-buf heaps.
Cross-subsystem Changes:
- Rename DMA_HEAP_IOC_ALLOC to DMA_HEAP_IOCTL_ALLOC before it becomes abi.
- Change
On 23/12/2019 15:41, Yuti Amonkar wrote:
> Allow DisplayPort PHYs to be configured through the generic
> functions through a custom structure added to the generic union.
> The configuration structure is used for reconfiguration of
> DisplayPort PHYs during link training operation.
>
> The
On Tue, Dec 31, 2019 at 06:35:26PM +0530, Jagan Teki wrote:
> The MIPI DSI controller on Allwinner R40 is similar on
> the one on A64 like doesn't associate any DSI_SCLK gating.
>
> So, add R40 compatible and append A64 compatible as fallback.
>
> Signed-off-by: Jagan Teki
> ---
> Changes for v3:
On Tue, Dec 31, 2019 at 06:35:25PM +0530, Jagan Teki wrote:
> The MIPI DSI PHY controller on Allwinner R40 is similar
> on the one on A31.
>
> Add R40 compatible and append A31 compatible as fallback.
>
> Signed-off-by: Jagan Teki
> ---
> Changes for v3:
> - update the binding in new yaml format
From: Jordan Crouse
Everywhere an IOMMU object is created by msm_gpu_create_address_space
the IOMMU device is attached immediately after. Instead of carrying around
the infrastructure to do the attach from the device specific code do it
directly in the msm_iommu_init() function. This gets it out
The register read-modify-write construct is generic enough
that it can be used by other subsystems as needed, create
a more generic rmw() function and have the gpu_rmw() use
this new function.
Signed-off-by: Sharat Masetty
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c | 8
This patch calls the right function to destroy the iommu domain as well
as free the associated iommu structure there by facilitating proper
clean up of resources upon failure of creating an address space.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
1 file
From: Jordan Crouse
Refactor how address space initialization works. Instead of having the
address space function create the MMU object (and thus require separate but
equal functions for gpummu and iommu) use a single function and pass the
MMU struct. Make the generic code cleaner by using
The last level system cache can be partitioned to 32 different slices
of which GPU has two slices preallocated. One slice is used for caching GPU
buffers and the other slice is used for caching the GPU SMMU pagetables.
This patch talks to the core system cache driver to acquire the slice handles,
From: Jordan Crouse
Pass the propposed io_pgtable_cfg to the implementation specific
init_context() function to give the implementation an opportunity to
to modify it before it gets passed to io-pgtable.
Signed-off-by: Jordan Crouse
Signed-off-by: Sai Prakash Ranjan
---
From: Vivek Gautam
Add iommu domain attribute for using system cache aka last level
cache on QCOM SoCs by client drivers like GPU to set right
attributes for caching the hardware pagetables into the system cache.
Signed-off-by: Vivek Gautam
Co-developed-by: Sai Prakash Ranjan
Signed-off-by:
Some hardware variants contain a system level cache or the last level
cache(llc). This cache is typically a large block which is shared by multiple
clients on the SOC. GPU uses the system cache to cache both the GPU data
buffers(like textures) as well the SMMU pagetables. This helps with
improved
This patch add display nodes for mt8183
Signed-off-by: Yongqiang Niu
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 103 +++
1 file changed, 103 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index
This patch add connection from OVL0 to OVL_2L0
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index
This patch add support for mediatek SOC MT8183
1.ovl_2l share driver with ovl
2.rdma1 share drive with rdma0, but fifo size is different
3.add mt8183 mutex private data, and mmsys private data
4.add mt8183 main and external path module for crtc create
Signed-off-by: Yongqiang Niu
---
move dsi/dpi select input into mtk_ddp_sel_in
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index
From: Roman Stratiienko
According to DRM documentation the only difference between PRIMARY
and OVERLAY plane is that each CRTC must have PRIMARY plane and
OVERLAY are optional.
Allow PRIMARY plane to have dimension different from full-screen.
Fixes: 5bb5f5dafa1a ("drm/sun4i: Reorganize UI
This patch add connection from DITHER0 to DSI0
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index
Remove unnecessary comparisons to true/false in if statements.
Issues found by coccinelle.
Signed-off-by: Wambui Karuga
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_sdvo.c | 4 ++--
3 files changed, 4
This patch add mmsys private data for ddp path config
all these register offset and value will be different in future SOC
add these define into mmsys private data
u32 ovl0_mout_en;
u32 rdma1_sout_sel_in;
u32 rdma1_sout_dsi0;
u32 dpi0_sel_in;
u32
On Thu, 2020-01-02 at 13:33 +0800, CK Hu wrote:
> Hi, Yongqiang:
>
> On Thu, 2020-01-02 at 12:00 +0800, Yongqiang Niu wrote:
> > This patch add mmsys private data for ddp path config
> > all these register offset and value will be different in future SOC
> > add these define into mmsys private
syzbot has found a reproducer for the following crash on:
HEAD commit:738d2902 Merge git://git.kernel.org/pub/scm/linux/kernel/g..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=14e396c1e0
kernel config:
On Thu, 2020-01-02 at 13:03 +0800, CK Hu wrote:
> Hi, Yongqiang:
>
> On Thu, 2020-01-02 at 12:00 +0800, Yongqiang Niu wrote:
> > move dsi/dpi select input into mtk_ddp_sel_in
> >
> > Signed-off-by: Yongqiang Niu
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 10 ++
> > 1 file
This patch add connection from RDMA0 to COLOR0
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index
Hi!
Dne sreda, 01. januar 2020 ob 21:47:50 CET je
roman.stratiie...@globallogic.com napisal(a):
> From: Roman Stratiienko
>
> According to DRM documentation the only difference between PRIMARY
> and OVERLAY plane is that each CRTC must have PRIMARY plane and
> OVERLAY are optional.
>
> Allow
the fifo size of rdma in mt8183 is different.
rdma0 fifo size is 5k
rdma1 fifo size is 2k
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
Since the if statement only checks for the value of the `id` variable,
it can be replaced by the more concise BUG_ON() macro for error
reporting.
Issue found using coccinelle.
Signed-off-by: Wambui Karuga
---
drivers/gpu/drm/omapdrm/dss/dispc.c | 3 +--
1 file changed, 1 insertion(+), 2
On Thu, 2020-01-02 at 14:40 +0800, CK Hu wrote:
> Hi, Yongqiang:
>
> On Thu, 2020-01-02 at 14:21 +0800, Yongqiang Niu wrote:
> > On Thu, 2020-01-02 at 14:02 +0800, CK Hu wrote:
> > > Hi, Yongqiang:
> > >
> > > On Thu, 2020-01-02 at 13:39 +0800, Yongqiang Niu wrote:
> > > > On Thu, 2020-01-02 at
This series are based on 5.5-rc1 and provid 14 patch
to support mediatek SOC MT8183
Change since v5
- fix reviewed issue in v5
Change since v4
- fix reviewed issue in v4
Change since v3
- fix reviewed issue in v3
- fix type error in v3
- fix conflict with iommu patch
Change since v2
- fix
Use resource_size rather than a verbose computation on
the end and start fields.
The semantic patch that makes these changes is as follows:
(http://coccinelle.lip6.fr/)
@@
struct resource ptr;
@@
- ((ptr.end) - (ptr.start) + 1)
+ resource_size()
@@
struct resource *ptr;
@@
- ((ptr->end) -
Use resource_size rather than a verbose computation on
the end and start fields.
The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)
@@ struct resource ptr; @@
- (ptr.end - ptr.start + 1)
+ resource_size()
Signed-off-by: Julia Lawall
---
On Thu, 2020-01-02 at 13:20 +0800, CK Hu wrote:
> Hi, Yongqiang:
>
> On Thu, 2020-01-02 at 12:00 +0800, Yongqiang Niu wrote:
> > the fifo size of rdma in mt8183 is different.
> > rdma0 fifo size is 5k
> > rdma1 fifo size is 2k
> >
> > Signed-off-by: Yongqiang Niu
> > ---
> >
From: Roman Stratiienko
Create callback to update engine's registers on mode change.
Signed-off-by: Roman Stratiienko
Reviewed-by: Jernej Skrabec
---
v2:
- Split commit in 2 parts.
- Add description to mode_set callback
- Dropped 1 line from sun4i_crtc_mode_set_nofb()
- Add struct
On Thu, 2020-01-02 at 14:02 +0800, CK Hu wrote:
> Hi, Yongqiang:
>
> On Thu, 2020-01-02 at 13:39 +0800, Yongqiang Niu wrote:
> > On Thu, 2020-01-02 at 13:03 +0800, CK Hu wrote:
> > > Hi, Yongqiang:
> > >
> > > On Thu, 2020-01-02 at 12:00 +0800, Yongqiang Niu wrote:
> > > > move dsi/dpi select
there will be more sout case in the future,
make the sout function format same mtk_ddp_sel_in
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git
This patch add connection from OVL_2L1 to RDMA1
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index
This patch add connection from RDMA1 to DSI0
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index
This patch move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel
rdma only has single output, but no multi output,
all these rdma->dsi/dpi usecase should move to mtk_ddp_sout_sel
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 90
Hi,
On Tue, Dec 24, 2019 at 12:29:40PM +, Yuti Suresh Amonkar wrote:
> > -Original Message-
> > From: Maxime Ripard
> > Sent: Monday, December 23, 2019 22:49
> > To: Yuti Suresh Amonkar
> > Cc: linux-ker...@vger.kernel.org; dri-devel@lists.freedesktop.org;
> > prane...@ti.com;
this patch add add connection from OVL_2L0 to RDMA0
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
Use resource_size rather than a verbose computation on
the end and start fields.
The semantic patch that makes these changes is as follows:
(http://coccinelle.lip6.fr/)
@@ struct resource ptr; @@
- (ptr.end - ptr.start + 1)
+ resource_size()
Signed-off-by: Julia Lawall
---
This patch add connection from RDMA0 to DSI0
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index
On Tue, Dec 31, 2019 at 06:35:22PM +0530, Jagan Teki wrote:
> tcon_tv0, tcon_tv1 nodes have a clock names of tcon-ch0,
> tcon-ch1 which are referring tcon_top clocks via index
> numbers like 0, 1 with CLK_TCON_TV0 and CLK_TCON_TV1
> respectively.
>
> Use the macro in place of index numbers, for
On Tue, Dec 31, 2019 at 06:35:21PM +0530, Jagan Teki wrote:
> TCON LCD0, LCD1 in allwinner R40, are used for managing
> LCD interfaces like RGB, LVDS and DSI.
>
> Like TCON TV0, TV1 these LCD0, LCD1 are also managed via
> tcon top.
>
> Add support for it, in tcon driver.
>
> Signed-off-by: Jagan
On 02-01-2020 14:48, Jani Nikula wrote:
On Mon, 30 Dec 2019, Animesh Manna wrote:
vswing/pre-emphasis adjustment calculation is needed in processing
of auto phy compliance request other than link training, so moved
the same function in intel_dp.c.
I guess I'm still asking why you think this
To complement panel-simple.yaml, create panel-simple-dsi.yaml.
panel-simple-dsi-yaml are for all simple DSP panels with a single
power-supply and optional backlight / enable GPIO.
Migrate panasonic,vvx10f034n00 over to the new file.
The objectives with one file for all the simple DSI panels are:
There is an increasing number of new simple panels.
Common for many of these simple panels are that they have one
mandatory power-supply and some of them have backlight and / or
an enable gpio.
The binding file to describe these panels adds overhead
that really do not add value.
The binding are
This patchset introduces two files:
panel-simple.yaml
panel-simple-dsi.yaml
The two files will be used for bindings for simple
panels that have only a single power-supply.
For now only a few bindings are migrated - the
reamining bindings will be migrated when we have agreed
on the
Hi,
On Wed, Jan 01, 2020 at 10:47:50PM +0200, roman.stratiie...@globallogic.com
wrote:
> From: Roman Stratiienko
>
> According to DRM documentation the only difference between PRIMARY
> and OVERLAY plane is that each CRTC must have PRIMARY plane and
> OVERLAY are optional.
>
> Allow PRIMARY
On Thu, 02 Jan 2020, Wambui Karuga wrote:
> Remove unnecessary comparisons to true/false in if statements.
> Issues found by coccinelle.
>
> Signed-off-by: Wambui Karuga
Thanks for the patch.
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
>
Signed-off-by: Christian Gmeiner
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index 253301be9e95..cecef5034db1 100644
---
Take product id, customer id and eco id into account. If that
delivers no match try a search for model and revision.
Signed-off-by: Christian Gmeiner
---
drivers/gpu/drm/etnaviv/etnaviv_hwdb.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git
They will be used for extended HWDB support. The eco id logic was taken
from galcore kernel driver sources.
Signed-off-by: Christian Gmeiner
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 17 +
drivers/gpu/drm/etnaviv/etnaviv_gpu.h | 6 +++---
2 files changed, 20 insertions(+), 3
This patch series extends the hwdb for an entry for the gc400 found
in the ST STM32 SoC. With this patches we report the same limits and
features for this GPU as the galcore kernel driver does.
Christian Gmeiner (6):
drm/etnaviv: update hardware headers from rnndb
drm/etnaviv: determine
The information was taken from STM32 glacore driver hw database.
The entry is named as gc7000nano_0x4652.
Signed-off-by: Christian Gmeiner
---
drivers/gpu/drm/etnaviv/etnaviv_hwdb.c | 31 ++
1 file changed, 31 insertions(+)
diff --git
Use ~0U as marker for 'I do not care'. I am not sure what
GC7000 based devices are in the wild and I do not want to
break them. In the near future we should extend the hwdb.
Signed-off-by: Christian Gmeiner
---
drivers/gpu/drm/etnaviv/etnaviv_hwdb.c | 3 +++
1 file changed, 3 insertions(+)
Update the state HI header from rnndb commit
7f1ce75 ("rnndb: document some GPU identity register")
Signed-off-by: Christian Gmeiner
---
drivers/gpu/drm/etnaviv/state_hi.xml.h | 29 --
1 file changed, 18 insertions(+), 11 deletions(-)
diff --git
On Sun, Dec 29, 2019 at 02:02:33PM +0100, Jernej Škrabec wrote:
> Dne nedelja, 29. december 2019 ob 13:47:38 CET je Roman Stratiienko
> napisal(a):
> > On Sun, Dec 29, 2019 at 2:18 PM Jernej Škrabec
> wrote:
> > > Dne nedelja, 29. december 2019 ob 13:08:19 CET je Roman Stratiienko
> > >
> > >
On Mon, 30 Dec 2019, Animesh Manna wrote:
> As per request from DP phy compliance test few special
> test pattern need to set by source. Added function
> to set pattern in DP_COMP_CTL register. It will be
> called along with other test parameters like vswing,
> pre-emphasis programming in
On Mon, 30 Dec 2019, Animesh Manna wrote:
> vswing/pre-emphasis adjustment calculation is needed in processing
> of auto phy compliance request other than link training, so moved
> the same function in intel_dp.c.
I guess I'm still asking why you think this is better located in
intel_dp.c than
On Mon, 16 Dec 2019, Hans de Goede wrote:
> When the LCD has not been turned on by the firmware/GOP, because e.g. the
> device was booted with an external monitor connected over HDMI, we should
> not turn on the panel-enable GPIO when we request it.
>
> Turning on the panel-enable GPIO when we
https://bugzilla.kernel.org/show_bug.cgi?id=201957
--- Comment #25 from Janpieter Sollie (janpieter.sol...@dommel.be) ---
Created attachment 286575
--> https://bugzilla.kernel.org/attachment.cgi?id=286575=edit
kernel config 5.4.7 Fiji
Some additional info for my case:
- Running kernel 5.4.7
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