On 01.09.20 16:45, Roger Pau Monné wrote:
On Tue, Sep 01, 2020 at 10:33:26AM +0200, Roger Pau Monne wrote:
+static int fill_list(unsigned int nr_pages)
+{
+ struct dev_pagemap *pgmap;
+ void *vaddr;
+ unsigned int i, alloc_pages = round_up(nr_pages, PAGES_PER_SECTION);
+
On Sat, 29 Aug 2020 16:24:52 +0200, Krzysztof Kozlowski wrote:
> Additional properties actually might appear (e.g. assigned-clocks) so
> use unevaluatedProperties to fix dtbs_check warnings like:
>
> arch/arm64/boot/dts/exynos/exynos5433-tm2.dt.yaml:
> system-controller@105c:
>
On 9/1/20 3:59 AM, Karol Herbst wrote:
On Tue, Sep 1, 2020 at 9:13 AM Daniel Vetter wrote:
On Tue, Aug 18, 2020 at 04:37:51PM +0200, Thierry Reding wrote:
On Fri, Aug 14, 2020 at 07:25:17PM +0200, Daniel Vetter wrote:
On Fri, Aug 14, 2020 at 7:17 PM Daniel Stone wrote:
Hi,
On Fri, 14
On Tue, Sep 1, 2020 at 3:32 AM Kai-Heng Feng
wrote:
>
> Suspend with s2idle or by the following steps cause screen frozen:
> # echo devices > /sys/power/pm_test
> # echo freeze > /sys/power/mem
>
> [ 289.625461] [drm:uvd_v1_0_ib_test [radeon]] *ERROR* radeon: fence wait
> timed out.
> [
https://bugzilla.kernel.org/show_bug.cgi?id=201957
Evgeniy A. Dushistov (dushis...@mail.ru) changed:
What|Removed |Added
CC|
On 2020-09-01 3:54 a.m., Daniel Vetter wrote:
> On Wed, Aug 26, 2020 at 11:24:23AM +0300, Pekka Paalanen wrote:
>> On Tue, 25 Aug 2020 12:58:19 -0400
>> "Kazlauskas, Nicholas" wrote:
>>
>>> On 2020-08-22 5:59 a.m., Michel Dänzer wrote:
On 2020-08-21 8:07 p.m., Kazlauskas, Nicholas wrote:
On Tue, Sep 1, 2020 at 3:44 AM Daniel Vetter wrote:
>
> On Wed, Aug 19, 2020 at 01:00:42AM -0400, Luben Tuikov wrote:
> > a) Embed struct drm_device into struct amdgpu_device.
> > b) Modify the inline-f drm_to_adev() accordingly.
> > c) Modify the inline-f adev_to_drm() accordingly.
> > d)
Am 01.09.20 um 15:32 schrieb Daniel Vetter:
On Mon, Aug 31, 2020 at 12:02:03PM +0200, Christian König wrote:
Am 31.08.20 um 06:17 schrieb Randy Dunlap:
Add @cookie to dma_fence_end_signalling() to prevent kernel-doc
warning in drivers/dma-buf/dma-fence.c:
../drivers/dma-buf/dma-fence.c:291:
On Wed, Aug 26, 2020 at 09:09:17AM +0200, Linus Walleij wrote:
> The Tosa backlight LCDE driver was converted to use GPIO descriptors
> in 0b0cb52bd80eda76c4b9921f5cf9c1b709d44e83
> ("video: backlight: tosa: Use GPIO lookup table") but
> still includes rather than .
> Fix it.
>
> Cc: Arnd
On Wed, Aug 26, 2020 at 09:05:40AM +0200, Linus Walleij wrote:
> The Tosa backlight driver was converted to use GPIO descriptors
> in 0b0cb52bd80eda76c4b9921f5cf9c1b709d44e83
> ("video: backlight: tosa: Use GPIO lookup table") but
> still includes rather than .
> Fix it.
>
> Cc: Arnd Bergmann
>
On Mon, Aug 31, 2020 at 12:02:03PM +0200, Christian König wrote:
> Am 31.08.20 um 06:17 schrieb Randy Dunlap:
> > Add @cookie to dma_fence_end_signalling() to prevent kernel-doc
> > warning in drivers/dma-buf/dma-fence.c:
> >
> > ../drivers/dma-buf/dma-fence.c:291: warning: Function parameter or
On Tue, Sep 01, 2020 at 08:57:37AM +, Simon Ser wrote:
> On Monday, August 31, 2020 3:48 PM, Ville Syrjälä
> wrote:
>
> > > > It doesn't seem like this IGT test's goal is to exercise support for
> > > > gamma LUTs. Does the test just tries to reset the gamma LUT to linear?
> > > > If so, I
On Tue, Sep 01, 2020 at 03:30:17PM +0800, crj wrote:
> Hi,
>
> 在 2020/9/1 3:53, Ville Syrjälä 写道:
> > On Fri, Aug 28, 2020 at 09:07:13AM +0800, crj wrote:
> > > Hi Ville Syrjälä,
> > >
> > > 在 2020/8/27 18:57, Ville Syrjälä 写道:
> > > > On Wed, Aug 26, 2020 at 10:23:28PM +0800, Algea Cao wrote:
>
Hi Swapnil,
On 31/08/2020 11:23, Swapnil Jakhade wrote:
> + line_thresh1 = ((vs + 1) << 5) * 8 / bpp;
> + line_thresh2 = (pxlclock << 5) / 1000 / rate * (vs + 1) - (1 << 5);
> + line_thresh = line_thresh1 - line_thresh2 / mhdp->link.num_lanes;
> + line_thresh = (line_thresh >> 5)
In the future, we'll be needing more of the extended receiver capability
field starting at DPCD address 0x2200. (Specifically, we'll need main
link channel coding cap for DP 2.0.) Start using it now to not miss out
later on.
Cc: Lyude Paul
Signed-off-by: Jani Nikula
---
I guess this can be
On 01/09/2020 10:46, Tomi Valkeinen wrote:
> I think the above suggests that the driver is not properly updating all the
> registers based on the
> new mode and link. I tried adding cdns_mhdp_validate_mode_params() call to
> cdns_mhdp_atomic_enable(), so that tu-size etc will be calculated, but
On Wed, Aug 26, 2020 at 11:44:07AM +1000, Dave Airlie wrote:
> From: Dave Airlie
>
> This can be gotten back from bdev.
>
> Signed-off-by: Dave Airlie
> ---
> drivers/gpu/drm/radeon/radeon_ttm.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git
Hi Swapnil,
On 31/08/2020 11:23, Swapnil Jakhade wrote:
> +static int cdns_mhdp_validate_mode_params(struct cdns_mhdp_device *mhdp,
> + const struct drm_display_mode *mode,
> + struct drm_bridge_state *bridge_state)
> +{
On Fri, Aug 07, 2020 at 03:05:45PM +0530, Karthik B S wrote:
> Add enable/disable flip done functions and the flip done handler
> function which handles the flip done interrupt.
>
> Enable the flip done interrupt in IER.
>
> Enable flip done function is called before writing the
> surface
On Fri, Aug 07, 2020 at 03:05:49PM +0530, Karthik B S wrote:
> This hook is added to avoid writing other plane registers in case of
> async flips, so that we do not write the double buffered registers
> during async surface address update.
>
> Signed-off-by: Karthik B S
> Signed-off-by: Vandita
On Fri, Aug 07, 2020 at 03:05:48PM +0530, Karthik B S wrote:
> Since the flip done event will be sent in the flip_done_handler,
> no need to add the event to the list and delay it for later.
>
> v2: -Moved the async check above vblank_get as it
> was causing issues for PSR.
>
> v3: -No need
On Fri, Aug 07, 2020 at 03:05:47PM +0530, Karthik B S wrote:
> If flip is requested on any other plane, reject it.
>
> Make sure there is no change in fbc, offset and framebuffer modifiers
> when async flip is requested.
>
> If any of these are modified, reject async flip.
>
> v2: -Replace
On Fri, Aug 07, 2020 at 03:05:46PM +0530, Karthik B S wrote:
> Set the Async Address Update Enable bit in plane ctl
> when async flip is requested.
>
> v2: -Move the Async flip enablement to individual patch (Paulo)
>
> v3: -Rebased.
>
> v4: -Add separate plane hook for async flip case (Ville)
On Fri, Aug 07, 2020 at 03:05:45PM +0530, Karthik B S wrote:
> Add enable/disable flip done functions and the flip done handler
> function which handles the flip done interrupt.
>
> Enable the flip done interrupt in IER.
>
> Enable flip done function is called before writing the
> surface
On Tue, Sep 1, 2020 at 9:13 AM Daniel Vetter wrote:
>
> On Tue, Aug 18, 2020 at 04:37:51PM +0200, Thierry Reding wrote:
> > On Fri, Aug 14, 2020 at 07:25:17PM +0200, Daniel Vetter wrote:
> > > On Fri, Aug 14, 2020 at 7:17 PM Daniel Stone wrote:
> > > >
> > > > Hi,
> > > >
> > > > On Fri, 14 Aug
On Sat, Aug 29, 2020 at 04:24:57PM +0200, Krzysztof Kozlowski wrote:
> Additional properties actually might appear (e.g. power-domains) so use
> unevaluatedProperties to fix dtbs_check warnings like:
Please submit patches using subject lines reflecting the style for the
subsystem, this makes it
On Thu, Apr 30, 2020 at 02:50:52PM +0100, Emil Velikov wrote:
> Hi Ville
>
> I don't fully grok the i915 changes to provide meaningful review.
> There are couple of small comments below, but regardless of those
Sorry, forgot to reply to this in a timely manner.
>
> Patches 01-11 and 14-16 are:
Hi,
On Tue, 1 Sep 2020 at 08:13, Daniel Vetter wrote:
> I think right thing to do is *shrug*, please use modifiers. They're meant
> to solve these kind of problems for real, adding more hacks to paper over
> userspace not using modifiers doesn't seem like a good idea.
>
> Wrt dri3, since we do
On Tue, Sep 01, 2020 at 10:56:42AM +0200, Michel Dänzer wrote:
> On 2020-09-01 9:57 a.m., Daniel Vetter wrote:
> > On Tue, Aug 25, 2020 at 04:55:28PM +0200, Michel Dänzer wrote:
> >> On 2020-08-24 9:43 a.m., Pekka Paalanen wrote:
> >>
> >>> Sounds like the helpers you refer to are inadequate for
Hi Rob,
On Mon, Aug 24, 2020 at 05:04:58PM -0600, Rob Herring wrote:
> On Mon, Aug 10, 2020 at 04:22:17PM +0100, Biju Das wrote:
> > Document optional vcc-supply property that may be used as VCC source.
> >
> > Signed-off-by: Biju Das
> > ---
> > New patch Ref:
Hello,
On Wed, Aug 26, 2020 at 06:58:50AM +, Biju Das wrote:
> > Subject: Re: [PATCH v2 1/3] dt-bindings: display: bridge: lvds-codec:
> > Document vcc-supply property
> >
> > On Mon, Aug 10, 2020 at 04:22:17PM +0100, Biju Das wrote:
> > > Document optional vcc-supply property that may be
On Tue, Aug 18, 2020 at 09:25:10AM +0200, Gerd Hoffmann wrote:
> When going through a disable/enable cycle without changing the
> framebuffer the optimization added by commit 3954ff10e06e ("drm/virtio:
> skip set_scanout if framebuffer didn't change") causes the screen stay
> blank. Add a bool to
On Sat, Aug 29, 2020 at 07:25:30PM +0200, Krzysztof Kozlowski wrote:
> The fixed clocks are kept under dedicated node fixed-rate-clocks, thus a
> fake "reg" was added. This is not correct with dtschema as fixed-clock
> binding does not have a "reg" property:
>
>
On Sat, Aug 29, 2020 at 04:24:59PM +0200, Krzysztof Kozlowski wrote:
> System register nodes, implementing syscon binding, should use
> appropriate compatible. This fixes dtbs_check warnings:
>
> arch/arm64/boot/dts/exynos/exynos5433-tm2.dt.yaml: syscon@13b8:
> compatible: ['syscon']
On Sat, Aug 29, 2020 at 04:24:58PM +0200, Krzysztof Kozlowski wrote:
> "gpios" property is deprecated. Update the Exynos5433 DTS to fix
> dtbs_checks warnings like:
>
> arch/arm64/boot/dts/exynos/exynos5433-tm2.dt.yaml: i2c-gpio-0: 'sda-gpios'
> is a required property
>
On Sat, Aug 29, 2020 at 04:24:52PM +0200, Krzysztof Kozlowski wrote:
> Additional properties actually might appear (e.g. assigned-clocks) so
> use unevaluatedProperties to fix dtbs_check warnings like:
>
> arch/arm64/boot/dts/exynos/exynos5433-tm2.dt.yaml:
> system-controller@105c:
>
On 9/1/2020 2:08 PM, Viresh Kumar wrote:
On 01-09-20, 13:01, Rajendra Nayak wrote:
So FWIU, dpu_unbind() gets called even when dpu_bind() fails for some reason.
Ahh, I see.
I tried to address that earlier [1] which I realized did not land.
I don't think that patch was required, as you
On Mon, Jul 27, 2020 at 04:03:37PM +1000, Sam McNally wrote:
> For DP MST outputs, the i2c device currently only supports transfers
> that can be implemented using remote i2c reads. Such transfers must
> consist of zero or more write transactions followed by one read
> transaction. DDC/CI commands
On Monday, August 31, 2020 3:48 PM, Ville Syrjälä
wrote:
> > > It doesn't seem like this IGT test's goal is to exercise support for
> > > gamma LUTs. Does the test just tries to reset the gamma LUT to linear?
> > > If so, I think the IGT test should be fixed to ignore "I don't support
> > >
On 2020-09-01 9:57 a.m., Daniel Vetter wrote:
> On Tue, Aug 25, 2020 at 04:55:28PM +0200, Michel Dänzer wrote:
>> On 2020-08-24 9:43 a.m., Pekka Paalanen wrote:
>>
>>> Sounds like the helpers you refer to are inadequate for your case.
>>> Can't you fix the helpers in the long run and land this
On Sun, Aug 23, 2020 at 04:41:59PM -0700, Randy Dunlap wrote:
> From: Randy Dunlap
>
> /home/rdunlap/lnx/lnx-59-rc2/Documentation/driver-api/dma-buf.rst:182:
> WARNING: Title underline too short.
> Indefinite DMA Fences
>
>
> Fixes: 72b6ede73623 ("dma-buf.rst: Document why
On Tue, Aug 25, 2020 at 04:55:28PM +0200, Michel Dänzer wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA1
>
> On 2020-08-24 9:43 a.m., Pekka Paalanen wrote:
> > On Sat, 22 Aug 2020 11:59:26 +0200 Michel Dänzer
> > wrote:
> >> On 2020-08-21 8:07 p.m., Kazlauskas, Nicholas wrote:
> >>> On
On Wed, Aug 26, 2020 at 11:24:23AM +0300, Pekka Paalanen wrote:
> On Tue, 25 Aug 2020 12:58:19 -0400
> "Kazlauskas, Nicholas" wrote:
>
> > On 2020-08-22 5:59 a.m., Michel Dänzer wrote:
> > > On 2020-08-21 8:07 p.m., Kazlauskas, Nicholas wrote:
> > >> On 2020-08-21 12:57 p.m., Michel Dänzer
On Wed, Aug 19, 2020 at 02:55:15PM +0300, Laurent Pinchart wrote:
> Hi Dinghao,
>
> Thank you for the patch.
>
> On Wed, Aug 19, 2020 at 04:22:28PM +0800, Dinghao Liu wrote:
> > When verify_crc_source() fails, source needs to be freed.
> > However, current code is returning directly and ends up
On Wed, Aug 19, 2020 at 01:00:42AM -0400, Luben Tuikov wrote:
> a) Embed struct drm_device into struct amdgpu_device.
> b) Modify the inline-f drm_to_adev() accordingly.
> c) Modify the inline-f adev_to_drm() accordingly.
> d) Eliminate the use of drm_device.dev_private,
>in amdgpu.
> e)
On Tue, Aug 18, 2020 at 11:20:16AM +0200, Gerd Hoffmann wrote:
> Add max_segment argument to drm_prime_pages_to_sg(). When set pass it
> through to the __sg_alloc_table_from_pages() call, otherwise use
> SCATTERLIST_MAX_SEGMENT.
>
> Also add max_segment field to drm driver and pass it to
>
On 2020-08-18 at 11:38:48 -0400, Sean Paul wrote:
> From: Sean Paul
>
> Only one functional change, reversed the hdcp_1x/2x_present bits in the
> QUERY_STREAM_ENCRYPTION_STATUS parsing with a comment explaining my
> confusion.
>
> Other than that, lots of rebasing, the most notable being the
>
On Fri, Aug 28, 2020 at 01:27:59PM +0200, Gerd Hoffmann wrote:
> On Mon, Aug 24, 2020 at 09:24:40AM +0200, Jiri Slaby wrote:
> > On 18. 08. 20, 9:25, Gerd Hoffmann wrote:
> > > When going through a disable/enable cycle without changing the
> > > framebuffer the optimization added by commit
On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:
> From: Rob Clark
>
> In a later patch, the drvdata will not directly be 'struct msm_gpu *',
> so add a helper to reduce the churn.
>
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 10 --
>
On Tue 01 Sep 03:42 UTC 2020, Rob Clark wrote:
> On Mon, Aug 31, 2020 at 7:35 PM Bjorn Andersson
> wrote:
> >
> > On Fri 14 Aug 02:40 UTC 2020, Rob Clark wrote:
> >
> > > From: Rob Clark
> > >
> > > Currently it doesn't matter, since we free the ctx immediately. But
> > > when we start
On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:
> From: Jordan Crouse
>
> Each submitqueue is attached to a context. Add a pointer to the
> context to the submitqueue at create time and refcount it so
> that it stays around through the life of the queue.
>
Reviewed-by: Bjorn Andersson
>
On Sun, Aug 16, 2020 at 02:22:46PM -0300, Ezequiel Garcia wrote:
> This heap is basically a wrapper around DMA-API dma_alloc_attrs,
> which will allocate memory suitable for the given device.
>
> The implementation is mostly a port of the Contiguous Videobuf2
> memory allocator (see
If in fotg210_udc_probe() after initialization
INIT_LIST_HEAD(>queue)
and after a registration of an interrupt handler in fotg210_irq()
fotg210_in_fifo_handler() is calling then in fotg210_in_fifo_handler()
list_entry() tries to get struct fotg210_request from ep->queue.next,
but
after
Hi Andy,
On 8/29/20 12:12 AM, Andy Shevchenko wrote:
Static analyzer is not happy about intel_iommu_gfx_mapped declaration:
.../drivers/iommu/intel/iommu.c:364:5: warning: symbol 'intel_iommu_gfx_mapped'
was not declared. Should it be static?
Move its declaration to Intel IOMMU header file.
Suspend with s2idle or by the following steps cause screen frozen:
# echo devices > /sys/power/pm_test
# echo freeze > /sys/power/mem
[ 289.625461] [drm:uvd_v1_0_ib_test [radeon]] *ERROR* radeon: fence wait timed
out.
[ 289.625494] [drm:radeon_ib_ring_tests [radeon]] *ERROR* radeon: failed
On Fri, Aug 28, 2020 at 02:50:32PM +0200, Ondrej Jirman wrote:
> It's writing too much data. regmap_bulk_write expects number of
> register sized chunks to write, not a byte sized length of the
> bounce buffer. Bounce buffer needs to be padded too, so that
> regmap_bulk_write will not read past
syzbot is reporting OOB read at vga_8planes_imageblit() [1], for
"cdat[y] >> 4" can become a negative value due to "const char *cdat".
[1]
https://syzkaller.appspot.com/bug?id=0d7a0da1557dcd1989e00cb3692b26d4173b4132
Reported-by: syzbot
Signed-off-by: Tetsuo Handa
---
On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:
> From: Jordan Crouse
>
> Add support to create a io-pgtable for use by targets that support
> per-instance pagetables. In order to support per-instance pagetables the
> GPU SMMU device needs to have the qcom,adreno-smmu compatible string and
>
On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:
> From: Rob Clark
>
> Sprinkle a few `const`s where helpers don't need write access.
>
Reviewed-by: Bjorn Andersson
> Signed-off-by: Rob Clark
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu.h | 6 +++---
> 1 file changed, 3 insertions(+), 3
Hi Maxime,
On 7/9/20 2:42 AM, Maxime Ripard wrote:
> The HSM clock needs to be setup at around 101% of the pixel rate. This
> was done previously by setting the clock rate to 163.7MHz at probe time and
> only check in mode_valid whether the mode pixel clock was under the pixel
> clock +1% or not.
On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:
> From: Jordan Crouse
>
> Add a special implementation for the SMMU attached to most Adreno GPU
> target triggered from the qcom,adreno-smmu compatible string.
>
> The new Adreno SMMU implementation will enable split pagetables
> (TTBR1) for the
On 28-08-20, 11:37, Viresh Kumar wrote:
> Hello,
>
> This cleans up some of the user code around calls to
> dev_pm_opp_of_remove_table().
>
> All the patches can be picked by respective maintainers directly except
> for the last patch, which needs the previous two to get merged first.
>
> These
On Fri 14 Aug 02:40 UTC 2020, Rob Clark wrote:
> From: Rob Clark
>
> Currently it doesn't matter, since we free the ctx immediately. But
> when we start refcnt'ing the ctx, we don't want old dangling list
> entries to hang around.
>
> Signed-off-by: Rob Clark
Reviewed-by: Bjorn Andersson
Hi Maxime,
On 7/9/20 2:42 AM, Maxime Ripard wrote:
> The HDMI controllers found in the BCM2711 SoC need some adjustments to the
> bindings, especially since the registers have been shuffled around in more
> register ranges.
>
> Reviewed-by: Rob Herring
> Signed-off-by: Maxime Ripard
> ---
>
On 8/28/2020 11:37 AM, Viresh Kumar wrote:
dev_pm_opp_of_remove_table() doesn't report any errors when it fails to
find the OPP table with error -ENODEV (i.e. OPP table not present for
the device). And we can call dev_pm_opp_of_remove_table()
unconditionally here.
Its a little tricky to call
On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:
> From: Jordan Crouse
>
> Every Qcom Adreno GPU has an embedded SMMU for its own use. These
> devices depend on unique features such as split pagetables,
> different stall/halt requirements and other settings. Identify them
> with a compatible
Hi Bilal,
On 31/8/20 11:32, Bilal Wasim wrote:
>
> Hi Enric,
>
> On Thu, 27 Aug 2020 10:59:11 +0200
> Enric Balletbo i Serra wrote:
>
>> The get_edid() callback can be triggered anytime by an ioctl, i.e
>>
>> drm_mode_getconnector (ioctl)
>> -> drm_helper_probe_single_connector_modes
>>
On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:
> From: Rob Clark
>
> For the Adreno GPU's SMMU, we want SCTLR.HUPCF set to ensure that
> pending translations are not terminated on iova fault. Otherwise
> a terminated CP read could hang the GPU by returning invalid
> command-stream data.
>
On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:
> From: Jordan Crouse
>
> Now that we can get the ctx from the submitqueue, the extra arg is
> redundant.
>
Reviewed-by: Bjorn Andersson
> Signed-off-by: Jordan Crouse
> [split out of previous patch to reduce churny noise]
> Signed-off-by: Rob
On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:
> From: Jordan Crouse
>
> Use the aperture settings from the IOMMU domain to set up the virtual
> address range for the GPU. This allows us to transparently deal with
> IOMMU side features (like split pagetables).
>
Reviewed-by: Bjorn Andersson
On Tue, 2020-09-01 at 00:01 +0800, Chun-Kuang Hu wrote:
> Hi, Chunfeng:
>
> Chunfeng Yun 於 2020年8月31日 週一 上午9:48寫道：
> >
> > On Mon, 2020-08-31 at 07:03 +0800, Chun-Kuang Hu wrote:
> > > Hi, Chunfeng & Kishon:
> > >
> > > How do you feel about this patch?
> > It's fine to me,
> >
> > Reviewed-by:
On Thu 13 Aug 21:40 CDT 2020, Rob Clark wrote:
> From: Jordan Crouse
>
> Enable TTBR1 for a context bank if IO_PGTABLE_QUIRK_ARM_TTBR1 is selected
> by the io-pgtable configuration.
>
> Signed-off-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu.c |
On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:
> From: Rob Clark
>
> This will be populated by adreno-smmu, to provide a way for coordinating
> enabling/disabling TTBR0 translation.
>
Reviewed-by: Bjorn Andersson
> Signed-off-by: Rob Clark
> ---
>
On Thu 13 Aug 21:40 CDT 2020, Rob Clark wrote:
> From: Jordan Crouse
>
> Construct the io-pgtable config before calling the implementation specific
> init_context function and pass it so the implementation specific function
> can get a chance to change it before the io-pgtable is created.
>
>
Hi Enric,
On Thu, 27 Aug 2020 10:59:11 +0200
Enric Balletbo i Serra wrote:
> The get_edid() callback can be triggered anytime by an ioctl, i.e
>
> drm_mode_getconnector (ioctl)
> -> drm_helper_probe_single_connector_modes
>-> drm_bridge_connector_get_modes
> ->
On 28/08/2020 22:58, Sam Ravnborg wrote:
Hi Dmitry
On Fri, Aug 28, 2020 at 06:49:05PM +0300, Dmitry Baryshkov wrote:
Add support for Lontium LT9611UXC HDMI bridge. Lontium LT9611UXC is a
DSI to HDMI bridge which supports two DSI ports and I2S port as an input
and HDMI port as output. Despite
On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:
> From: Jordan Crouse
>
> Add support for allocating private address space instances. Targets that
> support per-context pagetables should implement their own function to
> allocate private address spaces.
>
> The default will return a pointer to
On Mon 31 Aug 13:02 UTC 2020, Sumit Semwal wrote:
> Novatek NT36672a is a generic DSI IC that drives command and video mode
> panels. Add the driver for it.
>
> Right now adding support for some Poco F1 phones that have an LCD panel
> from Tianma connected with this IC, with a resolution of
Hi Hoegeun,
It looks good to me. But, just one comment.
On 9/1/20 1:07 PM, Hoegeun Kwon wrote:
> There is a problem that the output does not work at a resolution
> exceeding FHD. To solve this, we need to adjust the bvb clock at a
> resolution exceeding FHD.
>
> Signed-off-by: Hoegeun Kwon
>
On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:
> From: Rob Clark
>
> This interface will be used for drm/msm to coordinate with the
> qcom_adreno_smmu_impl to enable/disable TTBR0 translation.
>
> Once TTBR0 translation is enabled, the GPU's CP (Command Processor)
> will directly switch TTBR0
On Fri 14 Aug 02:40 UTC 2020, Rob Clark wrote:
> From: Rob Clark
>
> Currently it doesn't matter, since we free the ctx immediately. But
> when we start refcnt'ing the ctx, we don't want old dangling list
> entries to hang around.
>
> Signed-off-by: Rob Clark
> ---
>
On Tue, 2020-09-01 at 00:02 +0800, Chun-Kuang Hu wrote:
> Hi, Chunfeng:
>
> Chunfeng Yun 於 2020年8月31日 週一 上午9:50寫道：
> >
> > On Sun, 2020-08-23 at 09:48 +0800, Chun-Kuang Hu wrote:
> > > Mediatek HDMI phy driver is moved from drivers/gpu/drm/mediatek to
> > > drivers/phy/mediatek, so add the new
On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:
> From: Rob Clark
>
> In $debugfs/gem we already show any vma(s) associated with an object.
> Also show process names if the vma's address space is a per-process
> address space.
>
Reviewed-by: Bjorn Andersson
> Signed-off-by: Rob Clark
> ---
Hi Ben Skeggs,
Gentle Reminder, Can you please take a look at the patch and provide your ack.
Thanks
Jeevan B
>-Original Message-
>From: B, Jeevan
>Sent: Sunday, August 16, 2020 12:22 PM
>To: nouv...@lists.freedesktop.org; intel-...@lists.freedesktop.org; dri-
On Mon, Aug 17, 2020 at 02:23:47AM -0400, Marek Olšák wrote:
> On Wed, Aug 12, 2020 at 9:54 AM Daniel Vetter wrote:
>
> > On Tue, Aug 11, 2020 at 09:42:11AM -0400, Marek Olšák wrote:
> > > There are a few cases when the flags can change, for example DCC can be
> > > disabled due to a hw
On Tue, Aug 18, 2020 at 04:37:51PM +0200, Thierry Reding wrote:
> On Fri, Aug 14, 2020 at 07:25:17PM +0200, Daniel Vetter wrote:
> > On Fri, Aug 14, 2020 at 7:17 PM Daniel Stone wrote:
> > >
> > > Hi,
> > >
> > > On Fri, 14 Aug 2020 at 17:22, Thierry Reding
> > > wrote:
> > > > I suspect that
From: Hans Verkuil
Signed-off-by: Hans Verkuil
[sa...@chromium.org:
- rebased
- removed polling-related changes
- moved the calls to drm_dp_cec_(un)set_edid() into the next patch
]
Signed-off-by: Sam McNally
---
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
With DP v2.0 errata E5, CEC tunneling can be supported through an MST
topology.
There are some minor differences for CEC tunneling through an MST
topology compared to CEC tunneling to an SST port:
- CEC IRQs are delivered via a sink event notify message
- CEC-related DPCD registers are accessed
From: Hans Verkuil
For adapters behind an MST hub use the correct AUX channel.
Signed-off-by: Hans Verkuil
[sa...@chromium.org: rebased, removing redundant changes]
Signed-off-by: Sam McNally
---
drivers/gpu/drm/drm_dp_mst_topology.c | 36 +++
1 file changed, 36
From: Hans Verkuil
These are required for the CEC MST support.
Signed-off-by: Hans Verkuil
Signed-off-by: Sam McNally
---
drivers/gpu/drm/drm_dp_mst_topology.c | 6 ++
include/drm/drm_dp_mst_helper.h | 4
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git
Sink event notify messages are used for MST CEC IRQs. Add parsing
support for sink event notify messages in preparation for handling MST
CEC IRQs.
Signed-off-by: Sam McNally
---
drivers/gpu/drm/drm_dp_mst_topology.c | 37 ++-
include/drm/drm_dp_mst_helper.h | 14
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