From: Junlin Yang
r is "u32" always >= 0,mipi_dsi_create_packet may return little than zero.
so r < 0 condition is never accessible.
Fixes coccicheck warnings:
./drivers/gpu/drm/omapdrm/dss/dsi.c:2155:5-6:
WARNING: Unsigned expression compared with zero: r < 0
Signed-off-by: Junlin Yang
---
d
On Thu, Mar 11, 2021 at 2:49 PM Daniel Gomez wrote:
>
> On Thu, 11 Mar 2021 at 10:09, Daniel Gomez wrote:
> >
> > On Wed, 10 Mar 2021 at 18:06, Alex Deucher wrote:
> > >
> > > On Wed, Mar 10, 2021 at 11:37 AM Daniel Gomez wrote:
> > > >
> > > > Disabling GFXOFF via the quirk list fixes a hardwa
This patch adds an initial DRM driver for the Loongson LS7A1000
bridge chip(LS7A). The LS7A bridge chip contains two display
controllers, support dual display output. The maximum support for
each channel display is to 1920x1080@60Hz.
At present, DC device detection and DRM driver registration are
c
Am 11.03.21 um 14:17 schrieb Daniel Vetter:
[SNIP]
So I did the following quick experiment on vmwgfx, and it turns out that
with it,
fast gup never succeeds. Without the "| PFN_MAP", it typically succeeds
I should probably craft an RFC formalizing this.
Yeah I think that would be good. Mayb
On Wednesday, March 10, 2021 4:10:35 AM EST Thomas Zimmermann wrote:
> Hi
>
> Am 10.03.21 um 03:50 schrieb nerdopolis:
> > On Friday, September 2, 2016 4:22:38 AM EST David Herrmann wrote:
> >> Hey
> >>
> >> On request of Noralf, I picked up the patches and prepared v5. Works fine
> >> with
> >>
On Thu, 11 Mar 2021 12:11:48 -0600
Jason Ekstrand wrote:
> > > > > > 2/ Queued jobs might be executed out-of-order (unless they have
> > > > > > explicit/implicit deps between them), and Vulkan asks that the
> > > > > > out
> > > > > > fence be signaled when all jobs are done. Timeline s
[AMD Official Use Only - Internal Distribution Only]
Hi, Andrey,
ok, I have changed it and uploaded V2 patch.
Thanks,
Jack
-Original Message-
From: Grodzovsky, Andrey
Sent: Friday, March 12, 2021 1:04 PM
To: Alex Deucher ; Zhang, Jack (Jian)
; Maling list - DRI developers
Cc: amd-gfx
re-insert Bailing jobs to avoid memory leak.
Signed-off-by: Jack Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c| 8 ++--
drivers/gpu/drm/panfrost/panfrost_job.c| 2 +-
drivers/gpu/drm/scheduler/sched_main.c | 8 +++-
inc
On Thu, 11 Mar 2021 20:31:33 -0800, Jason Ekstrand wrote:
> On March 11, 2021 20:26:06 "Dixit, Ashutosh" wrote:
> On Wed, 10 Mar 2021 13:00:49 -0800, Jason Ekstrand wrote:
>
> libdrm has supported the newer execbuffer2 ioctl and using it by default
> when it exists since libdrm commit b50964027
On 11-03-21, 22:20, Dmitry Osipenko wrote:
> +struct opp_table *devm_pm_opp_set_clkname(struct device *dev, const char
> *name)
> +{
> + struct opp_table *opp_table;
> + int err;
> +
> + opp_table = dev_pm_opp_set_clkname(dev, name);
> + if (IS_ERR(opp_table))
> + retur
On 11-03-21, 22:20, Dmitry Osipenko wrote:
> From: Yangtao Li
>
> Add devres wrapper for dev_pm_opp_register_notifier() to simplify driver
> code.
>
> Signed-off-by: Yangtao Li
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/opp/core.c | 38 ++
> inclu
Check panfrost driver at panfrost_scheduler_stop,
and panfrost_job_timedout - they also terminate prematurely
in both places so probably worth adding this there too.
Andrey
On 2021-03-11 11:13 p.m., Alex Deucher wrote:
+dri-devel
Please be sure to cc dri-devel when you send out gpu scheduler p
On Tuesday, 9 March 2021 11:49:49 PM AEDT Matthew Wilcox wrote:
> On Tue, Mar 09, 2021 at 11:14:58PM +1100, Alistair Popple wrote:
> > -static inline struct page *migration_entry_to_page(swp_entry_t entry)
> > -{
> > - struct page *p = pfn_to_page(swp_offset(entry));
> > - /*
> > -* Any use
Ilia Mirkin wrote:
> XRGB means that the memory layout should match a 32-bit integer,
> stored as LE, with the low bits being B, next bits being G, etc. This
> translates to byte 0 = B, byte 1 = G, etc. If you're on a BE system,
> and you're handed a XRGB buffer, it still expects that byte
On March 11, 2021 20:26:06 "Dixit, Ashutosh" wrote:
On Wed, 10 Mar 2021 13:00:49 -0800, Jason Ekstrand wrote:
libdrm has supported the newer execbuffer2 ioctl and using it by default
when it exists since libdrm commit b50964027bef249a0cc3d511de05c2464e0a1e22
which landed Mar 2, 2010. The i9
+dri-devel
Please be sure to cc dri-devel when you send out gpu scheduler patches.
On Thu, Mar 11, 2021 at 10:57 PM Jack Zhang wrote:
>
> re-insert Bailing jobs to avoid memory leak.
>
> Signed-off-by: Jack Zhang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +++-
> drivers/gpu/drm/am
On Thu 04 Mar 17:52 CST 2021, Douglas Anderson wrote:
> In commit 58074b08c04a ("drm/bridge: ti-sn65dsi86: Read EDID blob over
> DDC") we attempted to make the ti-sn65dsi86 bridge properly read the
> EDID from the panel. That commit kinda worked but it had some serious
> problems.
>
> The problem
On Fri, Mar 12, 2021 at 11:36:51AM +1000, Dave Airlie wrote:
> On Thu, 11 Mar 2021 at 21:28, Rodrigo Vivi wrote:
> >
> > Hi Dave and Daniel,
> >
> > Things are very quiet. Only 1 fix this round.
> > Since I will be out next week, if this trend continues I will
> > accumulate 2 weeks and send when
On Thu 04 Mar 17:52 CST 2021, Douglas Anderson wrote:
> This patch is _only_ code motion to prepare for the patch
> ("drm/bridge: ti-sn65dsi86: Properly get the EDID, but only if
> refclk") and make it easier to understand.
>
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> Signed-off-by: Dougla
On Thu 04 Mar 17:51 CST 2021, Douglas Anderson wrote:
> The clock framework makes it simple to deal with an optional clock.
> You can call clk_get_optional() and if the clock isn't specified it'll
> just return NULL without complaint. It's valid to pass NULL to
> enable/disable/prepare/unprepare.
On Wed, 10 Mar 2021 13:00:49 -0800, Jason Ekstrand wrote:
>
> libdrm has supported the newer execbuffer2 ioctl and using it by default
> when it exists since libdrm commit b50964027bef249a0cc3d511de05c2464e0a1e22
> which landed Mar 2, 2010. The i915 and i965 drivers in Mesa at the time
> both used
The pull request you sent on Fri, 12 Mar 2021 11:35:33 +1000:
> git://anongit.freedesktop.org/drm/drm tags/drm-fixes-2021-03-12-1
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/f78d76e72a4671ea52d12752d92077788b4f5d50
Thank you!
--
Deet-doot-dot, I am a bot.
https:/
On Thu, 11 Mar 2021 at 21:28, Rodrigo Vivi wrote:
>
> Hi Dave and Daniel,
>
> Things are very quiet. Only 1 fix this round.
> Since I will be out next week, if this trend continues I will
> accumulate 2 weeks and send when in -rc4.
>
> Here goes drm-intel-fixes-2021-03-11:
>
> - Wedge the GPU if c
Hi Linus,
Regular fixes for rc3. The i915 pull was based on the rc1 tag so I
just cherry-picked the single fix from there to avoid it. The misc and
amd trees seem to be on okay bases.
It's a bunch of fixes across the tree, amdgpu has most of them a few
ttm fixes around qxl, and nouveau.
Dave.
d
On Thu, Mar 11, 2021 at 5:58 PM Peter Stuge wrote:
>
> Ilia Mirkin wrote:
> > > > #define DRM_FORMAT_XRGB fourcc_code('X', 'R', '2', '4') /* [31:0]
> > > > x:R:G:B 8:8:8:8 little endian */
> > >
> > > Okay, "[31:0] x:R:G:B 8:8:8:8" can certainly mean
> > > [31:24]=x [23:16]=R [15:8]=G [7:0]=
> On Mar 11, 2021, at 17:35, Thomas Hellström (Intel)
> wrote:
>
> Hi, Zack
>
> On 3/11/21 10:07 PM, Zack Rusin wrote:
>>> On Mar 11, 2021, at 05:46, Thomas Hellström (Intel)
>>> wrote:
>>>
>>> Hi,
>>>
>>> I tried latest drm-fixes today and saw a lot of these: Fallout from ttm
>>> rework
Ilia Mirkin wrote:
> > > #define DRM_FORMAT_XRGB fourcc_code('X', 'R', '2', '4') /* [31:0]
> > > x:R:G:B 8:8:8:8 little endian */
> >
> > Okay, "[31:0] x:R:G:B 8:8:8:8" can certainly mean
> > [31:24]=x [23:16]=R [15:8]=G [7:0]=B, which when stored "little endian"
> > becomes B G R X in memory
> I'm not familiar with panfrost's needs and I don't work on a tiler and
> I know there are different issues there. But...
The primary issue is we submit vertex+compute and fragment for each
batch as two disjoint jobs (with a dependency of course), reflecting the
internal hardware structure as pa
Hi, Zack
On 3/11/21 10:07 PM, Zack Rusin wrote:
On Mar 11, 2021, at 05:46, Thomas Hellström (Intel)
wrote:
Hi,
I tried latest drm-fixes today and saw a lot of these: Fallout from ttm rework?
Yes, I fixed this in d1a73c641afd2617bd80bce8b71a096fc5b74b7e it was in
drm-misc-next in the drm-mi
On Thu, Mar 11, 2021 at 3:02 PM Peter Stuge wrote:
> > > Hence the question: What does DRM promise about the XRGB mode?
> >
> > That it's a 32-bit value. From include/uapi/drm/drm_fourcc.h:
> >
> > /* 32 bpp RGB */
> > #define DRM_FORMAT_XRGB fourcc_code('X', 'R', '2', '4') /* [31:0]
> >
> On Mar 11, 2021, at 05:46, Thomas Hellström (Intel)
> wrote:
>
> Hi,
>
> I tried latest drm-fixes today and saw a lot of these: Fallout from ttm
> rework?
Yes, I fixed this in d1a73c641afd2617bd80bce8b71a096fc5b74b7e it was in
drm-misc-next in the drm-misc tree for a while but hasn’t been
Noralf Trønnes wrote:
> > Endianness matters because parts of pix32 are used.
>
> This code:
..
> prints:
>
> xrgb=aabbccdd
> 32-bit access:
> r=bb
> g=cc
> b=dd
> Byte access on LE:
> r=cc
> g=bb
> b=aa
As expected, and:
xrgb=aabbccdd
32-bit access:
r=bb
g=cc
b=dd
Byte access on BE:
r=
On Thu, 11 Mar 2021 at 17:10, Alex Deucher wrote:
>
> On Thu, Mar 11, 2021 at 10:02 AM Alexandre Desnoyers wrote:
> >
> > On Thu, Mar 11, 2021 at 2:49 PM Daniel Gomez wrote:
> > >
> > > On Thu, 11 Mar 2021 at 10:09, Daniel Gomez wrote:
> > > >
> > > > On Wed, 10 Mar 2021 at 18:06, Alex Deucher
11.03.2021 22:44, Mark Brown пишет:
> On Thu, Mar 11, 2021 at 10:20:58PM +0300, Dmitry Osipenko wrote:
>
>> Acked-by: Mark brown
>
> Typo there.
>
Good catch! Although, that should be a patchwork fault since it
auto-added acks when I downloaded v1 patches and I haven't changed them.
I'll fix i
On Thu, Mar 11, 2021 at 10:20:58PM +0300, Dmitry Osipenko wrote:
> Acked-by: Mark brown
Typo there.
signature.asc
Description: PGP signature
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri
From: Yangtao Li
Use resource-managed API to simplify code.
Signed-off-by: Yangtao Li
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Dmitry Osipenko
---
drivers/memory/samsung/exynos5422-dmc.c | 13 +++--
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/drivers/memory/
From: Yangtao Li
Use resource-managed OPP API to simplify code.
Signed-off-by: Yangtao Li
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/lima/lima_devfreq.c | 43 -
drivers/gpu/drm/lima/lima_devfreq.h | 2 --
2 files changed, 11 insertions(+), 34 deletions(-)
From: Yangtao Li
Use resource-managed OPP API to simplify code.
Signed-off-by: Yangtao Li
Signed-off-by: Dmitry Osipenko
---
drivers/media/platform/qcom/venus/pm_helpers.c | 18 +++---
1 file changed, 3 insertions(+), 15 deletions(-)
diff --git a/drivers/media/platform/qcom/venus
From: Yangtao Li
Use resource-managed OPP API to simplify code.
Signed-off-by: Yangtao Li
Reviewed-by: Steven Price
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 33 +
drivers/gpu/drm/panfrost/panfrost_devfreq.h | 1 -
2 files changed,
From: Yangtao Li
Use resource-managed OPP API to simplify code.
Signed-off-by: Yangtao Li
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
drivers/gpu/drm/msm/d
From: Yangtao Li
Use resource-managed OPP API to simplify code.
Signed-off-by: Yangtao Li
Signed-off-by: Dmitry Osipenko
---
drivers/mmc/host/sdhci-msm.c | 20 +++-
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/s
From: Yangtao Li
Use resource-managed OPP API to simplify code.
Signed-off-by: Yangtao Li
Acked-by: Mark Brown
Signed-off-by: Dmitry Osipenko
---
drivers/spi/spi-qcom-qspi.c | 19 ++-
1 file changed, 6 insertions(+), 13 deletions(-)
diff --git a/drivers/spi/spi-qcom-qspi.c b
From: Yangtao Li
Use resource-managed OPP API to simplify code.
Signed-off-by: Yangtao Li
Acked-by: Mark brown
Signed-off-by: Dmitry Osipenko
---
drivers/spi/spi-geni-qcom.c | 17 +++--
include/linux/qcom-geni-se.h | 2 --
2 files changed, 7 insertions(+), 12 deletions(-)
diff
From: Yangtao Li
Use resource-managed OPP API to simplify code.
Signed-off-by: Yangtao Li
Signed-off-by: Dmitry Osipenko
---
drivers/tty/serial/qcom_geni_serial.c | 24 +---
1 file changed, 9 insertions(+), 15 deletions(-)
diff --git a/drivers/tty/serial/qcom_geni_serial.
From: Yangtao Li
Add devres wrapper for dev_pm_opp_register_notifier() to simplify driver
code.
Signed-off-by: Yangtao Li
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 38 ++
include/linux/pm_opp.h | 6 ++
2 files changed, 44 insertions(+
From: Yangtao Li
Add devres wrapper for dev_pm_opp_set_supported_hw() to simplify driver
code.
Signed-off-by: Yangtao Li
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 38 ++
include/linux/pm_opp.h | 8
2 files changed, 46 insertions(
From: Yangtao Li
Add devres wrapper for dev_pm_opp_of_add_table() to simplify driver
code.
Signed-off-by: Yangtao Li
Signed-off-by: Dmitry Osipenko
---
drivers/opp/of.c | 36
include/linux/pm_opp.h | 6 ++
2 files changed, 42 insertions(+)
diff
From: Yangtao Li
Add devres wrapper for dev_pm_opp_set_regulators() to simplify drivers
code.
Signed-off-by: Yangtao Li
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 39 +++
include/linux/pm_opp.h | 8
2 files changed, 47 insertions(
From: Yangtao Li
Add devres wrapper for dev_pm_opp_set_clkname() to simplify drivers code.
Signed-off-by: Yangtao Li
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 36
include/linux/pm_opp.h | 6 ++
2 files changed, 42 insertions(+)
diff
This series adds resource-managed OPP API helpers and makes drivers
to use them.
Changelog:
v2: - This is a continuation of the work that was started by Yangtao Li.
Apparently Yangtao doesn't have time to finish it, so I
(Dmitry Osipenko) picked up the effort since these patches are
On Thu, 11 Mar 2021 at 08:04, Keith Packard wrote:
>
> Jason Ekstrand writes:
>
> > libdrm has supported the newer execbuffer2 ioctl and using it by default
> > when it exists since libdrm commit b50964027bef249a0cc3d511de05c2464e0a1e22
> > which landed Mar 2, 2010. The i915 and i965 drivers in
On Thu, Mar 11, 2021 at 12:20 PM Zbigniew Kempczyński
wrote:
>
> On Thu, Mar 11, 2021 at 11:18:11AM -0600, Jason Ekstrand wrote:
> > On Thu, Mar 11, 2021 at 10:51 AM Zbigniew Kempczyński
> > wrote:
> > >
> > > On Thu, Mar 11, 2021 at 10:24:38AM -0600, Jason Ekstrand wrote:
> > > > On Thu, Mar 11,
On Thu, Mar 11, 2021 at 11:18:11AM -0600, Jason Ekstrand wrote:
> On Thu, Mar 11, 2021 at 10:51 AM Zbigniew Kempczyński
> wrote:
> >
> > On Thu, Mar 11, 2021 at 10:24:38AM -0600, Jason Ekstrand wrote:
> > > On Thu, Mar 11, 2021 at 9:57 AM Daniel Vetter wrote:
> > > >
> > > > On Thu, Mar 11, 2021
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Rajneesh Bhardwaj
-Original Message-
From: amd-gfx On Behalf Of Oak Zeng
Sent: Wednesday, March 10, 2021 10:29 PM
To: dri-devel@lists.freedesktop.org; amd-...@lists.freedesktop.org
Cc: Zeng, Oak
Subject: [PATCH 2/2] drm/
On Thu, Mar 11, 2021 at 11:25 AM Boris Brezillon
wrote:
>
> Hi Jason,
>
> On Thu, 11 Mar 2021 10:58:46 -0600
> Jason Ekstrand wrote:
>
> > Hi all,
> >
> > Dropping in where I may or may not be wanted to feel free to ignore. : -)
>
> I'm glad you decided to chime in. :-)
>
>
> > > > > 2/ Queued jo
Hi Jason,
On Thu, 11 Mar 2021 10:58:46 -0600
Jason Ekstrand wrote:
> Hi all,
>
> Dropping in where I may or may not be wanted to feel free to ignore. : -)
I'm glad you decided to chime in. :-)
> > > > 2/ Queued jobs might be executed out-of-order (unless they have
> > > > explicit/impli
Display controller (DC) performs isochronous memory transfers, and thus,
has a requirement for a minimum memory bandwidth that shall be fulfilled,
otherwise framebuffer data can't be fetched fast enough and this results
in a DC's data-FIFO underflow that follows by a visual corruption.
The Memory
It's useful to know the total number of underflow events and currently
the debug stats are getting reset each time CRTC is being disabled. Let's
account the overall number of events that doesn't get a reset.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
dr
This series adds memory bandwidth management to the NVIDIA Tegra DRM driver,
which is done using interconnect framework. It fixes display corruption that
happens due to insufficient memory bandwidth.
Changelog:
v15: - Corrected tegra_plane_icc_names[] NULL-check that was partially lost
by
On Thu, Mar 11, 2021 at 10:51 AM Zbigniew Kempczyński
wrote:
>
> On Thu, Mar 11, 2021 at 10:24:38AM -0600, Jason Ekstrand wrote:
> > On Thu, Mar 11, 2021 at 9:57 AM Daniel Vetter wrote:
> > >
> > > On Thu, Mar 11, 2021 at 4:50 PM Jason Ekstrand
> > > wrote:
> > > >
> > > > On Thu, Mar 11, 2021
Den 11.03.2021 15.48, skrev Peter Stuge:
> Noralf Trønnes wrote:
>>> I didn't receive the expected bits/bytes for RGB111 on the bulk endpoint,
>>> I think because of how components were extracted in gud_xrgb_to_color().
>>>
>>> Changing to the following gets me the expected (X R1 G1 B1 X R2 G
11.03.2021 20:06, Dmitry Osipenko пишет:
> +static const char * const tegra_plane_icc_names[TEGRA_DC_LEGACY_PLANES_NUM]
> = {
> + "wina", "winb", "winc", "", "", "", "cursor",
> +};
> +
> +int tegra_plane_interconnect_init(struct tegra_plane *plane)
> +{
> + const char *icc_name = tegra_pl
11.03.2021 20:06, Dmitry Osipenko пишет:
> This series adds memory bandwidth management to the NVIDIA Tegra DRM driver,
> which is done using interconnect framework. It fixes display corruption that
> happens due to insufficient memory bandwidth.
>
> Changelog:
>
> v14: - Made improvements that w
Display controller (DC) performs isochronous memory transfers, and thus,
has a requirement for a minimum memory bandwidth that shall be fulfilled,
otherwise framebuffer data can't be fetched fast enough and this results
in a DC's data-FIFO underflow that follows by a visual corruption.
The Memory
It's useful to know the total number of underflow events and currently
the debug stats are getting reset each time CRTC is being disabled. Let's
account the overall number of events that doesn't get a reset.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
dr
This series adds memory bandwidth management to the NVIDIA Tegra DRM driver,
which is done using interconnect framework. It fixes display corruption that
happens due to insufficient memory bandwidth.
Changelog:
v14: - Made improvements that were suggested by Michał Mirosław to v13:
- Chan
Hi all,
Dropping in where I may or may not be wanted to feel free to ignore. : -)
On Thu, Mar 11, 2021 at 7:00 AM Boris Brezillon
wrote:
>
> Hi Steven,
>
> On Thu, 11 Mar 2021 12:16:33 +
> Steven Price wrote:
>
> > On 11/03/2021 09:25, Boris Brezillon wrote:
> > > Hello,
> > >
> > > I've be
On Thu, Mar 11, 2021 at 10:24:38AM -0600, Jason Ekstrand wrote:
> On Thu, Mar 11, 2021 at 9:57 AM Daniel Vetter wrote:
> >
> > On Thu, Mar 11, 2021 at 4:50 PM Jason Ekstrand wrote:
> > >
> > > On Thu, Mar 11, 2021 at 5:44 AM Zbigniew Kempczyński
> > > wrote:
> > > >
> > > > On Wed, Mar 10, 2021
On Thu, Mar 11, 2021 at 10:31 AM Chris Wilson wrote:
>
> Quoting Zbigniew Kempczyński (2021-03-11 11:44:32)
> > On Wed, Mar 10, 2021 at 03:50:07PM -0600, Jason Ekstrand wrote:
> > > The Vulkan driver in Mesa for Intel hardware never uses relocations if
> > > it's running on a version of i915 that
On Wed, 10 Mar 2021 22:08:35 +0800, Carlis wrote:
> From: "Carlis"
>
> Document support for the Waveshare 2inch LCD module display, which is a
> 240x320 2" TFT display driven by a Sitronix ST7789V TFT Controller.
>
> Signed-off-by: Carlis
> ---
> .../bindings/display/sitronix,st7789v.yaml
From: Colin Ian King
The variable result is being initialized with a value that is
never read and it is being updated later with a new value. The
initialization is redundant and can be removed.
Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/amd/display/
Quoting Zbigniew Kempczyński (2021-03-11 11:44:32)
> On Wed, Mar 10, 2021 at 03:50:07PM -0600, Jason Ekstrand wrote:
> > The Vulkan driver in Mesa for Intel hardware never uses relocations if
> > it's running on a version of i915 that supports at least softpin which
> > all versions of i915 support
Hi Wang,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v5.12-rc2 next-20210311]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--bas
The Vulkan driver in Mesa for Intel hardware never uses relocations if
it's running on a version of i915 that supports at least softpin which
all versions of i915 supporting Gen12 do. On the OpenGL side, Gen12+ is
only supported by iris which never uses relocations. The older i965
driver in Mesa
On Thu, Mar 11, 2021 at 9:57 AM Daniel Vetter wrote:
>
> On Thu, Mar 11, 2021 at 4:50 PM Jason Ekstrand wrote:
> >
> > On Thu, Mar 11, 2021 at 5:44 AM Zbigniew Kempczyński
> > wrote:
> > >
> > > On Wed, Mar 10, 2021 at 03:50:07PM -0600, Jason Ekstrand wrote:
> > > > The Vulkan driver in Mesa for
On Thu, Mar 11, 2021 at 2:01 AM Doug Anderson wrote:
> If you happen to feel in an applying mood one other patch to
> simple-panel I think is OK to land is at:
>
> https://lore.kernel.org/r/20210222081716.1.I1a45aece5d2ac6a2e73bbec50da2086e43e0862b@changeid
I applied and pushed this as well.
Yo
Quoting Daniel Vetter (2021-03-11 16:01:46)
> On Fri, Mar 05, 2021 at 11:05:46AM -0600, Jason Ekstrand wrote:
> > This reverts commit 9e31c1fe45d555a948ff66f1f0e3fe1f83ca63f7. Ever
> > since that commit, we've been having issues where a hang in one client
> > can propagate to another. In particul
On Fri, Jan 15, 2021 at 11:44 PM Douglas Anderson wrote:
> This series is to get the N116BCA-EA1 panel working. Most of the
> patches are simple, but on hardware I have in front of me the panel
> sometimes doesn't come up. I'm still working with the hardware
> manufacturer to get to the bottom of
On Thu, Mar 11, 2021 at 10:02 AM Alexandre Desnoyers wrote:
>
> On Thu, Mar 11, 2021 at 2:49 PM Daniel Gomez wrote:
> >
> > On Thu, 11 Mar 2021 at 10:09, Daniel Gomez wrote:
> > >
> > > On Wed, 10 Mar 2021 at 18:06, Alex Deucher wrote:
> > > >
> > > > On Wed, Mar 10, 2021 at 11:37 AM Daniel Gom
On Fri, Mar 05, 2021 at 11:05:46AM -0600, Jason Ekstrand wrote:
> This reverts commit 9e31c1fe45d555a948ff66f1f0e3fe1f83ca63f7. Ever
> since that commit, we've been having issues where a hang in one client
> can propagate to another. In particular, a hang in an app can propagate
> to the X server
On Thu, Mar 11, 2021 at 4:50 PM Jason Ekstrand wrote:
>
> On Thu, Mar 11, 2021 at 5:44 AM Zbigniew Kempczyński
> wrote:
> >
> > On Wed, Mar 10, 2021 at 03:50:07PM -0600, Jason Ekstrand wrote:
> > > The Vulkan driver in Mesa for Intel hardware never uses relocations if
> > > it's running on a vers
On Thu, Mar 11, 2021 at 5:44 AM Zbigniew Kempczyński
wrote:
>
> On Wed, Mar 10, 2021 at 03:50:07PM -0600, Jason Ekstrand wrote:
> > The Vulkan driver in Mesa for Intel hardware never uses relocations if
> > it's running on a version of i915 that supports at least softpin which
> > all versions of
Applied. Thanks!
Alex
On Tue, Feb 9, 2021 at 7:50 AM Christian König wrote:
>
> Reviewed-by: Christian König for the series.
>
> Am 09.02.21 um 13:44 schrieb Sebastian Andrzej Siewior:
> > Folks,
> >
> > in the discussion about preempt count consistency across kernel
> > configurations:
> >
>
Applied. Thanks!
Alex
On Thu, Mar 11, 2021 at 4:28 AM Colin King wrote:
>
> From: Colin Ian King
>
> There is a spelling mistake in a drm debug message. Fix it.
>
> Signed-off-by: Colin Ian King
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
> 1 file changed, 1 insertion(+), 1 de
On 3/11/21 2:17 PM, Daniel Vetter wrote:
On Thu, Mar 11, 2021 at 2:12 PM Thomas Hellström (Intel)
wrote:
Hi!
On 3/11/21 2:00 PM, Daniel Vetter wrote:
On Thu, Mar 11, 2021 at 11:22:06AM +0100, Thomas Hellström (Intel) wrote:
On 3/1/21 3:09 PM, Daniel Vetter wrote:
On Mon, Mar 1, 2021 at 11:
On Wed, Mar 10, 2021 at 04:47:57PM -0500, Sean Paul wrote:
> From: Sean Paul
>
> One instance of DRM_DEBUG_KMS was leftover in dp_link_training, convert
> it to the new shiny.
>
> Signed-off-by: Sean Paul
> ---
> .../gpu/drm/i915/display/intel_dp_link_training.c | 15 ---
> 1 file
On Wed, Mar 10, 2021 at 04:47:56PM -0500, Sean Paul wrote:
> From: Sean Paul
>
> This patch adds some newlines which are missing from debug messages.
> This will prevent logs from being stacked up in dmesg.
>
> Signed-off-by: Sean Paul
> ---
> drivers/gpu/drm/i915/display/intel_dp_link_trainin
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Noralf Trønnes wrote:
> > I didn't receive the expected bits/bytes for RGB111 on the bulk endpoint,
> > I think because of how components were extracted in gud_xrgb_to_color().
> >
> > Changing to the following gets me the expected (X R1 G1 B1 X R2 G2 B2)
> > bytes:
> >
> >
On Fri, Mar 05, 2021 at 11:54:49AM +0100, Christian König wrote:
> Am 05.03.21 um 11:51 schrieb Chris Wilson:
> > Commit c545781e1c55 ("dma-buf: doc polish for pin/unpin") disagrees with
> > the introduction of dynamism in commit: bb42df4662a4 ("dma-buf: add
> > dynamic DMA-buf handling v15") resul
On Fri, Mar 05, 2021 at 05:44:04PM +0200, Pekka Paalanen wrote:
> On Thu, 4 Mar 2021 09:43:22 +0530
> Hardik Panchal wrote:
>
> > Hello Sir/Madam,
> >
> > I am trying to render some stuff using DRM with Qt GUI application and
> > decoded stream from Intel H/w decoder.
> >
> > I have two applica
https://bugzilla.kernel.org/show_bug.cgi?id=211277
--- Comment #15 from kolAflash (kolafl...@kolahilft.de) ---
(In reply to Alex Deucher from comment #10)
> Can you bisect?
> https://www.kernel.org/doc/html/latest/admin-guide/bug-bisect.html
I've done several s2ram-wakeup cycles (100 automatic a
On Thu, 11 Mar 2021, Daniel Vetter wrote:
> On Mon, Mar 08, 2021 at 09:19:32AM +, Lee Jones wrote:
> > On Fri, 05 Mar 2021, Roland Scheidegger wrote:
> >
> > > The vmwgfx ones look all good to me, so for
> > > 23-53: Reviewed-by: Roland Scheidegger
> > > That said, they were already signed o
On Thu, 11 Mar 2021 at 10:09, Daniel Gomez wrote:
>
> On Wed, 10 Mar 2021 at 18:06, Alex Deucher wrote:
> >
> > On Wed, Mar 10, 2021 at 11:37 AM Daniel Gomez wrote:
> > >
> > > Disabling GFXOFF via the quirk list fixes a hardware lockup in
> > > Ryzen V1605B, RAVEN 0x1002:0x15DD rev 0x83.
> > >
On Mon, Mar 08, 2021 at 09:19:32AM +, Lee Jones wrote:
> On Fri, 05 Mar 2021, Roland Scheidegger wrote:
>
> > The vmwgfx ones look all good to me, so for
> > 23-53: Reviewed-by: Roland Scheidegger
> > That said, they were already signed off by Zack, so not sure what
> > happened here.
>
> Ye
On Thu, Mar 11, 2021 at 02:13:57PM +0100, Hans de Goede wrote:
> Hi,
>
> On 3/11/21 2:11 PM, Daniel Vetter wrote:
> > On Wed, Mar 03, 2021 at 09:39:46AM +0800, Tian Tao wrote:
> >> updated to use drmm_vram_helper_init().
> >>
> >> Signed-off-by: Tian Tao
> >
> > Hans, do you plan to pick this up
On Thu, Mar 11, 2021 at 2:12 PM Thomas Hellström (Intel)
wrote:
>
> Hi!
>
> On 3/11/21 2:00 PM, Daniel Vetter wrote:
> > On Thu, Mar 11, 2021 at 11:22:06AM +0100, Thomas Hellström (Intel) wrote:
> >> On 3/1/21 3:09 PM, Daniel Vetter wrote:
> >>> On Mon, Mar 1, 2021 at 11:17 AM Christian König
> >>
Hi,
On 3/11/21 2:11 PM, Daniel Vetter wrote:
> On Wed, Mar 03, 2021 at 09:39:46AM +0800, Tian Tao wrote:
>> updated to use drmm_vram_helper_init().
>>
>> Signed-off-by: Tian Tao
>
> Hans, do you plan to pick this up?
The drm patch-workflow falls outside my daily kernel-work workflow,
so it is a
Hi!
On 3/11/21 2:00 PM, Daniel Vetter wrote:
On Thu, Mar 11, 2021 at 11:22:06AM +0100, Thomas Hellström (Intel) wrote:
On 3/1/21 3:09 PM, Daniel Vetter wrote:
On Mon, Mar 1, 2021 at 11:17 AM Christian König
wrote:
Am 01.03.21 um 10:21 schrieb Thomas Hellström (Intel):
On 3/1/21 10:05 AM, D
On Wed, Mar 03, 2021 at 09:39:46AM +0800, Tian Tao wrote:
> updated to use drmm_vram_helper_init().
>
> Signed-off-by: Tian Tao
Hans, do you plan to pick this up?
-Daniel
> ---
> drivers/gpu/drm/vboxvideo/vbox_ttm.c | 7 ++-
> 1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git
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