On 11.06.2021 02:05, Matthew Brost wrote:
> In upcoming patch we will allow more CTB requests to be sent in
> parallel to the GuC for processing, so we shouldn't assume any more
> that GuC will always reply without 10ms.
s/without/within
>
> Use bigger value hardcoded value of 1s instead.
>
Am 10.06.21 um 22:42 schrieb Daniel Vetter:
On Thu, Jun 10, 2021 at 10:10 PM Jason Ekstrand wrote:
On Thu, Jun 10, 2021 at 8:35 AM Jason Ekstrand wrote:
On Thu, Jun 10, 2021 at 6:30 AM Daniel Vetter wrote:
On Thu, Jun 10, 2021 at 11:39 AM Christian König
wrote:
Am 10.06.21 um 11:29 schrie
On 11/06/2021 08:54, Maxime Ripard wrote:
Hi,
On Thu, Jun 10, 2021 at 11:00:05PM +0200, Daniel Vetter wrote:
On Thu, Jun 10, 2021 at 7:47 PM Maxime Ripard wrote:
New KMS properties come with a bunch of requirements to avoid each
driver from running their own, inconsistent, set of properties,
Hi
Am 10.06.21 um 15:32 schrieb Daniel Vetter:
On Thu, Jun 10, 2021 at 1:15 PM Thomas Zimmermann wrote:
Hi Dave and Daniel,
here's the second PR for drm-misc-next for this week, and the final one
for 5.14. I backmerged drm-next for the TTM changes. As for highlights
nouveau now has eDP backl
We have established previously we stop using relocations starting
from gen12 platforms with Tigerlake as an exception. We keep this
statement but we want to enable relocations conditionally for
Alderlake S+P under require_force_probe flag set.
Keeping relocations under require_force_probe flag is
On Thu, Jun 10, 2021 at 10:36:12AM -0400, Rodrigo Vivi wrote:
> On Thu, Jun 10, 2021 at 12:39:55PM +0200, Zbigniew Kempczyński wrote:
> > We have established previously we stop using relocations starting
> > from gen12 platforms with Tigerlake as an exception. We keep this
> > statement but we want
From: Chris Wilson
Due to a change in requirements that disallows tasklet_disable() being
called from atomic context, rearrange the selftest to avoid doing so.
<3> [324.942939] BUG: sleeping function called from invalid context at
kernel/softirq.c:888
<3> [324.942952] in_atomic(): 1, irqs_disab
On 10/06/2021 23:46, john.c.harri...@intel.com wrote:
From: John Harrison
Various UMDs need to know the L3 bank count. So add a query API for it.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_gt.c | 15 +++
drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
drivers/gp
Hi,
On Thu, Jun 10, 2021 at 11:00:05PM +0200, Daniel Vetter wrote:
> On Thu, Jun 10, 2021 at 7:47 PM Maxime Ripard wrote:
> >
> > New KMS properties come with a bunch of requirements to avoid each
> > driver from running their own, inconsistent, set of properties,
> > eventually leading to issues
Hi, Christian,
I know you have a lot on your plate, and that the drm community is a bit
lax about following the kernel patch submitting guidelines, but now that
we're also spinning up a number of Intel developers on TTM could we
please make a better effort with cover letters and commit message
On 6/10/21 2:48 AM, Stephen Rothwell wrote:
Hi all,
Changes since 20210609:
on x86_64:
../drivers/gpu/drm/nouveau/dispnv50/disp.c: In function
‘nv50_sor_atomic_disable’:
../drivers/gpu/drm/nouveau/dispnv50/disp.c:1665:52: error: ‘struct
nouveau_connector’ has no member named ‘backlight’
On Friday, 11 June 2021 11:00:34 AM AEST Peter Xu wrote:
> On Fri, Jun 11, 2021 at 09:17:14AM +1000, Alistair Popple wrote:
> > On Friday, 11 June 2021 9:04:19 AM AEST Peter Xu wrote:
> > > On Fri, Jun 11, 2021 at 12:21:26AM +1000, Alistair Popple wrote:
> > > > > Hmm, the thing is.. to me FOLL_SPL
Hey Linus,
Another week of fixes, nothing too crazy, but a few all over the
place, two locking fixes in the core/ttm area, a couple of small
driver fixes (radeon, sun4i, mcde, vc4). Then msm and amdgpu have a
set of fixes each, mostly for smaller things, though the msm has a DSI
fix for a black sc
On 11/6/21 1:49 am, Emil Velikov wrote:
On Thu, 10 Jun 2021 at 11:10, Daniel Vetter wrote:
On Wed, Jun 09, 2021 at 05:21:19PM +0800, Desmond Cheong Zhi Xi wrote:
This patch eliminates the following smatch warning:
drivers/gpu/drm/drm_auth.c:320 drm_master_release() warn: unlocked access 'mast
Hi Dave,
Just two cleanups to replace pm_runtime_get_sync() with
pm_runtime_resume_and_get().
Please kinkdly let me know if there is any problem.
Thanks,
Inki Dae
The following changes since commit c707b73f0cfb1acc94a20389aecde65e6385349b:
Merge tag 'amd-drm-next-5.14-2021-06-09' of
On 11/6/21 12:48 am, Daniel Vetter wrote:
On Thu, Jun 10, 2021 at 11:21:39PM +0800, Desmond Cheong Zhi Xi wrote:
On 10/6/21 6:10 pm, Daniel Vetter wrote:
On Wed, Jun 09, 2021 at 05:21:19PM +0800, Desmond Cheong Zhi Xi wrote:
This patch eliminates the following smatch warning:
drivers/gpu/drm/d
On Fri, Jun 11, 2021 at 09:17:14AM +1000, Alistair Popple wrote:
> On Friday, 11 June 2021 9:04:19 AM AEST Peter Xu wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > On Fri, Jun 11, 2021 at 12:21:26AM +1000, Alistair Popple wrote:
> > > > Hmm, the thing is.. to me FO
A previous version of patch [1] was NACK'd because it introduced a
Kconfig option. We agreed on a larger timeout value if problems were
shown with the current timeout value. A problem was shown in CI [2],
let's increase the timeout.
[1] https://patchwork.freedesktop.org/patch/436623/
[2]
https://
In upcoming patch we will allow more CTB requests to be sent in
parallel to the GuC for processing, so we shouldn't assume any more
that GuC will always reply without 10ms.
Use bigger value hardcoded value of 1s instead.
v2: Add CONFIG_DRM_I915_GUC_CTB_TIMEOUT config option
v3:
(Daniel Vetter)
A fence will be added to resource_flush for resources that
are guest blobs.
Cc: Gerd Hoffmann
Signed-off-by: Vivek Kasireddy
---
drivers/gpu/drm/virtio/virtgpu_drv.h | 4 +++-
drivers/gpu/drm/virtio/virtgpu_vq.c | 7 +--
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/driver
If the framebuffer associated with the plane contains a fence, then
it is added to resource_flush and will be waited upon for a max of
50 msecs or until it is signalled by the Host.
Cc: Gerd Hoffmann
Signed-off-by: Vivek Kasireddy
---
drivers/gpu/drm/virtio/virtgpu_plane.c | 45
Add prepare and cleanup routines for primary planes as well
where a fence is added only if the BO/FB associated with the
plane is a guest blob.
Cc: Gerd Hoffmann
Signed-off-by: Vivek Kasireddy
---
drivers/gpu/drm/virtio/virtgpu_plane.c | 19 ---
1 file changed, 12 insertions(+),
This 3 patch series is the counterpart for this other series:
https://lists.nongnu.org/archive/html/qemu-devel/2021-06/msg02906.html
It makes it possible for the Guest to wait until the Host has
completely consumed its FB before reusing it again thereby ensuring
that both the parties don't access
On Friday, 11 June 2021 9:04:19 AM AEST Peter Xu wrote:
> External email: Use caution opening links or attachments
>
>
> On Fri, Jun 11, 2021 at 12:21:26AM +1000, Alistair Popple wrote:
> > > Hmm, the thing is.. to me FOLL_SPLIT_PMD should have similar effect to
> > > explicit
> > > call split_h
Hi,
On Thu, Jun 10, 2021 at 4:01 PM Linus Walleij wrote:
>
> On Fri, Jun 11, 2021 at 12:42 AM Doug Anderson wrote:
> > On Thu, Jun 10, 2021 at 3:39 PM Linus Walleij
> > wrote:
>
>
> > > #define mipi_dbi_command(dbi, cmd, seq...) \
> > > ({ \
> > > const u8 d[] = { seq }; \
> > >
On Fri, Jun 11, 2021 at 12:21:26AM +1000, Alistair Popple wrote:
> > Hmm, the thing is.. to me FOLL_SPLIT_PMD should have similar effect to
> > explicit
> > call split_huge_pmd_address(), afaict. Since both of them use
> > __split_huge_pmd()
> > internally which will generate that unwanted CLEAR
On 10.06.2021 22:46, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Various UMDs need to know the L3 bank count. So add a query API for it.
>
> Signed-off-by: John Harrison
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 15 +++
> drivers/gpu/drm/i915/gt/intel_gt.h | 1
On Fri, Jun 11, 2021 at 12:42 AM Doug Anderson wrote:
> On Thu, Jun 10, 2021 at 3:39 PM Linus Walleij
> wrote:
> > #define mipi_dbi_command(dbi, cmd, seq...) \
> > ({ \
> > const u8 d[] = { seq }; \
> > mipi_dbi_command_stackbuf(dbi, cmd, d, ARRAY_SIZE(d)); \
> > })
> >
> > I'l
On 6/2/2021 9:20 AM, Rodrigo Vivi wrote:
On Mon, May 24, 2021 at 10:47:59PM -0700, Daniele Ceraolo Spurio wrote:
From: "Huang, Sean Z"
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
session state might still be
On 10.06.2021 22:46, john.c.harri...@intel.com wrote:
> From: Rodrigo Vivi
>
> GuC contains a consolidated table with a bunch of information about the
> current device.
>
> Previously, this information was spread and hardcoded to all the components
> including GuC, i915 and various UMDs. The
On 6/2/2021 11:14 AM, Rodrigo Vivi wrote:
On Mon, May 24, 2021 at 10:47:58PM -0700, Daniele Ceraolo Spurio wrote:
Now that we can handle destruction and re-creation of the arb session,
we can postpone the start of the session to the first submission that
requires it, to avoid keeping it runni
On Friday, 11 June 2021 4:04:35 AM AEST Peter Xu wrote:
> External email: Use caution opening links or attachments
>
>
> On Thu, Jun 10, 2021 at 10:18:25AM +1000, Alistair Popple wrote:
> > > > The main problem is split_huge_pmd_address() unconditionally calls a mmu
> > > > notifier so I would ne
Hi,
On Thu, Jun 10, 2021 at 3:39 PM Linus Walleij wrote:
>
> On Fri, Jun 11, 2021 at 12:30 AM Doug Anderson wrote:
>
> > > + mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, 0x0a);
> >
> > I would still prefer it if there was some type of error checking since
> > SPI commands can fail and
On Fri, Jun 11, 2021 at 12:30 AM Doug Anderson wrote:
> > + mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, 0x0a);
>
> I would still prefer it if there was some type of error checking since
> SPI commands can fail and could potentially fail silently. What about
> at least this (untested):
On 10.06.2021 22:46, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Implement support for fetching the hardware description table from the
> GuC. The call is made twice - once without a destination buffer to
> query the size and then a second time to fill in the buffer.
>
> This p
Hi,
On Thu, Jun 10, 2021 at 3:07 PM Linus Walleij wrote:
>
> @@ -0,0 +1,347 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Panel driver for the Samsung LMS397KF04 480x800 DPI RGB panel.
> + * According to the data sheet the display controller is called DB7430.
> + * Found in the Samsung Ga
On Thu, Jun 10, 2021 at 01:46:26PM -0700, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Various UMDs need to know the L3 bank count. So add a query API for it.
>
> Signed-off-by: John Harrison
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 15 +++
> drivers/gpu/drm/i915/
This adds a new driver for the Samsung DB7430 DPI display
controller as controlled over SPI.
Right now the only panel product we know that is using this
display controller is the LMS397KF04 but there may be more.
This is the first regular panel driver making use of the
MIPI DBI helper library. Th
Hi Noralf,
thanks for the review. Doug poked me with something sharp
until I finally complied and started to use the DBI library.
Now I have to convert the other 9bpw DBI type displays
I have.
On Thu, Jun 10, 2021 at 6:15 PM Noralf Trønnes wrote:
> > + /** @reset: reset GPIO line */
> > +
On Thu, Jun 10, 2021 at 01:46:25PM -0700, john.c.harri...@intel.com wrote:
> From: Rodrigo Vivi
>
> GuC contains a consolidated table with a bunch of information about the
> current device.
>
> Previously, this information was spread and hardcoded to all the components
> including GuC, i915 and
Render clients should be able to create/destroy dumb object to import
and use it as render buffer in case the default DRM device is different
from the render device (i.e. kmsro).
Signed-off-by: Dongwon Kim
---
drivers/gpu/drm/drm_ioctl.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
On Thu, Jun 10, 2021 at 01:46:24PM -0700, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Implement support for fetching the hardware description table from the
> GuC. The call is made twice - once without a destination buffer to
> query the size and then a second time to fill in the b
From: Rob Clark
Wire up support to stall the SMMU on iova fault, and collect a devcore-
dump snapshot for easier debugging of faults.
Currently this is a6xx-only, but mostly only because so far it is the
only one using adreno-smmu-priv.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/
From: Rob Clark
Add, via the adreno-smmu-priv interface, a way for the GPU to request
the SMMU to stall translation on faults, and then later resume the
translation, either retrying or terminating the current translation.
This will be used on the GPU side to "freeze" the GPU while we snapshot
us
From: Jordan Crouse
Use the new adreno-smmu-priv fault info function to get more SMMU
debug registers and print the current TTBR0 to debug per-instance
pagetables and figure out which GPU block generated the request.
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
---
drivers/gpu/drm/ms
From: Jordan Crouse
Add a callback in adreno-smmu-priv to read interesting SMMU
registers to provide an opportunity for a richer debug experience
in the GPU driver.
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 17
drivers/
From: Jordan Crouse
Call report_iommu_fault() to allow upper-level drivers to register their
own fault handlers.
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
Acked-by: Will Deacon
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-
From: Rob Clark
This picks up an earlier series[1] from Jordan, and adds additional
support needed to generate GPU devcore dumps on iova faults. Original
description:
This is a stack to add an Adreno GPU specific handler for pagefaults. The first
patch starts by wiring up report_iommu_fault for
This adds a new "DMA Buffer ioctls" section to the dma-buf docs and adds
documentation for DMA_BUF_IOCTL_SYNC.
v2 (Daniel Vetter):
- Fix a couple typos
- Add commentary about synchronization with other devices
- Use item list format for describing flags
Signed-off-by: Jason Ekstrand
Reviewed-
On 2021-06-07 10:53 a.m., Mark Yacoub wrote:
> On Fri, Jun 4, 2021 at 4:17 PM Harry Wentland wrote:
>>
>>
>>
>> On 2021-06-04 1:01 p.m., Mark Yacoub wrote:
>>> From: Mark Yacoub
>>>
>>> For each CRTC state, check the size of Gamma and Degamma LUTs so
>>> unexpected and larger sizes wouldn't s
For dma-buf sync_file import, we want to get all the fences on a
dma_resv plus one more. We could wrap the fence we get back in an array
fence or we could make dma_resv_get_singleton_unlocked take "one more"
to make this case easier.
Signed-off-by: Jason Ekstrand
Reviewed-by: Daniel Vetter
Cc:
This patch is analogous to the previous sync file export patch in that
it allows you to import a sync_file into a dma-buf. Unlike the previous
patch, however, this does add genuinely new functionality to dma-buf.
Without this, the only way to attach a sync_file to a dma-buf is to
submit a batch to
Modern userspace APIs like Vulkan are built on an explicit
synchronization model. This doesn't always play nicely with the
implicit synchronization used in the kernel and assumed by X11 and
Wayland. The client -> compositor half of the synchronization isn't too
bad, at least on intel, because we
This adds a new "DMA Buffer ioctls" section to the dma-buf docs and adds
documentation for DMA_BUF_IOCTL_SYNC.
v2 (Daniel Vetter):
- Fix a couple typos
- Add commentary about synchronization with other devices
- Use item list format for describing flags
Signed-off-by: Jason Ekstrand
Cc: Danie
Add a helper function to get a single fence representing
all fences in a dma_resv object.
This fence is either the only one in the object or all not
signaled fences of the object in a flatted out dma_fence_array.
v2 (Jason Ekstrand):
- Take reference of fences both for creating the dma_fence_arr
From: Christian König
Add a helper to iterate over all fences in a dma_fence_array object.
v2 (Jason Ekstrand)
- Return NULL from dma_fence_array_first if head == NULL. This matches
the iterator behavior of dma_fence_chain_for_each in that it iterates
zero times if head == NULL.
- Retur
Modern userspace APIs like Vulkan are built on an explicit
synchronization model. This doesn't always play nicely with the
implicit synchronization used in the kernel and assumed by X11 and
Wayland. The client -> compositor half of the synchronization isn't too
bad, at least on intel, because we
On Thu, Jun 10, 2021 at 7:47 PM Maxime Ripard wrote:
>
> New KMS properties come with a bunch of requirements to avoid each
> driver from running their own, inconsistent, set of properties,
> eventually leading to issues like property conflicts, inconsistencies
> between drivers and semantics, etc
On Thu, May 27, 2021 at 5:38 AM Daniel Vetter wrote:
>
> On Tue, May 25, 2021 at 04:17:50PM -0500, Jason Ekstrand wrote:
> > This adds a new "DMA Buffer ioctls" section to the dma-buf docs and adds
> > documentation for DMA_BUF_IOCTL_SYNC.
> >
> > Signed-off-by: Jason Ekstrand
> > Cc: Daniel Vett
From: John Harrison
Various UMDs need to know the L3 bank count. So add a query API for it.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_gt.c | 15 +++
drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
drivers/gpu/drm/i915/i915_query.c | 22 ++
drive
From: Rodrigo Vivi
GuC contains a consolidated table with a bunch of information about the
current device.
Previously, this information was spread and hardcoded to all the components
including GuC, i915 and various UMDs. The goal here is to consolidate
the data into GuC in a way that all interes
From: John Harrison
Implement support for fetching the hardware description table from the
GuC. The call is made twice - once without a destination buffer to
query the size and then a second time to fill in the buffer.
This patch also adds a header file which lists all the attribute values
curre
From: John Harrison
Various UMDs require hardware configuration information about the
current platform. A bunch of static information is available in a
fixed table that can be retrieved from the GuC. Further information
can be calculated dynamically from fuse registers.
Signed-off-by: John Harri
On Thu, Jun 10, 2021 at 10:10 PM Jason Ekstrand wrote:
>
> On Thu, Jun 10, 2021 at 8:35 AM Jason Ekstrand wrote:
> > On Thu, Jun 10, 2021 at 6:30 AM Daniel Vetter
> > wrote:
> > > On Thu, Jun 10, 2021 at 11:39 AM Christian König
> > > wrote:
> > > > Am 10.06.21 um 11:29 schrieb Tvrtko Ursulin:
Add a small description and document struct fields of
drm_mode_get_plane.
Signed-off-by: Leandro Ribeiro
---
include/uapi/drm/drm_mode.h | 35 +++
1 file changed, 35 insertions(+)
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 9b6722
v2: possible_crtcs field is a bitmask, not a pointer. Suggested by
Ville Syrjälä
v3: document how userspace should find out CRTC index. Also,
document that field 'gamma_size' represents the number of
entries in the lookup table. Suggested by Pekka Paalanen
and Daniel Vetter
v4: document IN and
On Thu, Jun 10, 2021 at 3:11 PM Chia-I Wu wrote:
>
> On Tue, May 25, 2021 at 2:18 PM Jason Ekstrand wrote:
> > Modern userspace APIs like Vulkan are built on an explicit
> > synchronization model. This doesn't always play nicely with the
> > implicit synchronization used in the kernel and assume
On Tue, May 25, 2021 at 2:18 PM Jason Ekstrand wrote:
> Modern userspace APIs like Vulkan are built on an explicit
> synchronization model. This doesn't always play nicely with the
> implicit synchronization used in the kernel and assumed by X11 and
> Wayland. The client -> compositor half of th
On Thu, Jun 10, 2021 at 8:35 AM Jason Ekstrand wrote:
> On Thu, Jun 10, 2021 at 6:30 AM Daniel Vetter wrote:
> > On Thu, Jun 10, 2021 at 11:39 AM Christian König
> > wrote:
> > > Am 10.06.21 um 11:29 schrieb Tvrtko Ursulin:
> > > > On 09/06/2021 22:29, Jason Ekstrand wrote:
> > > >>
> > > >> We'
https://bugzilla.kernel.org/show_bug.cgi?id=213391
--- Comment #8 from Lahfa Samy (s...@lahfa.xyz) ---
In the meantime, I'll be trying to find a way to reproduce this issue reliably,
if you have any plans on writing a patch for this issue, I would be glad to
help in any testing in order to help sq
On Thu, Jun 10, 2021 at 07:47:31PM +0200, Maxime Ripard wrote:
> New KMS properties come with a bunch of requirements to avoid each
> driver from running their own, inconsistent, set of properties,
> eventually leading to issues like property conflicts, inconsistencies
> between drivers and semanti
Hi Maxime,
On Thu, Jun 10, 2021 at 07:47:31PM +0200, Maxime Ripard wrote:
> New KMS properties come with a bunch of requirements to avoid each
> driver from running their own, inconsistent, set of properties,
> eventually leading to issues like property conflicts, inconsistencies
> between drivers
Am 10.06.21 um 19:11 schrieb Daniel Vetter:
On Thu, Jun 10, 2021 at 06:54:13PM +0200, Christian König wrote:
Am 10.06.21 um 18:37 schrieb Daniel Vetter:
On Thu, Jun 10, 2021 at 6:24 PM Jason Ekstrand wrote:
On Thu, Jun 10, 2021 at 10:13 AM Daniel Vetter wrote:
On Thu, Jun 10, 2021 at 3:5
On Wed, 02 Jun 2021 22:37:30 +0200, Marek Vasut wrote:
> Decoder input LVDS format is a property of the decoder chip or even
> its strapping. Add DT property data-mapping the same way lvds-panel
> does, to define the LVDS data mapping.
>
> Signed-off-by: Marek Vasut
> Cc: Laurent Pinchart
> Cc:
On Thu, Jun 10, 2021 at 10:18:25AM +1000, Alistair Popple wrote:
> > > The main problem is split_huge_pmd_address() unconditionally calls a mmu
> > > notifier so I would need to plumb in passing an owner everywhere which
> > > could
> > > get messy.
> >
> > Could I ask why? split_huge_pmd_addres
Am 10.06.21 um 19:50 schrieb Ondrej Zary:
On Thursday 10 June 2021 08:43:06 Christian König wrote:
Am 09.06.21 um 22:00 schrieb Ondrej Zary:
On Wednesday 09 June 2021 11:21:05 Christian König wrote:
Am 09.06.21 um 09:10 schrieb Ondrej Zary:
On Wednesday 09 June 2021, Christian König wrote:
A
On Thursday 10 June 2021 08:43:06 Christian König wrote:
>
> Am 09.06.21 um 22:00 schrieb Ondrej Zary:
> > On Wednesday 09 June 2021 11:21:05 Christian König wrote:
> >> Am 09.06.21 um 09:10 schrieb Ondrej Zary:
> >>> On Wednesday 09 June 2021, Christian König wrote:
> Am 09.06.21 um 08:57 sc
On Thu, 10 Jun 2021 at 11:10, Daniel Vetter wrote:
>
> On Wed, Jun 09, 2021 at 05:21:19PM +0800, Desmond Cheong Zhi Xi wrote:
> > This patch eliminates the following smatch warning:
> > drivers/gpu/drm/drm_auth.c:320 drm_master_release() warn: unlocked access
> > 'master' (line 318) expected lock
New KMS properties come with a bunch of requirements to avoid each
driver from running their own, inconsistent, set of properties,
eventually leading to issues like property conflicts, inconsistencies
between drivers and semantics, etc.
Let's document what we expect.
Cc: Alexandre Belloni
Cc: Al
https://bugzilla.kernel.org/show_bug.cgi?id=213391
--- Comment #7 from Nirmoy (nirmoy.ai...@gmail.com) ---
Actually, I am wrong, I checked out v5.12.9-arch1 from Arch and realized the
fix I mentioned before isn't valid.
--
You may reply to this email to add a comment.
You are receiving this mai
On Thu, Jun 10, 2021 at 01:12:36PM +0200, Thierry Reding wrote:
> From: Thierry Reding
>
> Rather than open-coding the vendor extraction operation, use the newly
> introduced helper macro.
>
> Signed-off-by: Thierry Reding
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/tegra/fb.c| 2
On Thu, Jun 10, 2021 at 11:27:42AM +0300, Pekka Paalanen wrote:
> On Wed, 9 Jun 2021 20:00:38 -0300
> Leandro Ribeiro wrote:
>
> > In this patch we add a section to document what userspace should do to
> > find out the CRTC index. This is important as they may be many places in
> > the documenta
Hi Dave, Daniel,
Here's this week drm-misc-fixes PR
Thanks!
Maxime
drm-misc-fixes-2021-06-10:
One fix for snu4i that prevents it from probing, two locking fixes for
ttm and drm_auth, one off-by-x1000 fix for mcde and a fix for vc4 to
prevent an out-of-bounds access.
The following changes since c
Hi,
On Wed, Jun 09, 2021 at 09:23:27PM +, Simon Ser wrote:
> This function sends a hotplug uevent with a CONNECTOR property.
>
> Signed-off-by: Simon Ser
> ---
> drivers/gpu/drm/drm_sysfs.c | 25 +
> include/drm/drm_sysfs.h | 1 +
> 2 files changed, 26 insertion
On Thu, Jun 10, 2021 at 06:54:13PM +0200, Christian König wrote:
> Am 10.06.21 um 18:37 schrieb Daniel Vetter:
> > On Thu, Jun 10, 2021 at 6:24 PM Jason Ekstrand wrote:
> > > On Thu, Jun 10, 2021 at 10:13 AM Daniel Vetter
> > > wrote:
> > > > On Thu, Jun 10, 2021 at 3:59 PM Jason Ekstrand
> >
On Thu, Jun 10, 2021 at 11:52:23AM -0500, Jason Ekstrand wrote:
> On Thu, Jun 10, 2021 at 11:38 AM Daniel Vetter wrote:
> >
> > On Thu, Jun 10, 2021 at 6:24 PM Jason Ekstrand wrote:
> > >
> > > On Thu, Jun 10, 2021 at 10:13 AM Daniel Vetter
> > > wrote:
> > > >
> > > > On Thu, Jun 10, 2021 at 3
On 6/10/21 2:49 AM, Thomas Hellström (Intel) wrote:
Hi,
On 6/9/21 7:23 PM, Zack Rusin wrote:
The has_dx variable was only set during the initialization which
meant that UPDATE_SUBRESOURCE was never used. We were emulating it
with UPDATE_GB_IMAGE but that's always been a stop-gap. Instead
of has
Am 10.06.21 um 18:37 schrieb Daniel Vetter:
On Thu, Jun 10, 2021 at 6:24 PM Jason Ekstrand wrote:
On Thu, Jun 10, 2021 at 10:13 AM Daniel Vetter wrote:
On Thu, Jun 10, 2021 at 3:59 PM Jason Ekstrand wrote:
On Thu, Jun 10, 2021 at 1:51 AM Christian König
wrote:
Am 09.06.21 um 23:29 schrieb
On Thu, Jun 10, 2021 at 11:44 AM Daniel Vetter wrote:
>
> On Wed, Jun 09, 2021 at 11:00:26AM -0500, Jason Ekstrand wrote:
> > On Wed, Jun 9, 2021 at 6:28 AM Daniel Vetter wrote:
> > >
> > > On Tue, Jun 08, 2021 at 11:35:58PM -0500, Jason Ekstrand wrote:
> > > > The current context uAPI allows for
On Thu, Jun 10, 2021 at 11:38 AM Daniel Vetter wrote:
>
> On Thu, Jun 10, 2021 at 6:24 PM Jason Ekstrand wrote:
> >
> > On Thu, Jun 10, 2021 at 10:13 AM Daniel Vetter
> > wrote:
> > >
> > > On Thu, Jun 10, 2021 at 3:59 PM Jason Ekstrand
> > > wrote:
> > > >
> > > > On Thu, Jun 10, 2021 at 1:5
On Thu, Jun 10, 2021 at 11:21:39PM +0800, Desmond Cheong Zhi Xi wrote:
> On 10/6/21 6:10 pm, Daniel Vetter wrote:
> > On Wed, Jun 09, 2021 at 05:21:19PM +0800, Desmond Cheong Zhi Xi wrote:
> > > This patch eliminates the following smatch warning:
> > > drivers/gpu/drm/drm_auth.c:320 drm_master_rele
Am 10.06.21 um 18:34 schrieb Michel Dänzer:
On 2021-06-10 11:17 a.m., Christian König wrote:
Since we can't find a consensus on hot to move forward with the dma_resv object
I concentrated on changing the approach for amdgpu first.
This new approach changes how the driver stores the command sub
On Wed, Jun 09, 2021 at 11:00:26AM -0500, Jason Ekstrand wrote:
> On Wed, Jun 9, 2021 at 6:28 AM Daniel Vetter wrote:
> >
> > On Tue, Jun 08, 2021 at 11:35:58PM -0500, Jason Ekstrand wrote:
> > > The current context uAPI allows for two methods of setting context
> > > parameters: SET_CONTEXT_PARAM
On Wed, Jun 09, 2021 at 04:07:24PM +0200, Christian König wrote:
> Am 09.06.21 um 15:42 schrieb Daniel Vetter:
> > [SNIP]
> > > That won't work. The problem is that you have only one exclusive slot, but
> > > multiple submissions which execute out of order and compose the buffer
> > > object togeth
On Thu, Jun 10, 2021 at 6:24 PM Jason Ekstrand wrote:
>
> On Thu, Jun 10, 2021 at 10:13 AM Daniel Vetter wrote:
> >
> > On Thu, Jun 10, 2021 at 3:59 PM Jason Ekstrand wrote:
> > >
> > > On Thu, Jun 10, 2021 at 1:51 AM Christian König
> > > wrote:
> > > >
> > > > Am 09.06.21 um 23:29 schrieb Jas
Hi Dmitry
I will take a look at this next week for sure.
Thanks
Abhinav
On 2021-06-10 06:48, Dmitry Baryshkov wrote:
On 15/05/2021 16:12, Dmitry Baryshkov wrote:
This patch series brings back several patches targeting assigning
dispcc
clock parents, that were removed from the massive dsi rew
On 2021-06-10 11:17 a.m., Christian König wrote:
> Since we can't find a consensus on hot to move forward with the dma_resv
> object I concentrated on changing the approach for amdgpu first.
>
> This new approach changes how the driver stores the command submission fence
> in the dma_resv object
Hi guys,
maybe soften that a bit. Reading from the shared memory of the user
fence is ok for everybody. What we need to take more care of is the
writing side.
So my current thinking is that we allow read only access, but writing a
new sequence value needs to go through the scheduler/kernel.
On Thu, Jun 10, 2021 at 10:07 AM Tvrtko Ursulin
wrote:
>
> On 10/06/2021 14:57, Jason Ekstrand wrote:
> > On Thu, Jun 10, 2021 at 5:04 AM Tvrtko Ursulin
> > wrote:
> >>
> >> On 09/06/2021 22:29, Jason Ekstrand wrote:
> >>> This appears to break encapsulation by moving an intel_engine_cs
> >>> fun
On Thu, Jun 10, 2021 at 10:13 AM Daniel Vetter wrote:
>
> On Thu, Jun 10, 2021 at 3:59 PM Jason Ekstrand wrote:
> >
> > On Thu, Jun 10, 2021 at 1:51 AM Christian König
> > wrote:
> > >
> > > Am 09.06.21 um 23:29 schrieb Jason Ekstrand:
> > > > This helper existed to handle the weird corner-cases
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