Hi Vinay,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next drm/drm-next v5.13 next-20210709]
[If your patch is applied to the wrong git tree
On Fri, Jul 09, 2021 at 05:16:34PM -0700, John Harrison wrote:
> On 6/24/2021 00:04, Matthew Brost wrote:
> > When running the GuC the GPU can't be considered idle if the GuC still
> > has contexts pinned. As such, a call has been added in
> > intel_gt_wait_for_idle to idle the UC and in turn the
On Fri, Jul 09, 2021 at 03:59:11PM -0700, John Harrison wrote:
> On 6/24/2021 00:04, Matthew Brost wrote:
> > Extend the deregistration context fence to fence whne a GuC context has
> > scheduling disable pending.
> >
> > Cc: John Harrison
> > Signed-off-by: Matthew Brost
> > ---
> >
Hi Vinay,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next drm/drm-next v5.13 next-20210709]
[If your patch is applied to the wrong git tree
On Fri, Jul 09, 2021 at 03:53:29PM -0700, John Harrison wrote:
> On 6/24/2021 00:04, Matthew Brost wrote:
> > Disable engine barriers for unpinning with GuC. This feature isn't
> > needed with the GuC as it disables context scheduling before unpinning
> > which guarantees the HW will not reference
From: Uwe Kleine-König
[ Upstream commit b9481a667a90ec739995e85f91f3672ca44d6ffa ]
According to .update_status() is supposed to
return 0 on success and a negative error code otherwise. Adapt
lm3630a_bank_a_update_status() and lm3630a_bank_b_update_status() to
actually do it.
While touching
From: Uwe Kleine-König
[ Upstream commit b9481a667a90ec739995e85f91f3672ca44d6ffa ]
According to .update_status() is supposed to
return 0 on success and a negative error code otherwise. Adapt
lm3630a_bank_a_update_status() and lm3630a_bank_b_update_status() to
actually do it.
While touching
From: Uwe Kleine-König
[ Upstream commit b9481a667a90ec739995e85f91f3672ca44d6ffa ]
According to .update_status() is supposed to
return 0 on success and a negative error code otherwise. Adapt
lm3630a_bank_a_update_status() and lm3630a_bank_b_update_status() to
actually do it.
While touching
From: Uwe Kleine-König
[ Upstream commit b9481a667a90ec739995e85f91f3672ca44d6ffa ]
According to .update_status() is supposed to
return 0 on success and a negative error code otherwise. Adapt
lm3630a_bank_a_update_status() and lm3630a_bank_b_update_status() to
actually do it.
While touching
From: Uwe Kleine-König
[ Upstream commit b9481a667a90ec739995e85f91f3672ca44d6ffa ]
According to .update_status() is supposed to
return 0 on success and a negative error code otherwise. Adapt
lm3630a_bank_a_update_status() and lm3630a_bank_b_update_status() to
actually do it.
While touching
From: Uwe Kleine-König
[ Upstream commit b9481a667a90ec739995e85f91f3672ca44d6ffa ]
According to .update_status() is supposed to
return 0 on success and a negative error code otherwise. Adapt
lm3630a_bank_a_update_status() and lm3630a_bank_b_update_status() to
actually do it.
While touching
From: Uwe Kleine-König
[ Upstream commit b9481a667a90ec739995e85f91f3672ca44d6ffa ]
According to .update_status() is supposed to
return 0 on success and a negative error code otherwise. Adapt
lm3630a_bank_a_update_status() and lm3630a_bank_b_update_status() to
actually do it.
While touching
This feature hands over the control of HW RC6 to the GUC.
GUC decides when to put HW into RC6 based on it's internal
busyness algorithms.
GUCRC needs GUC submission to be enabled, and only
supported on Gen12+ for now.
When GUCRC is enabled, do not set HW RC6. Use a H2G message
to tell guc to
Tests that exercise the slpc get/set frequency interfaces.
Clamp_max will set max frequency to multiple levels and check
that slpc requests frequency lower than or equal to it.
Clamp_min will set min frequency to different levels and check
if slpc requests are higher or equal to those levels.
Update the get/set min/max freq hooks to work for
slpc case as well. Consolidate helpers for requested/min/max
frequency get/set to intel_rps where the proper action can
be taken depending on whether slpc is enabled.
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Tvrtko Ursulin
Signed-off-by:
SLPC requests efficient frequency by default instead of min.
It provides a flag to turn this off. Set that flag to maintain
original semantics so that tests do not fail. SLPC can also
request frequency that is much higher than the platform max,
update that as well for the same reason.
Cache rp0, rp1 and rpn platform limits into slpc structure
for range checking while setting min/max frequencies.
Also add "soft" limits which keep track of frequency changes
made from userland. These are initially set to platform min
and max.
Signed-off-by: Vinay Belgaumkar
---
This interrupt is enabled during RPS initialization, and
now needs to be done by slpc code. It allows ARAT timer
expiry interrupts to get forwarded to GuC.
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 16
This prints out relevant SLPC info from the SLPC shared structure.
We will send a h2g message which forces SLPC to update the
shared data structure with latest information before reading it.
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
Add helpers to read the min/max frequency being used
by SLPC. This is done by send a h2g command which forces
SLPC to update the shared data struct which can then be
read.
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 58
Add param set h2g helpers to set the min and max frequencies
for use by SLPC.
Signed-off-by: Sundaresan Sujaritha
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 94 +
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 2 +
2 files changed, 96
Add methods for interacting with guc for enabling SLPC. Enable
SLPC after guc submission has been established. GuC load will
fail if SLPC cannot be successfully initialized. Add various
helper methods to set/unset the parameters for SLPC. They can
be set using h2g calls or directly setting bits in
Allocate data structures for SLPC and functions for
initializing on host side.
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 11 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 36 -
Replicate the SLPC header file in GuC for the most part. There are
some SLPC mode based parameters which haven't been included since
we are not using them.
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 4 +
Declare header and source files for SLPC, along with init and
enable/disable function templates.
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 ++
Disable RPS when slpc is enabled. Also ensure uc_init is called
before we initialize RPS so that we can check for slpc support.
We do not need to enable up/down interrupts when slpc is enabled.
However, we still need the ARAT interrupt, which will be enabled
separately.
Signed-off-by: Vinay
Add macros to check for slpc support. This feature is currently supported
for gen12+ and enabled whenever guc submission is enabled/selected.
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c
This series enables Single Loop Power Control (SLPC) feature in GuC.
GuC implements various power management algorithms as part of it's
operation. These need to be specifically enabled by KMD. They replace
the legacy host based management of these features.
With this series, we will enable two PM
On 2021-07-09 16:50, Dmitry Baryshkov wrote:
Move setting up encoders from set_encoder_mode to
_dpu_kms_initialize_dsi() / _dpu_kms_initialize_displayport(). This
allows us to support not only "single DSI" and "bonded DSI" but also
"two
independent DSI" configurations. In future this would
KFD Thunk maps invisible VRAM BOs with PROT_NONE, MAP_PRIVATE.
is_cow_mapping returns true for these mappings. Add a check for
vm_flags & VM_WRITE to avoid mmap failures on private read-only or
PROT_NONE mappings.
v2: protect against mprotect making a mapping writable after the fact
Fixes:
On 2021-07-09 3:37 p.m., Christian König wrote:
Am 09.07.21 um 21:31 schrieb Felix Kuehling:
On 2021-07-09 2:38 a.m., Christian König wrote:
Am 08.07.21 um 21:36 schrieb Alex Deucher:
From: Felix Kuehling
KFD Thunk maps invisible VRAM BOs with PROT_NONE, MAP_PRIVATE.
is_cow_mapping
On 6/24/2021 00:04, Matthew Brost wrote:
When running the GuC the GPU can't be considered idle if the GuC still
has contexts pinned. As such, a call has been added in
intel_gt_wait_for_idle to idle the UC and in turn the GuC by waiting for
the number of unpinned contexts to go to zero.
v2:
On 6/24/2021 00:04, Matthew Brost wrote:
Semaphores are an optimization and not required for basic GuC submission
to work properly. Disable until we have time to do the implementation to
enable semaphores and tune them for performance. Also long direction is
just to delete semaphores from the
Add two helper functions to be used by display drivers for setting up
encoders.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/dsi.c | 7 +++
drivers/gpu/drm/msm/dsi/dsi_manager.c | 14 ++
drivers/gpu/drm/msm/msm_drv.h |
Move a call to mdp5_encoder_set_intf_mode() after
msm_dsi_modeset_init(), removing set_encoder_mode callback.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git
set_encoder_mode callback is completely unused now. Drop it from
msm_kms_func().
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/msm_kms.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
None of the display drivers now implement set_encoder_mode callback.
Stop calling it from the modeset init code.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_display.c | 18 --
1 file changed, 18 deletions(-)
diff --git
Move setting up encoders from set_encoder_mode to
_dpu_kms_initialize_dsi() / _dpu_kms_initialize_displayport(). This
allows us to support not only "single DSI" and "bonded DSI" but also "two
independent DSI" configurations. In future this would also help adding
support for multiple DP connectors.
None of the display drivers now implement set_encoder_mode callback.
Stop calling it from the modeset init code.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/dsi.c | 2 --
drivers/gpu/drm/msm/dsi/dsi.h | 1 -
We are preparing to support two independent DSI hosts in the DSI/DPU
code. To remove possible confusion (as both configurations can be
referenced as dual DSI) let's rename old "dual DSI" (two DSI hosts
driving single device, with clocks being locked) to "bonded DSI".
Signed-off-by: Dmitry
This patchseries adds support for independent DSI config to DPU1 display
subdriver. Also drop one of msm_kms_funcs callbacks, made unnecessary
now.
Tested on RB5 (dpu, dsi). Previous iteration was tested by Alexey
Minnekhanov.
Cahanges since v1:
- Rewrote dsi encoder setup function by
On 10/07/2021 01:16, abhin...@codeaurora.org wrote:
On 2021-07-08 05:28, Dmitry Baryshkov wrote:
None of the display drivers now implement set_encoder_mode callback.
Stop calling it from the modeset init code.
Signed-off-by: Dmitry Baryshkov
The change looks fine,
Reviewed-by: Abhinav Kumar
On 6/24/2021 00:04, Matthew Brost wrote:
Disable preempt busywait when using GuC scheduling. This isn't need as
needed
the GuC control preemption when scheduling.
controls
With the above fixed:
Reviewed-by: John Harrison
Cc: John Harrison
Signed-off-by: Matthew Brost
---
On 6/24/2021 00:04, Matthew Brost wrote:
Extend the deregistration context fence to fence whne a GuC context has
scheduling disable pending.
Cc: John Harrison
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +++
1 file changed, 30
On 6/24/2021 00:04, Matthew Brost wrote:
Disable engine barriers for unpinning with GuC. This feature isn't
needed with the GuC as it disables context scheduling before unpinning
which guarantees the HW will not reference the context. Hence it is
not necessary to defer unpinning until a kernel
On 6/24/2021 00:04, Matthew Brost wrote:
With GuC scheduling, it isn't safe to unpin a context while scheduling
is enabled for that context as the GuC may touch some of the pinned
state (e.g. LRC). To ensure scheduling isn't enabled when an unpin is
done, a call back is added to
On 6/24/2021 00:04, Matthew Brost wrote:
Sometime during context pinning a context with the same guc_id is
Sometime*s*
registered with the GuC. In this a case deregister must be before before
before before -> done before
the context can be registered. A fence is inserted on all requests
Hi,
On Fri, Jul 9, 2021 at 1:41 PM Ville Syrjälä
wrote:
>
> On Fri, Jul 09, 2021 at 06:54:05AM -0700, Doug Anderson wrote:
> > Hi,
> >
> > On Sat, Jun 26, 2021 at 9:52 AM Rajeev Nandan
> > wrote:
> > >
> > > This series adds the support for the eDP panel that needs the backlight
> > >
We were getting a depmod error:
depmod: ERROR: Cycle detected: drm_kms_helper -> drm -> drm_kms_helper
It looks like the rule is that drm_kms_helper can call into drm, but
drm can't call into drm_kms_helper. That means we've got to move the
DP AUX backlight support into drm_dp_helper.
NOTE: as
On 2021-07-08 05:28, Dmitry Baryshkov wrote:
set_encoder_mode callback is completely unused now. Drop it from
msm_kms_func().
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/msm_kms.h | 3 ---
1 file changed, 3 deletions(-)
diff --git
On 2021-07-08 05:28, Dmitry Baryshkov wrote:
None of the display drivers now implement set_encoder_mode callback.
Stop calling it from the modeset init code.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/dsi.c | 2 --
On 2021-07-08 05:28, Dmitry Baryshkov wrote:
None of the display drivers now implement set_encoder_mode callback.
Stop calling it from the modeset init code.
Signed-off-by: Dmitry Baryshkov
The change looks fine,
Reviewed-by: Abhinav Kumar
But has DP been re-verified with this change by
On 2021-07-08 05:28, Dmitry Baryshkov wrote:
Move a call to mdp5_encoder_set_intf_mode() after
msm_dsi_modeset_init(), removing set_encoder_mode callback.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 11 +++
1 file
On 2021-07-08 05:28, Dmitry Baryshkov wrote:
Add two helper functions to be used by display drivers for setting up
encoders.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/dsi.c | 7 +++
drivers/gpu/drm/msm/dsi/dsi_manager.c | 14
On 2021-07-08 05:28, Dmitry Baryshkov wrote:
We are preparing to support two independent DSI hosts in the DSI/DPU
code. To remove possible confusion (as both configurations can be
referenced as dual DSI) let's rename old "dual DSI" (two DSI hosts
driving single device, with clocks being locked)
On 10/07/2021 01:09, abhin...@codeaurora.org wrote:
On 2021-07-08 05:28, Dmitry Baryshkov wrote:
Move setting up encoders from set_encoder_mode to
_dpu_kms_initialize_dsi() / _dpu_kms_initialize_displayport(). This
allows us to support not only "single DSI" and "bonded DSI" but also "two
On 2021-07-08 05:28, Dmitry Baryshkov wrote:
Move setting up encoders from set_encoder_mode to
_dpu_kms_initialize_dsi() / _dpu_kms_initialize_displayport(). This
allows us to support not only "single DSI" and "bonded DSI" but also
"two
independent DSI" configurations. In future this would
On Fri, Jul 9 2021 at 09:49:02 AM +0200, Geert Uytterhoeven
wrote:
Bummer, more code to revert to re-enable acceleration in the _56_
fbdev drivers using acceleration (some of them unusable without),
despite commit 39aead8373b3 claiming "No other driver supportes
accelerated fbcon"...
Should
Hello Thierry,
09.07.2021 22:31, Thierry Reding пишет:
> From: Thierry Reding
>
> Hi all,
>
> Mikko has been away for a few weeks, so I've been testing and revising
> the new UABI patches in the meantime. There are very minor changes to
> the naming of some of the UABI fields, but other than
Instead of fetching shared timing through an extra function call, get
them directly from msm_dsi_phy_enable.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/dsi.h | 5 ++---
drivers/gpu/drm/msm/dsi/dsi_manager.c | 3 +--
Use of_device_get_match-data() instead of of_match_node().
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
Assign DSI clock source parents to DSI PHY clocks.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index
There is no reason to set clock parents manually, use device tree to
assign DSI/display clock parents to DSI PHY clocks. Dropping this manual
setup allows us to drop repeating code and to move registration of hw
clock providers to generic place.
Signed-off-by: Dmitry Baryshkov
Reviewed-by:
Assign DSI clock source parents to DSI PHY clocks.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index
Assign DSI clock source parents to DSI PHY clocks.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
Assign DSI clock source parents to DSI PHY clocks.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index
Restore the assgined-clocks and assigned-clock-parents properties that
were lost during the txt -> YAML conversion.
Signed-off-by: Dmitry Baryshkov
---
.../display/msm/dsi-controller-main.yaml| 17 +
1 file changed, 17 insertions(+)
diff --git
This patch series brings back several patches targeting assigning dispcc
clock parents, that were removed from the massive dsi rework patchset
earlier.
Few notes:
- assign-clock-parents is a mandatory proprety according to the current
dsi.txt description.
- There is little point in
Hi Yunus and Stefan,
On Fri, Jul 09, 2021 at 10:03:48PM +0200, Yunus Bas wrote:
> From: Stefan Riedmueller
>
> This patch adds support for the EDT ETMV570G2DHU 5.7" (640x480) lcd panel
> to DRM simple panel driver.
>
> Signed-off-by: Stefan Riedmueller
> Signed-off-by: Yunus Bas
Thanks for
On Fri, Jul 09, 2021 at 06:54:05AM -0700, Doug Anderson wrote:
> Hi,
>
> On Sat, Jun 26, 2021 at 9:52 AM Rajeev Nandan wrote:
> >
> > This series adds the support for the eDP panel that needs the backlight
> > controlling over the DP AUX channel using DPCD registers of the panel
> > as per the
On 7/9/21 4:04 PM, Dave Airlie wrote:
cc'ing Christian to fix this I assume it was ttm refactor?
Yes, but it's on me because after fixing it I kept forgetting to queue it up
for a merge. It's now in drm-misc/drm-misc-next-fixes.
Thomas, if you could make sure your next drm-misc-next-fixes
There is no need to free a NULL value. Instead, free the object
that is leaking due to the iterator.
The semantic patch that finds this problem is as follows:
//
@@
expression x,e;
identifier f;
@@
x = f(...);
if (x == NULL) {
... when any
when != x = e
*
cc'ing Christian to fix this I assume it was ttm refactor?
>
> This patch fixes vmwgfx driver compilation error due to a missing include
>
> drivers/gpu/drm/vmwgfx/vmwgfx_drv.c: In function ‘vmw_vram_manager_init’:
> drivers/gpu/drm/vmwgfx/vmwgfx_drv.c:678:8: error: implicit declaration of
>
From: Stefan Riedmueller
This patch adds support for the EDT ETM0350G0DH6 3.5" (320x240) lcd
panel to DRM simple panel driver.
Signed-off-by: Stefan Riedmueller
Signed-off-by: Yunus Bas
---
drivers/gpu/drm/panel/panel-simple.c | 29
1 file changed, 29
From: Stefan Riedmueller
This patch adds support for the EDT ETMV570G2DHU 5.7" (640x480) lcd panel
to DRM simple panel driver.
Signed-off-by: Stefan Riedmueller
Signed-off-by: Yunus Bas
---
Changes in v4:
- Moved code to proper place to keep alphabetic order
---
On 7/9/21 11:09 AM, Tong Zhang wrote:
> This patch fixes vmwgfx driver compilation error due to a missing include
>
> drivers/gpu/drm/vmwgfx/vmwgfx_drv.c: In function ‘vmw_vram_manager_init’:
> drivers/gpu/drm/vmwgfx/vmwgfx_drv.c:678:8: error: implicit declaration of
> function
Am 09.07.21 um 21:31 schrieb Felix Kuehling:
On 2021-07-09 2:38 a.m., Christian König wrote:
Am 08.07.21 um 21:36 schrieb Alex Deucher:
From: Felix Kuehling
KFD Thunk maps invisible VRAM BOs with PROT_NONE, MAP_PRIVATE.
is_cow_mapping returns true for these mappings. Add a check for
On Tue, Jun 29, 2021 at 1:52 PM Jing Xiangfeng wrote:
>
> psb_user_framebuffer_create() misses to call drm_gem_object_put() in an
> error path. Add the missed function call to fix it.
>
Sorry for the delay, I'm currently on vacation.
Looks good. Thanks for the patch.
Applied to drm-misc-next
Am Freitag, dem 09.07.2021 um 21:30 +0200 schrieb Sam Ravnborg:
> Hi Yunus,
>
> On Fri, Jul 09, 2021 at 07:02:52PM +, Yunus Bas wrote:
> > Hi Sam,
> >
> > Am Freitag, dem 09.07.2021 um 20:12 +0200 schrieb Sam Ravnborg:
> > > Hi Yunus,
> > >
> > > On Tue, Jul 06, 2021 at 09:59:08AM +0200,
On 2021-07-09 2:38 a.m., Christian König wrote:
Am 08.07.21 um 21:36 schrieb Alex Deucher:
From: Felix Kuehling
KFD Thunk maps invisible VRAM BOs with PROT_NONE, MAP_PRIVATE.
is_cow_mapping returns true for these mappings. Add a check for
vm_flags & VM_WRITE to avoid mmap failures on
Hi Yunus,
On Fri, Jul 09, 2021 at 07:02:52PM +, Yunus Bas wrote:
> Hi Sam,
>
> Am Freitag, dem 09.07.2021 um 20:12 +0200 schrieb Sam Ravnborg:
> > Hi Yunus,
> >
> > On Tue, Jul 06, 2021 at 09:59:08AM +0200, Yunus Bas wrote:
> > > From: Stefan Riedmueller
> > >
> > > This patch adds
From: Mikko Perttunen
Add a firewall that validates jobs before submission to ensure
they don't do anything they aren't allowed to do, like accessing
memory they should not access.
The firewall is functionality-wise a copy of the firewall already
implemented in gpu/host1x. It is copied here as
From: Mikko Perttunen
Bump driver version to 1.0.0 to allow userspace to detect
availability of new interfaces.
Signed-off-by: Mikko Perttunen
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/tegra/drm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Mikko Perttunen
Implement the job submission IOCTL with a minimum feature set.
Signed-off-by: Mikko Perttunen
Signed-off-by: Thierry Reding
---
Changes in v8:
- rebased on top of latest UABI changes
drivers/gpu/drm/tegra/Makefile| 2 +
drivers/gpu/drm/tegra/drm.c | 4 +-
From: Mikko Perttunen
Implement new syncpoint wait UAPI. This is different from the
legacy one in taking an absolute timestamp in line with modern
DRM conventions.
Signed-off-by: Mikko Perttunen
Signed-off-by: Thierry Reding
---
Changes in v8:
- rebase on top of latest UABI changes
From: Mikko Perttunen
Implement TegraDRM IOCTLs for allocating and freeing syncpoints.
Signed-off-by: Mikko Perttunen
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/tegra/drm.c | 5
drivers/gpu/drm/tegra/uapi.c | 52
drivers/gpu/drm/tegra/uapi.h
From: Mikko Perttunen
Implement the non-submission parts of the new UAPI, including
channel management and memory mapping. The UAPI is under the
CONFIG_DRM_TEGRA_STAGING config flag for now.
Signed-off-by: Mikko Perttunen
Signed-off-by: Thierry Reding
---
Changes in v8:
- rebase on top of
From: Mikko Perttunen
To avoid code duplication, allocate the per-engine shared channel in
the core code instead. This is the usual channel that all jobs are
submitted to when MLOCKing is not in use. Once MLOCKs are implemented
on Host1x side, we can also update this to avoid allocating a shared
From: Mikko Perttunen
With the new UAPI implementation, engines are powered on and off
when there are active jobs, and the core code handles channel
allocation. To accommodate that, boot the engine as part of
runtime PM instead of using the open_channel callback, which is
not used by the new
From: Mikko Perttunen
Update the tegra_drm.h UAPI header, adding the new proposed UAPI.
The old staging UAPI is left in for now, with minor modification
to avoid name collisions.
Signed-off-by: Mikko Perttunen
Signed-off-by: Thierry Reding
---
Changes in v8:
- renamed hardware_flags to
From: Mikko Perttunen
The static function host1x_bo_lookup in drm.c is also useful
elsewhere. Extract it as tegra_gem_lookup in gem.c.
Signed-off-by: Mikko Perttunen
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/tegra/drm.c | 20 +++-
drivers/gpu/drm/tegra/gem.c | 13
From: Mikko Perttunen
Add support for inserting syncpoint waits in the CDMA pushbuffer.
These waits need to be done in HOST1X class, while gather submitted
by the application execute in engine class.
Support is added by converting the gather list of job into a command
list that can include both
From: Mikko Perttunen
Add a callback field to the job structure, to be called just before
the job is to be freed. This allows the job's submitter to clean
up any of its own state, like decrement runtime PM refcounts.
Signed-off-by: Mikko Perttunen
Signed-off-by: Thierry Reding
---
From: Mikko Perttunen
Add a new property for jobs to enable or disable recovery i.e.
CPU increments of syncpoints to max value on job timeout. This
allows for a more solid model for hanged jobs, where userspace
doesn't need to guess if a syncpoint increment happened because
the job completed, or
From: Mikko Perttunen
Add an implementation of dma_fences based on syncpoints. Syncpoint
interrupts are used to signal fences. Additionally, after
software signaling has been enabled, a 30 second timeout is started.
If the syncpoint threshold is not reached within this period,
the fence is
From: Thierry Reding
Hi all,
Mikko has been away for a few weeks, so I've been testing and revising
the new UABI patches in the meantime. There are very minor changes to
the naming of some of the UABI fields, but other than that it's mostly
unchanged from v7.
One notable change is that
On Mon, Jul 05, 2021 at 02:45:08PM +0200, Thomas Zimmermann wrote:
> The S parameter is controls the loop filter bandwidth when programming
> the PLL. It's currently stored as part of P (i.e., the clock divider.)
> Add a separate variable for S prepares the PLL code for a further
> refactoring.
>
Ho Thomas,
On Mon, Jul 05, 2021 at 02:45:07PM +0200, Thomas Zimmermann wrote:
> The _set_plls() functions compute a pixel clock's PLL values
> and program the hardware accordingly. This happens during atomic
> commits.
>
> For atomic modesetting, it's better to separate computation and
>
Hi Sam,
Am Freitag, dem 09.07.2021 um 20:12 +0200 schrieb Sam Ravnborg:
> Hi Yunus,
>
> On Tue, Jul 06, 2021 at 09:59:08AM +0200, Yunus Bas wrote:
> > From: Stefan Riedmueller
> >
> > This patch adds support for the EDT ETM0350G0DH6 3.5" (320x240) lcd
> > panel to DRM simple panel driver.
> >
Hi Sam,
Am Freitag, dem 09.07.2021 um 20:08 +0200 schrieb Sam Ravnborg:
> Hi Yunus,
>
> On Tue, Jul 06, 2021 at 09:59:07AM +0200, Yunus Bas wrote:
> > From: Stefan Riedmueller
> >
> > This patch adds support for the EDT ETMV570G2DHU 5.7" (640x480) lcd
> > panel
> > to DRM simple panel driver.
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