Hi James,
Evan seems to have understood how this all works together.
See while any begin/end use critical section is active the work should not be
active.
When you handle only one ring you can just call cancel in begin use and
schedule in end use. But when you have more than one ring you need
[AMD Official Use Only]
Reviewed-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of
> Michel Dänzer
> Sent: Thursday, August 12, 2021 12:52 AM
> To: Deucher, Alexander ; Koenig, Christian
>
> Cc: Liu, Leo ; Zhu, James ; amd-
> g...@lists.freedesktop.org;
[AMD Official Use Only]
Different from the 1st patch(for amdgpu_gfx_off_ctrl) of the series,
"cancel_delayed_work_sync(>uvd.idle_work)" will be called on like
amdgpu_uvd_ring_begin_use(). Under this case, does it make any difference from
previous implementation "schedule_delayed_work"?
Hi Dave, Daniel,
Fixes for 5.14.
The following changes since commit d186f9c28008810d8f984d6bdd1c07757048ed63:
Merge tag 'amd-drm-fixes-5.14-2021-08-05' of
https://gitlab.freedesktop.org/agd5f/linux into drm-fixes (2021-08-06 11:22:09
+1000)
are available in the Git repository at:
Hi all,
Today's linux-next merge of the drm-intel tree got a conflict in:
drivers/gpu/drm/i915/intel_device_info.h
between commit:
3ffe82d701a4 ("drm/i915/xehp: handle new steering options")
from the drm tree and commit:
22e26af76903 ("drm/i915: Fork DG1 interrupt handler")
from the
Hi all,
Today's linux-next merge of the drm tree got a conflict in:
drivers/gpu/drm/i915/i915_globals.c
between commits:
1354d830cb8f ("drm/i915: Call i915_globals_exit() if pci_register_device()
fails")
a07296453bf2 ("drm/i915: fix i915_globals_exit() section mismatch error")
from
I will investigate it further. I am using DKMS-5.11 branch. The codebase I am
using to build has the right definition i.e. allow P2PDMA for Zen CPU's.
Regards,
Ramesh
-Original Message-
From: Alex Deucher
Sent: Wednesday, August 11, 2021 4:07 PM
To: Kuehling, Felix
Cc: Errabolu,
Quoting Sankeerth Billakanti (2021-08-11 17:08:01)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index b131fd37..1096c44 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++
Quoting Sankeerth Billakanti (2021-08-11 17:08:02)
> The Qualcomm SC7280 platform supports an eDP controller, add
> compatible string for it to msm/binding.
>
> Signed-off-by: Sankeerth Billakanti
> ---
> Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 3 +++
> 1 file changed,
Quoting Rob Clark (2021-08-11 16:52:47)
> From: Rob Clark
>
> If we created our own connector because the driver does not support the
> NO_CONNECTOR flag, we don't want the downstream bridge to *also* create
> a connector. And if this driver did pass the NO_CONNECTOR flag (and we
> supported
Hi, Yongqiang:
Yongqiang Niu 於 2021年8月11日 週三 上午9:48寫道：
>
> In cmdq mode, packet may be flushed before it is executed, so
> the pending flag should be cleared after cmdq packet is done.
Applied to mediatek-drm-next [1], thanks.
[1]
The Qualcomm SC7280 platform supports an eDP controller, add
compatible string for it to msm/binding.
Signed-off-by: Sankeerth Billakanti
---
Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git
The eDP controller on SC7280 is similar to the eDP/DP controllers
supported by the current driver implementation.
SC7280 supports one EDP and one DP controller which can operate
concurrently.
The following are some required changes for the sc7280 sink:
1. Additional gpio configuration for
This series will add eDP controller support for Qualcomm SC7280
platform. These patches are baseline changes with which we can enable
eDP display on sc7280. The sc7280 eDP controller can also support
additional features such as backlight control, PSR etc. which will be
enabled in
Chun-Kuang Hu 於 2021年8月9日 週一 上午7:47寫道：
>
> These refinements include using standard mailbox callback interface,
> timeout detection, and a fixed cmdq_handle.
For this series, applied to mediatek-drm-next [1].
[1]
From: Rob Clark
Slightly awkward to fish out the display_info when we aren't creating
own connector. But I don't see an obvious better way.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 34 +++
1 file changed, 29 insertions(+), 5 deletions(-)
From: Rob Clark
For the brave new world of bridges not creating their own connectors, we
need to implement the max clock limitation via bridge->mode_valid()
instead of connector->mode_valid().
Signed-off-by: Rob Clark
---
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 24 +++-
1
From: Rob Clark
For now, since we have a mix of bridges which support this flag, which
which do *not* support this flag, or work both ways, try it once with
NO_CONNECTOR and then fall back to the old way if that doesn't work.
Eventually we can drop the fallback path.
Signed-off-by: Rob Clark
From: Rob Clark
If we created our own connector because the driver does not support the
NO_CONNECTOR flag, we don't want the downstream bridge to *also* create
a connector. And if this driver did pass the NO_CONNECTOR flag (and we
supported that mode) this would change nothing.
Fixes:
From: Rob Clark
The first patch fixes breakage in drm-next for the ti eDP bridge (which
is used on nearly all the snapdragon windows laptops and chromebooks).
The second add drm/msm NO_CONNECTOR support, and the final two add
NO_CONNECTOR support to the ti eDP bridge.
Would be nice to get at
On Wed, Aug 11, 2021 at 09:32:49PM +, Simon Ser wrote:
Reviewed-by: Simon Ser
Do you need me to push this?
yes, please. I'm a committer only on drm-intel and I guess this should
go through another tree.
thanks
Lucas De Marchi
Hi, Jason:
jason-jh.lin 於 2021年8月10日 週二 下午12:02寫道：
>
> Add component_del in OVL and COLOR remove function.
Applied to mediatek-drm-fixes [1], thanks.
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-fixes
Regards,
Chun-Kuang.
>
> Fixes:
Hi, Jason:
jason-jh.lin 於 2021年8月10日 週二 上午10:55寫道：
>
> To avoid the output width and height is incorrect,
> AAL_OUTPUT_SIZE configuration should be set.
Applied to mediatek-drm-fixes [1], thanks.
[1]
Quoting Laurent Pinchart (2021-08-11 15:40:24)
> On Wed, Aug 11, 2021 at 01:51:28PM -0700, Rob Clark wrote:
> >
> > I kinda think *all* bridges that create a connector (whether optional
> > or not) should OR in NO_CONNECTOR when attaching the next downstream
> > bridge.. since you never want
On Wed, Aug 11, 2021 at 01:51:28PM -0700, Rob Clark wrote:
> On Wed, Aug 11, 2021 at 1:39 PM Stephen Boyd wrote:
> > Quoting Rob Clark (2021-08-11 09:20:30)
> > > On Wed, Aug 11, 2021 at 5:15 AM Laurent Pinchart wrote:
> > > > On Tue, Aug 10, 2021 at 10:26:33PM -0700, Stephen Boyd wrote:
> > > > >
[AMD Official Use Only]
I shouldn't say reduce one delay work call , For this case, Michael's proposal
is closer to idle work design's purpose.
Thanks & Best Regards!
James Zhu
From: amd-gfx on behalf of Zhu, James
Sent: Wednesday, August 11, 2021 6:12
[AMD Official Use Only]
Hi Christian,
Since we have strict check on queue status, I don't think original design can
cause issue here.
But this change should help improve below case:
1. both enc thread and dec thread try to start begin_use.
2. dec thread gets the chance to finish
On Thu, 5 Aug 2021 22:18:56 -0300
Jason Gunthorpe wrote:
> This is in support of Max's series to split vfio-pci. For that to work the
> reflck concept embedded in vfio-pci needs to be sharable across all of the
> new VFIO PCI drivers which motivated re-examining how this is
> implemented.
>
>
On Wednesday, August 11th, 2021 at 13:40, John Cox wrote:
> Raspberry Pi displaying video with subtitles or other controls. I was
> thinking of the fullscreen case but if zero copy video can be made to
> work to the main desktop then that would even better.
>
> If displaying 4k video the Pi
NAK to at least this patch.
Since activating power management while submitting work is problematic
cancel_delayed_work() must have been called during begin use or otherwise we
have a serious coding problem in the first place.
So this change shouldn't make a difference and I suggest to really
Reviewed-by: Simon Ser
Do you need me to push this?
On Wed, Aug 11, 2021 at 4:50 PM Felix Kuehling wrote:
>
>
> Am 2021-08-11 um 3:29 p.m. schrieb Alex Deucher:
> > On Wed, Aug 11, 2021 at 3:11 PM Ramesh Errabolu
> > wrote:
> >> Current implementation will disallow P2P DMA if the participating
> >> devices belong to different root complexes.
[AMD Official Use Only]
This patch is Reviewed-by: James Zhu
Thanks & Best Regards!
James Zhu
From: Alex Deucher
Sent: Wednesday, August 11, 2021 4:34 PM
To: Michel Dänzer
Cc: Deucher, Alexander ; Koenig, Christian
; Liu, Leo ; Zhu, James
; amd-gfx list
Byte 26 in a edid struct is supposed to be "Blue and white
least-significant 2 bits", not "black and white". Rename the field
accordingly. This field is not used anywhere, so just renaming it here
for correctness.
Signed-off-by: Lucas De Marchi
---
include/drm/drm_edid.h | 2 +-
1 file changed,
Am 2021-08-11 um 3:29 p.m. schrieb Alex Deucher:
> On Wed, Aug 11, 2021 at 3:11 PM Ramesh Errabolu
> wrote:
>> Current implementation will disallow P2P DMA if the participating
>> devices belong to different root complexes. Implementation allows
>> this default behavior to be overridden for
On Wed, Aug 11, 2021 at 1:39 PM Stephen Boyd wrote:
>
> Quoting Rob Clark (2021-08-11 09:20:30)
> > On Wed, Aug 11, 2021 at 5:15 AM Laurent Pinchart
> > wrote:
> > >
> > > Hi Stephen,
> > >
> > > On Tue, Aug 10, 2021 at 10:26:33PM -0700, Stephen Boyd wrote:
> > > > Quoting Laurent Pinchart
Quoting Rob Clark (2021-08-11 09:20:30)
> On Wed, Aug 11, 2021 at 5:15 AM Laurent Pinchart
> wrote:
> >
> > Hi Stephen,
> >
> > On Tue, Aug 10, 2021 at 10:26:33PM -0700, Stephen Boyd wrote:
> > > Quoting Laurent Pinchart (2021-06-23 17:03:02)
> > > > To simplify interfacing with the panel, wrap
On Wed, Aug 11, 2021 at 12:52 PM Michel Dänzer wrote:
>
> From: Michel Dänzer
>
> In contrast to schedule_delayed_work, this pushes back the work if it
> was already scheduled before. Specific behaviour change:
>
> Before:
>
> The scheduled work ran ~1 second after the first time ring_end_use
Applied. Thanks!
Alex
On Wed, Aug 11, 2021 at 7:35 AM Tuo Li wrote:
>
> The variable val is declared without initialization, and its address is
> passed to amdgpu_i2c_get_byte(). In this function, the value of val is
> accessed in:
> DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
>
On Wed, 2021-08-11 at 15:34 -0400, Rodrigo Vivi wrote:
> On Tue, Aug 10, 2021 at 04:52:11PM -0700, Juston Li wrote:
> > When reading RepeaterAuth_Send_ReceiverID_List, RxInfo is read by
> > itself
> > once to retrieve the DEVICE_COUNT to calculate the size of the
> > ReceiverID list then read a
On Tue, Aug 10, 2021 at 04:52:11PM -0700, Juston Li wrote:
> When reading RepeaterAuth_Send_ReceiverID_List, RxInfo is read by itself
> once to retrieve the DEVICE_COUNT to calculate the size of the
> ReceiverID list then read a second time as a part of reading ReceiverID
> list.
>
> On some MST
On Wed, Aug 11, 2021 at 3:11 PM Ramesh Errabolu wrote:
>
> Current implementation will disallow P2P DMA if the participating
> devices belong to different root complexes. Implementation allows
> this default behavior to be overridden for whitelisted devices. The
> patch adds an AMD host bridge to
Current implementation will disallow P2P DMA if the participating
devices belong to different root complexes. Implementation allows
this default behavior to be overridden for whitelisted devices. The
patch adds an AMD host bridge to be whitelisted
Signed-off-by: Ramesh Errabolu
---
On Wed, Aug 04, 2021 at 04:13:51PM +0800, Shawn Guo wrote:
> The Truly NT35521 is a 5.24" 1280x720 DSI panel, and the backlight is
> managed through DSI link.
>
> Signed-off-by: Shawn Guo
> ---
> .../bindings/display/panel/truly,nt35521.yaml | 62 +++
> 1 file changed, 62
On Wed, 04 Aug 2021 06:34:38 +0200, Oleksij Rempel wrote:
> Add SKOV imx6q/dl LT2, LT6 and mi1010ait-1cp1 boards.
>
> Signed-off-by: Oleksij Rempel
> ---
> Documentation/devicetree/bindings/arm/fsl.yaml | 5 +
> 1 file changed, 5 insertions(+)
>
Acked-by: Rob Herring
On Wed, 04 Aug 2021 06:34:37 +0200, Oleksij Rempel wrote:
> Add "skov" entry for the SKOV A/S: https://www.skov.com/en/
>
> Signed-off-by: Oleksij Rempel
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring
On Tue, Aug 10, 2021 at 10:53:37AM +0200, Daniel Vetter wrote:
> On Mon, Aug 09, 2021 at 06:58:23PM +, Matthew Brost wrote:
> > On Mon, Aug 09, 2021 at 05:17:34PM +0200, Daniel Vetter wrote:
> > > On Tue, Aug 03, 2021 at 03:29:13PM -0700, Matthew Brost wrote:
> > > > Implement GuC parent-child
On Tue, Aug 10, 2021 at 11:07:55AM +0200, Daniel Vetter wrote:
> On Tue, Aug 10, 2021 at 10:53:37AM +0200, Daniel Vetter wrote:
> > On Mon, Aug 09, 2021 at 06:58:23PM +, Matthew Brost wrote:
> > > On Mon, Aug 09, 2021 at 05:17:34PM +0200, Daniel Vetter wrote:
> > > > On Tue, Aug 03, 2021 at
w100fb_probe() did not reset the global state to its initial state. This
can result in invocation of iounmap() even when there was not the
appropriate successful call of ioremap(). For instance, this may be the
case if first probe fails after two successful ioremap() while second
probe fails when
Hello,
I have nightly tests that run on VM's against our btrfs devel tree, and I'm
getting this warning every day
[15522.437976] [ cut here ]
[15522.438356] WARNING: CPU: 0 PID: 2334448 at drivers/gpu/drm/ttm/ttm_bo.c:512
ttm_bo_release+0x4f9/0x5c0 [ttm]
On Tue, Aug 10, 2021 at 08:53:16AM +0200, Daniel Vetter wrote:
> On Mon, Aug 09, 2021 at 06:37:01PM +, Matthew Brost wrote:
> > On Mon, Aug 09, 2021 at 04:30:06PM +0200, Daniel Vetter wrote:
> > > On Tue, Aug 03, 2021 at 03:29:11PM -0700, Matthew Brost wrote:
> > > > Expose logical engine
From: Mark Yacoub
[Why]
Userspace should get back a copy of the request that's been modified
even when drm_wait_vblank_ioctl returns a failure.
Rationale:
drm_wait_vblank_ioctl modifies the request and expects the user to read
back. When the type is RELATIVE, it modifies it to ABSOLUTE and
Quoting Akhil P Oommen (2021-08-11 07:23:54)
> Add the necessary dt nodes for gpu support in sc7280.
>
> Signed-off-by: Akhil P Oommen
> ---
Reviewed-by: Stephen Boyd
On Tue, Aug 10, 2021 at 08:47:10AM +0200, Daniel Vetter wrote:
> On Mon, Aug 09, 2021 at 06:20:51PM +, Matthew Brost wrote:
> > On Mon, Aug 09, 2021 at 04:27:01PM +0200, Daniel Vetter wrote:
> > > On Tue, Aug 03, 2021 at 03:29:08PM -0700, Matthew Brost wrote:
> > > > Calling
On Wed, Aug 11, 2021 at 11:55:48AM +0200, Daniel Vetter wrote:
> On Mon, Aug 09, 2021 at 07:32:26PM +, Matthew Brost wrote:
> > On Mon, Aug 09, 2021 at 07:17:27PM +0200, Daniel Vetter wrote:
> > > On Tue, Aug 03, 2021 at 03:29:43PM -0700, Matthew Brost wrote:
> > > > Some workloads use lots of
On Wed, Aug 11, 2021 at 12:04:04PM +0200, Daniel Vetter wrote:
> On Tue, Aug 10, 2021 at 05:29:46PM +, Matthew Brost wrote:
> > On Tue, Aug 10, 2021 at 11:27:31AM +0200, Daniel Vetter wrote:
> > > On Tue, Aug 10, 2021 at 11:23:39AM +0200, Daniel Vetter wrote:
> > > > On Mon, Aug 09, 2021 at
On Wed, Aug 11, 2021 at 12:30:52PM +0200, Daniel Vetter wrote:
> On Wed, Aug 11, 2021 at 01:16:14AM +, Matthew Brost wrote:
> > Prior to this patch the blocked context counter was cleared on
> > init_sched_state (used during registering a context & resets) which is
> > incorrect. This state
Attach a top-level bridge to each encoder, which will be used for
negociating the bus format and flags.
All the bridges are now attached with DRM_BRIDGE_ATTACH_NO_CONNECTOR.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 92 +--
1 file changed,
When using C8 color mode, make sure that the palette is always uploaded
before a frame; otherwise the very first frame will have wrong colors.
Do that by changing the link order of the DMA descriptors.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 53
Setting the DMA descriptor chain register in the probe function has been
fine until now, because we only ever had one descriptor per foreground.
As the driver will soon have real descriptor chains, and the DMA
descriptor chain register updates itself to point to the current
descriptor being
The IPU scaling information is computed in the plane's ".atomic_check"
callback, and used in the ".atomic_update" callback. As such, it is
state-specific, and should be moved to a private state structure.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-ipu.c | 73
Until now, the ingenic-drm as well as the ingenic-ipu drivers used to
put state-specific information in their respective private structure.
Add boilerplate code to support private objects in the two drivers, so
that state-specific information can be put in the state-specific private
structure.
Instead of having one 'hwdesc' variable for the plane #0, one for the
plane #1 and one for the palette, use a 'hwdesc[3]' array, where the
DMA hardware descriptors are indexed by the plane's number.
v2: dma_hwdesc_addr() extended to support palette hwdesc. The palette
hwdesc is now hwdesc[3]
Hi,
A V2 of my patchset for the ingenic-drm driver.
The patches "drm/ingenic: Remove dead code" and
"drm/ingenic: Use standard drm_atomic_helper_commit_tail"
that were present in V1 have been merged in drm-misc-next,
so they are not in this V2.
Changelog:
[PATCH 1/6]:
dma_hwdesc_addr()
From: Michel Dänzer
In contrast to schedule_delayed_work, this pushes back the work if it
was already scheduled before. Specific behaviour change:
Before:
The scheduled work ran ~1 second after the first time ring_end_use was
called, even if the ring was used again during that second.
After:
From: Michel Dänzer
In contrast to schedule_delayed_work, this pushes back the work if it
was already scheduled before. Specific behaviour change:
Before:
amdgpu_device_delay_enable_gfx_off ran ~100 ms after the first time
GFXOFF was disabled and re-enabled, even if GFXOFF was disabled and
Reduce link rate and re start link training if link training 1
failed due to loss of clock recovery done to fix Link Layer
CTS case 4.3.1.7. Also only update voltage and pre-emphasis
swing level after link training started to fix Link Layer CTS
case 4.3.1.6.
Changes in V2:
-- replaced cr_status
Response with correct edid checksum saved at connector after corrupted edid
checksum read. This fixes Link Layer CTS cases 4.2.2.3, 4.2.2.6.
Signed-off-by: Kuogee Hsieh
Reviewed-by: Stephen Boyd
---
drivers/gpu/drm/msm/dp/dp_panel.c | 9 +++--
1 file changed, 7 insertions(+), 2
Initialize both pre-emphasis and voltage swing level to 0 before
start link training and do not end link training until video is
ready to reduce the period between end of link training and video
start to meet Link Layer CTS requirement. Some dongle main link
symbol may become unlocked again if
DP cable should always connect to DPU during the entire PHY compliance
testing run. Since DP PHY compliance test is executed at irq_hpd event
context, dp_ctrl_off_link_stream() should be used instead of dp_ctrl_off().
dp_ctrl_off() is used for unplug event which is triggered when DP cable is
dis
Aux hardware calibration sequence requires resetting the aux controller
in order for the new setting to take effect. However resetting the AUX
controller will also clear HPD interrupt status which may accidentally
cause pending unplug interrupt to get lost. Therefore reset aux
controller only when
drm/msm/dp: add fixes to pass DP Link Layer compliance test cases
Kuogee Hsieh (6):
drm/msm/dp: use dp_ctrl_off_link_stream during PHY compliance test run
drm/msm/dp: reduce link rate if failed at link training 1
drm/msm/dp: reset aux controller after dp_aux_cmd_fifo_tx() failed.
Remove special handling of replug interrupt and instead treat replug event
as a sequential unplug followed by a plugin event. This is needed to meet
the requirements of DP Link Layer CTS test case 4.2.1.3.
Changes in V2:
-- add fixes statement
Changes in V3:
-- delete EV_HPD_REPLUG_INT
Fixes:
Hi CK,
On Mon, 2021-08-09 at 22:34 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
>
> jason-jh.lin 於 2021年8月6日 週五 上午4:52寫道：
> >
> > 1. Adjust to the alphabetic order for the define, function, struct
> >and array in mediatek-drm driver
> > 2. Remove the unsed define in mtk_drm_ddp_comp.c
>
>
Hi CK,
On Sat, 2021-08-07 at 00:44 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
>
> jason-jh.lin 於 2021年8月6日 週五 上午4:52寫道：
> >
> > DSC is designed for real-time systems with real-time compression,
> > transmission, decompression and display.
> > The DSC standard is a specification of the algorithms
On Wed, Aug 11, 2021 at 5:15 AM Laurent Pinchart
wrote:
>
> Hi Stephen,
>
> On Tue, Aug 10, 2021 at 10:26:33PM -0700, Stephen Boyd wrote:
> > Quoting Laurent Pinchart (2021-06-23 17:03:02)
> > > To simplify interfacing with the panel, wrap it in a panel-bridge and
> > > let the DRM bridge helpers
On Sat, 2021-08-07 at 01:10 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
>
> jason-jh.lin 於 2021年8月6日 週五 上午4:52寫道：
> >
> > Add MERGE engine file:
> > MERGE module is used to merge two slice-per-line inputs
> > into one side-by-side output.
> >
> > Signed-off-by: jason-jh.lin
> > ---
> > This
Hi Matthias,
On Fri, 2021-08-06 at 13:28 +0200, Matthias Brugger wrote:
> Hi Jason,
>
> On 05/08/2021 22:52, jason-jh.lin wrote:
> > Add mt8195 vdosys0 clock driver name and routing table to
> > the driver data of mtk-mmsys.
> >
>
> I'd like to see the implementation of vdosys1 as well, to
On 8/11/21 7:19 AM, Kirill A. Shutemov wrote:
> On Tue, Aug 10, 2021 at 02:48:54PM -0500, Tom Lendacky wrote:
>> On 8/10/21 1:45 PM, Kuppuswamy, Sathyanarayanan wrote:
>>>
>>>
>>> On 7/27/21 3:26 PM, Tom Lendacky wrote:
diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
On 8/11/21 9:53 AM, Kuppuswamy, Sathyanarayanan wrote:
> On 7/27/21 3:26 PM, Tom Lendacky wrote:
>> diff --git a/include/linux/protected_guest.h
>> b/include/linux/protected_guest.h
>> new file mode 100644
>> index ..f8ed7b72967b
>> --- /dev/null
>> +++
On Wed, Aug 11, 2021 at 11:48:00AM +0200, Daniel Vetter wrote:
> On Wed, Aug 11, 2021 at 10:16:41AM +0300, Jani Nikula wrote:
> > On Tue, 10 Aug 2021, Daniel Vetter wrote:
> > > On Mon, Aug 09, 2021 at 09:19:39AM -0700, Matt Roper wrote:
> > >> On Mon, Aug 09, 2021 at 04:05:59PM +0200, Daniel
When going idle, it's not unlikely that more work will follow.
As such, use autosuspend with a 500ms suspend delay.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/vic.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/tegra/vic.c b/drivers/gpu/drm/tegra/vic.c
On 7/27/21 3:26 PM, Tom Lendacky wrote:
diff --git a/include/linux/protected_guest.h b/include/linux/protected_guest.h
new file mode 100644
index ..f8ed7b72967b
--- /dev/null
+++ b/include/linux/protected_guest.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+
Here's the v3 of the NVDEC support series, containing minor fixes
compared to v2.
NVDEC hardware documentation can be found at
https://github.com/NVIDIA/open-gpu-doc/tree/master/classes/video
and example userspace can be found at
https://github.com/cyndis/vaapi-tegra-driver
Thanks,
Mikko
Mikko
Add support for booting and using NVDEC on Tegra210, Tegra186
and Tegra194 to the Host1x and TegraDRM drivers. Booting in
secure mode is not currently supported.
Signed-off-by: Mikko Perttunen
---
v3:
* Change num_instances to unsigned int
* Remove unnecessary '= 0' initializer
* Populate
Add YAML device tree bindings for NVDEC, now in a more appropriate
place compared to the old textual Host1x bindings.
Signed-off-by: Mikko Perttunen
---
v3:
* Drop host1x bindings
* Change read2 to read-1 in interconnect names
v2:
* Fix issues pointed out in v1
* Add T194 nvidia,instance
Add a device tree node for NVDEC on Tegra186, and
device tree nodes for NVDEC and NVDEC1 on Tegra194.
Signed-off-by: Mikko Perttunen
---
v3:
* Change read2 to read-1
v2:
* Add NVDECSRD1 memory client
* Add also to T194 (both NVDEC0/1)
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 16
From: Manaf Meethalavalappu Pallikunhi
Add cooling-cells property and the cooling maps for the gpu thermal
zones to support GPU thermal cooling.
Signed-off-by: Manaf Meethalavalappu Pallikunhi
Signed-off-by: Akhil P Oommen
Reviewed-by: Stephen Boyd
---
(no changes since v1)
Add the necessary dt nodes for gpu support in sc7280.
Signed-off-by: Akhil P Oommen
---
Changes in v5:
- Added Stephen's reviewed-by tag to patch-2
Changes in v4:
- Removed the dependency on gpucc bindings (Stephen)
- Reordered GPU's opp table
Changes in v3:
- Re-ordered the nodes based on
Add the necessary dt nodes for gpu support in sc7280.
Signed-off-by: Akhil P Oommen
---
Changes in v4:
- Removed the dependency on gpucc bindings (Stephen)
- Reordered GPU's opp table
Changes in v3:
- Re-ordered the nodes based on address (Stephen)
- Added the patch for gpu cooling to the
From: Manaf Meethalavalappu Pallikunhi
Add cooling-cells property and the cooling maps for the gpu thermal
zones to support GPU thermal cooling.
Signed-off-by: Manaf Meethalavalappu Pallikunhi
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
arch/arm64/boot/dts/qcom/sc7280.dtsi | 29
On Wed, Aug 11, 2021 at 10:16:41AM +0300, Jani Nikula wrote:
> On Tue, 10 Aug 2021, Daniel Vetter wrote:
> > On Mon, Aug 09, 2021 at 09:19:39AM -0700, Matt Roper wrote:
> >> On Mon, Aug 09, 2021 at 04:05:59PM +0200, Daniel Vetter wrote:
> >> > On Fri, Aug 06, 2021 at 09:36:56AM +0300, Joonas
On Tue, Aug 10, 2021 at 02:48:54PM -0500, Tom Lendacky wrote:
> On 8/10/21 1:45 PM, Kuppuswamy, Sathyanarayanan wrote:
> >
> >
> > On 7/27/21 3:26 PM, Tom Lendacky wrote:
> >> diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
> >> index de01903c3735..cafed6456d45 100644
> >> ---
Hi Stephen,
On Tue, Aug 10, 2021 at 10:26:33PM -0700, Stephen Boyd wrote:
> Quoting Laurent Pinchart (2021-06-23 17:03:02)
> > To simplify interfacing with the panel, wrap it in a panel-bridge and
> > let the DRM bridge helpers handle chaining of operations.
> >
> > This also prepares for support
Hi
>On Wednesday, August 11th, 2021 at 11:43, Daniel Vetter
>wrote:
>
>> For wayland this is still in the works, so might be good if you check
>> there that your use-case is properly supported. Protocol MR is here:
>>
>>
The variable val is declared without initialization, and its address is
passed to amdgpu_i2c_get_byte(). In this function, the value of val is
accessed in:
DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
addr, *val);
Also, when amdgpu_i2c_get_byte() returns, val may remain uninitialized,
On Wed, 11 Aug 2021, Daniel Vetter wrote:
> On Wed, Aug 11, 2021 at 10:16:41AM +0300, Jani Nikula wrote:
>> On Tue, 10 Aug 2021, Daniel Vetter wrote:
>> > On Mon, Aug 09, 2021 at 09:19:39AM -0700, Matt Roper wrote:
>> >> On Mon, Aug 09, 2021 at 04:05:59PM +0200, Daniel Vetter wrote:
>> >> > On
On Thu, Aug 05 2021, Jason Gunthorpe wrote:
> Nothing uses this anymore, delete it.
>
> Signed-off-by: Yishai Hadas
> Reviewed-by: Christoph Hellwig
> Signed-off-by: Jason Gunthorpe
> ---
> drivers/vfio/mdev/vfio_mdev.c | 22 --
> drivers/vfio/vfio.c | 14
On Thu, Aug 05 2021, Jason Gunthorpe wrote:
> Like vfio_pci_dev_set_try_reset() this code wants to reset all of the
> devices in the "reset group" which is the same membership as the device
> set.
>
> Instead of trying to reconstruct the device set from the PCI list go
> directly from the device
On Wed, Aug 11, 2021 at 01:16:14AM +, Matthew Brost wrote:
> Prior to this patch the blocked context counter was cleared on
> init_sched_state (used during registering a context & resets) which is
> incorrect. This state needs to be persistent or the counter can read the
> incorrect value
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