2021年9月30日(木) 23:41 Daniel Vetter :
>
> On Wed, Sep 29, 2021 at 01:19:05PM +0900, Shunsuke Mie wrote:
> > Implement a ib device operation ‘reg_user_mr_dmabuf’. Generate a
> > rxe_map from the memory space linked the passed dma-buf.
> >
> > Signed-off-by: Shunsuke Mie
> > ---
> >
So, it means I need to make another commit?
Zhengkui
From: guozheng...@vivo.com On Behalf Of Christian K?nig
Sent: Thursday, September 30, 2021 7:56 PM
To: Guo Zhengkui ; Simon Ser
Cc: Deucher, Alexander ; Pan, Xinhui
; David Airlie ; Daniel Vetter
; Chen, Guchun ; Zhou, Peng Ju
; Zhang,
On Fri, Oct 1, 2021 at 12:55 AM Lucas De Marchi
wrote:
>
> On Thu, Sep 30, 2021 at 11:01:36PM +0900, Masahiro Yamada wrote:
> >On Thu, Sep 30, 2021 at 3:34 AM Lucas De Marchi
> > wrote:
> >>
> >> The check for config value doesn't really belong to i915_utils.h - we
> >> are trying to eliminate
On Tuesday, 14 September 2021 2:16:02 AM AEST Alex Sierra wrote:
> Device Public type uses device memory that is coherently accesible by
> the CPU. This could be shown as SP (special purpose) memory range
> at the BIOS-e820 memory enumeration. If no SP memory is supported in
> system, this could
The I915_TILING_* definitions in the uapi header are intended solely for
tiling modes that are visible to the old de-tiling fence ioctls. Since
modern hardware does not support de-tiling fences, we should not add new
definitions for new tiling types going forward. However we do want the
client
On Friday, 24 September 2021 1:52:47 AM AEST Sierra Guiza, Alejandro (Alex)
wrote:
>
> On 9/21/2021 12:14 AM, Alistair Popple wrote:
> > On Tuesday, 21 September 2021 6:05:30 AM AEST Sierra Guiza, Alejandro
> > (Alex) wrote:
> >> On 9/20/2021 3:53 AM, Alistair Popple wrote:
> >>> On Tuesday, 14
The following interfaces:
i915_wedged
i915_forcewake_user
i915_gem_interrupt
are dependent on gt values. Put them inside gt/ and drop the
"i915_" prefix name. This would be the new structure:
dri/0/gt
|
+-- forcewake_user
|
+-- interrupt_info
|
\-- reset
Signed-off-by: Andi
On Fri, Aug 20, 2021 at 03:44:43PM -0700, Matthew Brost wrote:
Did a review offline with John Harrison, adding notes for what we found.
> Allow multiple batch buffers to be submitted in a single execbuf IOCTL
> after a context has been configured with the 'set_parallel' extension.
> The number
> > > + /* Executable implies readable */
> > > + if ((args->flags & PANFROST_BO_NOREAD) &&
> > > + !(args->flags & PANFROST_BO_NOEXEC))
> > > + return -EINVAL;
> >
> > Generally, executable also implies not-writeable. Should we check that?
>
> We were allowing it until now, so
On Sun, Sep 26, 2021 at 10:10:05PM +0200, Michal Wajdeczko wrote:
> We assumed that for all modern GENs the PTEs and register space are
> split in the GTTMMADR BAR, but while it is true, we should rather use
> fixed offset as it is defined in the specification.
>
> Bspec: 4409, 4457, 4604, 11181,
https://bugzilla.kernel.org/show_bug.cgi?id=214587
--- Comment #1 from Lahfa Samy (s...@lahfa.xyz) ---
The computer did unfreeze then after the reset of the GPU but it seems hashcat
cannot use the GPU anymore for some reason, I'm not too sure why, but I think I
need to reboot my machine.
--
You
https://bugzilla.kernel.org/show_bug.cgi?id=214587
Bug ID: 214587
Summary: [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring gfx
timeout, signaled seq=5900910, emitted seq=5900912
Product: Drivers
Version: 2.5
Kernel Version:
On 9/29/21 10:05 PM, Bjorn Andersson wrote:
> The existing pxa driver and the upcoming addition of PWM support in the
> TI sn565dsi86 DSI/eDP bridge driver both has a single PWM channel and
> thereby a need for a of_xlate function with the period as its single
> argument.
>
> Introduce a common
Applied to drm-misc-next.
Thanks
On 09/28, Harry Wentland wrote:
> On 2021-09-27 15:23, Fangzhi Zuo wrote:
> > Include FEC, DSC, Link Training related headers.
> >
> > Change since v2
> > - Align with the spec for DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT
> >
> > Signed-off-by: Fangzhi Zuo
>
>
On Thu, Sep 30, 2021 at 4:35 PM wrote:
>
> From: Tom Rix
>
> When CONFIG_HSA_AMD=n this there is this error
> amdgpu_amdkfd.c:75:56: error: incompatible type for
> argument 2 of ‘kgd2kfd_probe’
>75 | adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev, vf);
>
> amdgpu_amdkfd.h:349:17:
From: Tom Rix
When CONFIG_HSA_AMD=n this there is this error
amdgpu_amdkfd.c:75:56: error: incompatible type for
argument 2 of ‘kgd2kfd_probe’
75 | adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev, vf);
amdgpu_amdkfd.h:349:17: note: declared here
349 | struct kfd_dev
Hi,
On 30/09/2021 20:49, Amit Pundir wrote:
On Thu, 30 Sept 2021 at 04:50, Rob Clark wrote:
On Wed, Sep 29, 2021 at 2:51 PM John Stultz wrote:
On Wed, Sep 29, 2021 at 2:32 PM John Stultz wrote:
On Wed, Sep 29, 2021 at 2:27 PM John Stultz wrote:
On Fri, Sep 10, 2021 at 3:12 AM Maxime
On Thu, 30 Sept 2021 at 04:50, Rob Clark wrote:
>
> On Wed, Sep 29, 2021 at 2:51 PM John Stultz wrote:
> >
> > On Wed, Sep 29, 2021 at 2:32 PM John Stultz wrote:
> > > On Wed, Sep 29, 2021 at 2:27 PM John Stultz
> > > wrote:
> > > > On Fri, Sep 10, 2021 at 3:12 AM Maxime Ripard wrote:
> > >
On Thu, 30 Sep 2021 20:47:23 +0200
Boris Brezillon wrote:
> So we can create GPU mappings without R/W permissions. Particularly
> useful to debug corruptions caused by out-of-bound writes.
Oops, I forgot to add the PANFROST_BO_PRIVATE flag suggested by Robin
here [1]. I'll send a v2.
On Thu, 30 Sep 2021 15:13:29 -0400
Alyssa Rosenzweig wrote:
> > + /* Executable implies readable */
> > + if ((args->flags & PANFROST_BO_NOREAD) &&
> > + !(args->flags & PANFROST_BO_NOEXEC))
> > + return -EINVAL;
>
> Generally, executable also implies not-writeable. Should
> + /* Executable implies readable */
> + if ((args->flags & PANFROST_BO_NOREAD) &&
> + !(args->flags & PANFROST_BO_NOEXEC))
> + return -EINVAL;
Generally, executable also implies not-writeable. Should we check that?
Jobs reading from the same BO should not be serialized. Add access
flags so we can relax the implicit dependencies in that case. We force
exclusive access for now to keep the behavior unchanged, but a new
SUBMIT ioctl taking explicit access flags will be introduced.
Signed-off-by: Boris Brezillon
This should help limit the number of ioctls when submitting multiple
jobs. The new ioctl also supports syncobj timelines and BO access flags.
v5:
* Fix typos
* Add BUILD_BUG_ON() checks to make sure SUBMIT_BATCH_VERSION and
descriptor sizes are synced
* Simplify error handling in
So we can re-use it from elsewhere.
Signed-off-by: Boris Brezillon
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_drv.c | 53 ++---
1 file changed, 29 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c
Now that we have a new SUBMIT ioctl dealing with timelined syncojbs we
can advertise the feature.
Signed-off-by: Boris Brezillon
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
Sometimes, all the user wants to do is add a synchronization point.
Userspace can already do that by submitting a NULL job, but this implies
submitting something to the GPU when we could simply skip the job and
signal the done fence directly.
v5:
* New patch
Signed-off-by: Boris Brezillon
---
Needed to keep VkQueues isolated from each other.
v4:
* Make panfrost_ioctl_create_submitqueue() return the queue ID
instead of a queue object
v3:
* Limit the number of submitqueue per context to 16
* Fix a deadlock
Signed-off-by: Boris Brezillon
Reviewed-by: Steven Price
---
We now have a new ioctl that allows submitting multiple jobs at once
(among other things) and we support timelined syncobjs. Bump the
minor version number to reflect those changes.
Signed-off-by: Boris Brezillon
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_drv.c | 3 +++
1
Hello,
I finally got to resubmitting a new version of this series. I think
I fixed all the issues reported by Steve and Daniel. Still no support
for {IN,OUT}_FENCE_FD, but that can be added later if we need it.
For those who didn't follow the previous iterations, this is an
attempt at providing
So we don't have to change the prototype if we extend the function.
v3:
* Fix subject
Signed-off-by: Boris Brezillon
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_job.c | 22 --
1 file changed, 8 insertions(+), 14 deletions(-)
diff --git
On Thu, Sep 30, 2021 at 7:06 PM Shunsuke Mie wrote:
>
> 2021年9月30日(木) 16:23 Zhu Yanjun :
> >
> > On Thu, Sep 30, 2021 at 2:58 PM Shunsuke Mie wrote:
> > >
> > > 2021年9月30日(木) 15:37 Zhu Yanjun :
> > > >
> > > > On Thu, Sep 30, 2021 at 2:20 PM Shunsuke Mie wrote:
> > > > >
> > > > > Implement a
Le 30/09/2021 à 16:21, Daniel Vetter a écrit :
On Sat, Sep 25, 2021 at 08:46:12PM +0800, Cai Huoqing wrote:
Replace direction definition PCI_DMA_BIDIRECTIONAL
with DMA_BIDIRECTIONAL, because it helps to enhance readability
and avoid possible inconsistency.
Signed-off-by: Cai Huoqing
Applied
On Thu, Sep 30, 2021 at 11:34 AM Daniel Vetter wrote:
>
> On Thu, Sep 30, 2021 at 8:20 PM Rob Clark wrote:
> >
> > From: Rob Clark
> >
> > In theory a context can be destroyed and a new one allocated at the same
> > address, making the pointer comparision to detect when we don't need to
> >
So we can create GPU mappings without R/W permissions. Particularly
useful to debug corruptions caused by out-of-bound writes.
Signed-off-by: Boris Brezillon
---
drivers/gpu/drm/panfrost/panfrost_drv.c | 14 --
drivers/gpu/drm/panfrost/panfrost_gem.c | 2 ++
On Thu, Sep 30, 2021 at 06:15:46PM +0100, Tvrtko Ursulin wrote:
> (Note I did not copy
> everyone on all patches but just the cover letter for context and the rest
> should be available from the mailing list.)
In general, if you can't be arsed to send it to me, I can't be arsed to
dig it
On Thu, Sep 30, 2021 at 8:20 PM Rob Clark wrote:
>
> From: Rob Clark
>
> In theory a context can be destroyed and a new one allocated at the same
> address, making the pointer comparision to detect when we don't need to
> update the current pagetables invalid. Instead assign a sequence number
>
On Thu, Sep 30, 2021 at 06:15:47PM +0100, Tvrtko Ursulin wrote:
> void set_user_nice(struct task_struct *p, long nice)
> {
> bool queued, running;
> - int old_prio;
> + int old_prio, ret;
> struct rq_flags rf;
> struct rq *rq;
>
> @@ -6913,6 +6945,9 @@ void
From: Rob Clark
In theory a context can be destroyed and a new one allocated at the same
address, making the pointer comparision to detect when we don't need to
update the current pagetables invalid. Instead assign a sequence number
to each context on creation, and use this for the check.
On Thu, Sep 30, 2021 at 12:02 PM Nathan Chancellor wrote:
>
> cc-ifversion only works for GCC, as clang pretends to be GCC 4.2.1 for
> glibc compatibility, which means IS_OLD_GCC will get set and unsupported
> flags will be passed to clang when building certain code within the DCN
> files:
>
>
On Thu, Sep 30, 2021 at 1:23 PM Nick Desaulniers
wrote:
>
> On Thu, Sep 30, 2021 at 10:10 AM Alex Deucher wrote:
> >
> > Applied. Thanks!
> >
> > Alex
> >
> > On Thu, Sep 30, 2021 at 12:23 PM Nathan Chancellor
> > wrote:
> > >
> > > Clang warns:
>
> Any chance AMDGPU folks can look into
Quoting mkri...@codeaurora.org (2021-09-30 04:56:59)
> On 2021-08-19 01:27, Stephen Boyd wrote:
> > Quoting Krishna Manikandan (2021-08-18 03:27:02)
> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >> index 53a21d0..fd7ff1c 100644
> >> ---
On Thu, 2021-09-30 at 15:46 +0200, Lukasz Majczak wrote:
> With patch "drm/i915/vbt: Fix backlight parsing for VBT 234+"
> the size of bdb_lfp_backlight_data structure has been increased,
> causing if-statement in the parse_lfp_backlight function
> that comapres this structure size to the one
On Thu, Sep 30, 2021 at 10:10 AM Alex Deucher wrote:
>
> Applied. Thanks!
>
> Alex
>
> On Thu, Sep 30, 2021 at 12:23 PM Nathan Chancellor wrote:
> >
> > Clang warns:
Any chance AMDGPU folks can look into adding clang to the CI roster?
--
Thanks,
~Nick Desaulniers
Applied. Thanks!
Alex
On Thu, Sep 30, 2021 at 12:16 PM Nathan Chancellor wrote:
>
> Clang warns:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_hwseq.c:505:6: error:
> variable 'remove_mpcc' is used uninitialized whenever 'if' condition is false
>
From: Tvrtko Ursulin
A simple hash table of registered clients indexed by the task struct
pointer is kept to be used in a following patch.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 ++
drivers/gpu/drm/i915/i915_drm_client.c | 31
From: Tvrtko Ursulin
We soon want to start answering questions like how much GPU time is the
context belonging to a client which exited still using.
To enable this we start tracking all context belonging to a client on a
separate list.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Aravind
From: Tvrtko Ursulin
Tracking DRM clients more explicitly will allow later patches to
accumulate past and current GPU usage in a centralised place and also
consolidate access to owning task pid/name.
Unique client id is also assigned for the purpose of distinguishing/
consolidating between
From: Tvrtko Ursulin
Implement a simple notifier chain via which interested parties can track
when process nice value changes. Simple because it is global so each user
would have to track which tasks it is interested in.
To use register_user_nice_notifier and unregister_user_nice_notifier
From: Tvrtko Ursulin
Make GEM contexts keep a reference to i915_drm_client for the whole of
of their lifetime which will come handy in following patches.
v2: Don't bother supporting selftests contexts from debugfs. (Chris)
v3 (Lucas): Finish constructing ctx before adding it to the list
v4
From: Tvrtko Ursulin
This is a somewhat early sketch of one of my ideas intended for early feedback
from the core scheduler experts. First and last two patches in the series are
the most interesting ones for people outside of i915. (Note I did not copy
everyone on all patches but just the cover
From: Tvrtko Ursulin
Introduce the concept of context nice value which exactly matches the
process nice, and also make use of the task user nice notifier chain to be
able to dynamically adjust GPU scheduling. Apart from runtime adjustments
context also inherits the nice value when created.
Applied. Thanks!
Alex
On Thu, Sep 30, 2021 at 12:23 PM Nathan Chancellor wrote:
>
> Clang warns:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:1017:10:
> error: expression which evaluates to zero treated as a null pointer constant
> of type 'struct pipe_ctx *'
On 7/27/21 6:13 PM, Marek Vasut wrote:
Decoder input LVDS format is a property of the decoder chip or even
its strapping. Handle data-mapping the same way lvds-panel does. In
case data-mapping is not present, do nothing, since there are still
legacy bindings which do not specify this property.
On 09/30, Melissa Wen wrote:
> On 09/30, Iago Toral wrote:
> > On Wed, 2021-09-29 at 10:45 +0100, Melissa Wen wrote:
> > > Using the generic extension from the previous patch, a specific
> > > multisync
> > > extension enables more than one in/out binary syncobj per job
> > > submission.
> > >
Clang warns:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:1017:10:
error: expression which evaluates to zero treated as a null pointer constant of
type 'struct pipe_ctx *' [-Werror,-Wnon-literal-null-conversion]
return false;
^
1
Using the generic extension from the previous patch, a specific multisync
extension enables more than one in/out binary syncobj per job submission.
Arrays of syncobjs are set in struct drm_v3d_multisync, that also cares
of determining the stage for sync (wait deps) according to the job
queue.
v2:
Add support to attach generic extensions on job submission. This patch
is third prep work to enable multiple syncobjs on job submission. With
this work, when the job submission interface needs to be extended to
accomodate a new feature, we will use a generic extension struct where
an id determines
Move job memory allocation to v3d_job_init function. This aim to facilitate
error handling in job initialization, since cleanup steps are similar for all
(struct v3d_job)-based types of job involved in a command submission. To
generalize v3d_job_init(), this change takes into account that all job
Clang warns:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_hwseq.c:505:6: error:
variable 'remove_mpcc' is used uninitialized whenever 'if' condition is false
[-Werror,-Wsometimes-uninitialized]
if (mpc->funcs->get_mpcc_for_dpp_from_secondary)
Prep work to enable a job to wait for more than one syncobj before
start. Also get rid of old checkpatch warnings in the v3d_gem file.
No functional changes.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/v3d/v3d_gem.c | 28 ++--
1 file changed, 18 insertions(+), 10
Currently, v3d only supports single in/out syncobj per submission (in
v3d_submit_cl, there are two in_sync, one for bin and another for render
job); however, Vulkan queue submit operations expect multiples wait and
signal semaphores. This series extends v3d interface and job dependency
operations
cc-ifversion only works for GCC, as clang pretends to be GCC 4.2.1 for
glibc compatibility, which means IS_OLD_GCC will get set and unsupported
flags will be passed to clang when building certain code within the DCN
files:
clang-14: error: unknown argument: '-mpreferred-stack-boundary=4'
make[5]:
On Thu, Sep 30, 2021 at 11:01:36PM +0900, Masahiro Yamada wrote:
On Thu, Sep 30, 2021 at 3:34 AM Lucas De Marchi
wrote:
The check for config value doesn't really belong to i915_utils.h - we
are trying to eliminate that utils helper and share them when possible
with other drivers and
Add mtk mutex support for MT8192 SoC.
Signed-off-by: Yongqiang Niu
Signed-off-by: Hsin-Yi Wang
Reviewed-by: CK Hu
---
drivers/soc/mediatek/mtk-mutex.c | 35
1 file changed, 35 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mutex.c
add support for mediatek SOC MT8192
Signed-off-by: Yongqiang Niu
Signed-off-by: Hsin-Yi Wang
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 6
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 20 +++
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6
This patch add component OVL_2L2
Signed-off-by: Yongqiang Niu
Reviewed-by: Chun-Kuang Hu
Signed-off-by: Hsin-Yi Wang
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
This patch add component POSTMASK.
Signed-off-by: Yongqiang Niu
Signed-off-by: Hsin-Yi Wang
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 102 ++--
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
2 files changed, 73 insertions(+), 30 deletions(-)
This patch add component RDMA4
Signed-off-by: Yongqiang Niu
Reviewed-by: Chun-Kuang Hu
Signed-off-by: Hsin-Yi Wang
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
base v5.15
Yongqiang Niu (5):
drm/mediatek: add component OVL_2L2
drm/mediatek: add component POSTMASK
drm/mediatek: add component RDMA4
soc: mediatek: add mtk mutex support for MT8192
drm/mediatek: add support for mediatek SOC MT8192
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 6
On Thu, Sep 30, 2021 at 01:46:21PM +0300, Jani Nikula wrote:
On Wed, 29 Sep 2021, Lucas De Marchi wrote:
It took me some time to understand the need for IS_ACTIVE and why we
couldn't use kconfig.h.
For anyone else wondering, the clues are in babaab2f4738 ("drm/i915:
Encapsulate kconfig
Hi,
On Wed, Sep 29, 2021 at 5:35 PM Philip Chen wrote:
>
> dp-aux-bus.yaml says we can list an eDP panel as a child of
> an eDP controller node to represent the fact that the panel
> is connected to the controller's DP AUX bus.
>
> Let's add it to the ps8640 bindings.
>
> Signed-off-by: Philip
On Thu, Sep 30, 2021 at 11:00:06AM +0100, Steven Price wrote:
On 29/09/2021 19:33, Lucas De Marchi wrote:
Like the IS_ENABLED() counterpart, we can make IS_CONFIG_NONZERO() to
return the right thing when the config is not defined rather than a
build error, with the limitation that it can't be
On Thu, 2021-09-23 at 20:50 +0200, Maxime Ripard wrote:
> Since commit 875a4d536842 ("drm/vc4: drv: Disable the CRTC at boot
> time"), during the initial setup of the driver we call into the VC4 HDMI
> controller hooks to make sure the controller is properly disabled.
>
> However, we were never
Hi,
On Wed, Sep 29, 2021 at 8:06 PM Bjorn Andersson
wrote:
>
> The multi-register u16 write operation can use regmap_bulk_write()
> instead of two separate regmap_write() calls.
>
> It's uncertain if this has any effect on the actual updates of the
> underlying registers, but this at least gives
Scroll acceleration is disabled in fbcon by hard-wiring
p->scrollmode = SCROLL_REDRAW. Remove the obsolete code in fbcon.c
and fbdev/core/
Signed-off-by: Claudio Suarez
---
- This is a task in the TODO list Documentation/gpu/todo.rst
- The contact in the task is Daniel Vetter. He is/you are in
Hi Chun-Kuang.
Thank you for your input.
I have tried to find commonalities between the two drivers but I didn't
find enough shared code to warrant that architecture.
I'll have another look, especially now that I'm more familiar with the
driver.
Regarding 2, I have removed as much
@Christian Koenig
Have you had a chance to look at this yet?
Alex
On Mon, Sep 20, 2021 at 4:44 AM Thomas Zimmermann wrote:
>
> Hi
>
> Am 20.09.21 um 10:41 schrieb Thomas Zimmermann:
> > (cc'ing dri-devel)
> >
> > Hi
> >
> > Am 13.09.21 um 16:36 schrieb Alex Deucher:
> >> On Thu, Sep 9, 2021 at
base v5.15
Yongqiang Niu (1):
drm/mediatek: add dither 6 setting
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 3 +++
1 file changed, 3 insertions(+)
--
2.25.1
dither 6 setting is missed in a6b7c98afdca
bit 1 is lfsr_en( "Enables LFSR-type dithering"), need enable
bit 2 is rdither_en(Enables running order dithering), need disable
Fixes: a6b7c98afdca(drm/mediatek: add mtk_dither_set_common())
Signed-off-by: Yongqiang Niu
Change-Id:
On Wed, Sep 29, 2021 at 04:07:01PM +0300, Pekka Paalanen wrote:
> On Wed, 29 Sep 2021 09:54:14 +
> Simon Ser wrote:
>
> > When a plane is missing the "alpha blend mode" property, KMS drivers
> > will use the pre-multiplied mode.
> >
> > Signed-off-by: Simon Ser
> > Cc: Daniel Vetter
> >
On Wed, Sep 29, 2021 at 01:19:05PM +0900, Shunsuke Mie wrote:
> Implement a ib device operation ‘reg_user_mr_dmabuf’. Generate a
> rxe_map from the memory space linked the passed dma-buf.
>
> Signed-off-by: Shunsuke Mie
> ---
> drivers/infiniband/sw/rxe/rxe_loc.h | 2 +
>
On Wed, Sep 29, 2021 at 01:32:41AM +0300, Jani Nikula wrote:
> If drm_modeset_lock() returns -EDEADLK, the caller is supposed to drop
> all currently held locks using drm_modeset_backoff(). Failing to do so
> will result in warnings and backtraces on the paths trying to lock a
> contended lock.
On Mon, Sep 27, 2021 at 09:23:45AM -0700, Kees Cook wrote:
> On Mon, Sep 27, 2021 at 04:28:02PM +0200, Arnd Bergmann wrote:
> > From: Arnd Bergmann
> >
> > With CONFIG_FB=m and CONFIG_DRM=y, we get a link error in the fb helper:
> >
> > aarch64-linux-ld: drivers/gpu/drm/drm_fb_helper.o: in
On Sat, Sep 25, 2021 at 08:46:12PM +0800, Cai Huoqing wrote:
> Replace direction definition PCI_DMA_BIDIRECTIONAL
> with DMA_BIDIRECTIONAL, because it helps to enhance readability
> and avoid possible inconsistency.
>
> Signed-off-by: Cai Huoqing
Applied to drm-intel-gt-next, thanks for the
On Tue, Sep 21, 2021 at 10:21:02PM +0100, Mark Brown wrote:
> The gbefb driver not only registers a driver but also the device for that
> driver. This is all well and good when run on the IP32 machines that are
> supported by the driver but since the driver supports building with
> COMPILE_TEST we
On Thu, Sep 30, 2021 at 01:32:28PM +0200, Christian König wrote:
> Am 30.09.21 um 12:26 schrieb Daniel Vetter:
> > On Thu, Sep 30, 2021 at 11:48:42AM +0200, Christian König wrote:
> > >
> > > Am 30.09.21 um 11:00 schrieb Daniel Vetter:
> > > > On Wed, Sep 22, 2021 at 01:08:44PM +0200, Christian
30.09.2021 17:06, Peter Chen пишет:
> On 21-09-27 01:40:39, Dmitry Osipenko wrote:
>> The Tegra USB controller belongs to the core power domain and we're going
>> to enable GENPD support for the core domain. Now USB controller must be
>> resumed using runtime PM API in order to initialize the USB
On 21-09-27 01:40:39, Dmitry Osipenko wrote:
> The Tegra USB controller belongs to the core power domain and we're going
> to enable GENPD support for the core domain. Now USB controller must be
> resumed using runtime PM API in order to initialize the USB power state.
> We already support runtime
On Thu, Sep 30, 2021 at 3:34 AM Lucas De Marchi
wrote:
>
> The check for config value doesn't really belong to i915_utils.h - we
> are trying to eliminate that utils helper and share them when possible
> with other drivers and subsystems.
>
> Rationale for having such macro is in commit
>
On Tue, 28 Sep 2021 20:13:33 +0200, Maxime Ripard wrote:
> If CONFIG_OF is disabled, devm_drm_of_get_bridge won't be compiled in
> and drivers using that function will fail to build.
>
> Add an inline stub so that we can still build-test those cases.
>
>
Applied to drm/drm-misc
Do not cache hw_pipe's sblk in dpu_plane. Use
pdpu->pipe_hw->cap->sblk directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 25 ---
1 file changed, 8 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
LUT levels are setup outside of setup_qos_ctrl, so remove them from the
struct dpu_hw_pipe_qos_cfg.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 15 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 16 ++--
Remove struct dpu_hw_pipe_cdp_cfg instance from dpu_plane, it is an
interim configuration structure. Allocate it on stack instead.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 14 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 2 --
2 files
Do not cache hw_pipe's features in dpu_plane. Use
pdpu->pipe_hw->cap->features directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
In preparations of virtualizing the dpu_plane rip out debugfs support
from dpu_plane (as it is mostly used to expose plane's pipe registers).
Also move disable_danger file to danger/ debugfs subdir where it belongs.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |
struct dpu_hw_pipe_cfg represents an interim state during atomic
update/color fill, so move it out of struct dpu_plane.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 104 --
1 file changed, 57 insertions(+), 47 deletions(-)
diff --git
The pipe_qos_cfg is used only in _dpu_plane_set_qos_ctrl(), so remove it
from the dpu_plane struct and allocate it on stack when necessary.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 30 ---
1 file changed, 16 insertions(+), 14
This is a cleanup part of the DPU multirect patchset [1], split away to
ease review and merging per Abhinav's request.
Currently significant part of atomic plane state is stored in the
drm_plane's subclass rather than drm_plane_state's subclass. Move it
either to the drm_plane_state or even to
Scaler and pixel_ext configuration does not contain a long living state,
it is used only during plane update, so remove these two fiels from
dpu_plane_state and allocate them on stack.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 59 ++-
Simplify code surrounding CSC table setup by removing struct dpu_csc_cfg
pointer from dpu_plane and getting it directly at the CSC setup time.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 2 +-
1 - 100 of 175 matches
Mail list logo
