On Thu, Oct 7, 2021 at 5:27 PM Andi Shyti wrote:
>
> From: Andi Shyti
>
> The following interfaces:
>
> i915_wedged
> i915_forcewake_user
> i915_gem_interrupt
>
> are dependent on gt values. Put them inside gt/ and drop the
> "i915_" prefix name. This would be the new structure:
>
> dri/0
Hi, Christian,
On Thu, 2021-10-07 at 16:57 +0200, Christian König wrote:
> Am 07.10.21 um 15:26 schrieb Thomas Hellström:
> > While the range notifier is executing, we have the write-side mmu
> > interval
> > seqlock, and mmu_interval_read_retry() is always returning true,
> > which means that if
Am 08.10.21 um 08:29 schrieb guangming@mediatek.com:
From: Guangming Cao
Because dma-buf.name can be freed in func: "dma_buf_set_name",
so, we need to acquire lock first before we read/write dma_buf.name
to prevent Use After Free(UAF) issue.
Signed-off-by: Guangming Cao
---
drivers/dma-
From: Guangming Cao
Because dma-buf.name can be freed in func: "dma_buf_set_name",
so, we need to acquire lock first before we read/write dma_buf.name
to prevent Use After Free(UAF) issue.
Signed-off-by: Guangming Cao
---
drivers/dma-buf/dma-buf.c | 5 +
1 file changed, 5 insertions(+)
di
From: Guangming Cao
Because dma-buf.name can be freed in func: "dma_buf_set_name",
so, we need to acquire lock first before we read/write dma_buf.name
to prevent Use After Free(UAF) issue.
Signed-off-by: Guangming Cao
---
drivers/dma-buf/dma-buf.c | 5 +
1 file changed, 5 insertions(+)
di
From: Andi Shyti
The following interfaces:
i915_wedged
i915_forcewake_user
i915_gem_interrupt
are dependent on gt values. Put them inside gt/ and drop the
"i915_" prefix name. This would be the new structure:
dri/0/gt
|
+-- forcewake_user
|
+-- interrupt_info
|
\-- reset
F
Hi Linus,
I've returned from my tropical island retreat, even managed to bring
one of my kids on a dive with some turtles. Thanks to Daniel for doing
last week's work.
Otherwise this is the weekly fixes pull, it's a bit bigger because the
vc4 reverts in your tree caused some problems with fixes i
On Fri, 2021-10-01 at 13:00 +0200, Dafna Hirschfeld wrote:
>
> On 30.09.21 17:52, Yongqiang Niu wrote:
> > This patch add component POSTMASK.
> >
> > Signed-off-by: Yongqiang Niu
> > Signed-off-by: Hsin-Yi Wang
> > Reviewed-by: CK Hu
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |
mt8192 has different routing registers than mt8183
Signed-off-by: Yongqiang Niu
Reviewed-by: Enric Balletbo i Serra
---
drivers/soc/mediatek/mt8192-mmsys.h | 77 +
drivers/soc/mediatek/mtk-mmsys.c| 11 +
2 files changed, 88 insertions(+)
create mode 100644 d
This patch add some more ddp component
OVL_2L2 is ovl which include 2 layers overlay
POSTMASK control round corner for display frame
RDMA4 read dma buffer
Signed-off-by: Yongqiang Niu
Reviewed-by: Chun-Kuang Hu
Reviewed-by: Enric Balletbo i Serra
Signed-off-by: Yongqiang Niu
---
include/linux
base v5.15
Yongqiang Niu (2):
soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4
soc: mediatek: mmsys: Add mt8192 mmsys routing table
drivers/soc/mediatek/mt8192-mmsys.h| 77 ++
drivers/soc/mediatek/mtk-mmsys.c | 11
include/linux/soc/mediatek/mtk-mm
mt8192 has different routing registers than mt8183
Signed-off-by: Yongqiang Niu
Reviewed-by: Enric Balletbo i Serra
---
drivers/soc/mediatek/mt8192-mmsys.h | 77 +
drivers/soc/mediatek/mtk-mmsys.c| 11 +
2 files changed, 88 insertions(+)
create mode 100644 d
This patch add some more ddp component
OVL_2L2 is ovl which include 2 layers overlay
POSTMASK control round corner for display frame
RDMA4 read dma buffer
Signed-off-by: Yongqiang Niu
Reviewed-by: Chun-Kuang Hu
Reviewed-by: Enric Balletbo i Serra
Signed-off-by: Yongqiang Niu
---
include/linux
base v5.15
Yongqiang Niu (2):
soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4
soc: mediatek: mmsys: Add mt8192 mmsys routing table
drivers/soc/mediatek/mt8192-mmsys.h| 77 ++
drivers/soc/mediatek/mtk-mmsys.c | 11
include/linux/soc/mediatek/mtk-mm
On Tue, 2021-10-05 at 07:41 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
>
> Yongqiang Niu 於 2021年9月30日 週四 下午9:18寫道：
> >
> > add time-out cycle setting to make sure time-out interrupt irq
> > will happened when instruction time-out for wait and poll
> >
> > Signed-off-by: Yongqiang Niu
> > ---
Quoting Saravana Kannan (2021-10-07 18:32:20)
> On Thu, Oct 7, 2021 at 6:24 PM Stephen Boyd wrote:
> >
> > Anyway, I think we still have to do a rescan so that we can try to bind
> > the aggregate device. Is there a better API to use for that?
>
> If you know the exact device, you could call devic
On Thu, Oct 07, 2021 at 12:50:28PM -0700, John Harrison wrote:
> On 10/4/2021 15:06, Matthew Brost wrote:
> > Add multi-lrc context registration H2G. In addition a workqueue and
> > process descriptor are setup during multi-lrc context registration as
> > these data structures are needed for multi-
On Wed, Oct 06, 2021 at 08:37:03PM -0700, John Harrison wrote:
> On 10/4/2021 15:06, Matthew Brost wrote:
> > Taking a PM reference to prevent intel_gt_wait_for_idle from short
> > circuiting while a deregister context H2G is in flight. To do this must
> > issue the deregister H2G from a worker as
On Thu, Oct 07, 2021 at 11:15:51AM -0700, John Harrison wrote:
> On 10/7/2021 08:19, Matthew Brost wrote:
> > On Wed, Oct 06, 2021 at 08:45:42PM -0700, John Harrison wrote:
> > > On 10/4/2021 15:06, Matthew Brost wrote:
> > > > Taking a PM reference to prevent intel_gt_wait_for_idle from short
> >
On Thu, Oct 07, 2021 at 03:03:04PM -0700, John Harrison wrote:
> On 10/4/2021 15:06, Matthew Brost wrote:
> > Assign contexts in parent-child relationship consecutive guc_ids. This
> > is accomplished by partitioning guc_id space between ones that need to
> > be consecutive (1/16 available guc_ids)
Quoting Saravana Kannan (2021-10-07 18:10:24)
> On Thu, Oct 7, 2021 at 1:11 PM Stephen Boyd wrote:
> >
> > Quoting Stephen Boyd (2021-10-07 11:40:07)
> > > Quoting Saravana Kannan (2021-10-06 20:07:11)
> > > > On Wed, Oct 6, 2021 at 12:38 PM Stephen Boyd
> > > > wrote:
> > > > > diff --git a/dri
On Thu, Oct 7, 2021 at 1:11 PM Stephen Boyd wrote:
>
> Quoting Stephen Boyd (2021-10-07 11:40:07)
> > Quoting Saravana Kannan (2021-10-06 20:07:11)
> > > On Wed, Oct 6, 2021 at 12:38 PM Stephen Boyd wrote:
> > > > diff --git a/drivers/base/component.c b/drivers/base/component.c
> > > > index 0a41
On 10/7/2021 08:19, Matthew Brost wrote:
On Wed, Oct 06, 2021 at 08:45:42PM -0700, John Harrison wrote:
On 10/4/2021 15:06, Matthew Brost wrote:
Taking a PM reference to prevent intel_gt_wait_for_idle from short
circuiting while a scheduling of user context could be enabled.
I'm not sure what
On Fri, 8 Oct 2021 at 07:46, Karol Herbst wrote:
>
> Reviewed-by: Karol Herbst
Reviewed-by: Ben Skeggs
>
> I haven't checked if other places need fixing up yet, and I still want
> to test this patch, but I won't get to it until Monday. But if
> everything is in place we can get this pushed next
This reverts commit f4be17cd5b14dd73545b0e014a63ebe9ab5ef837.
Commit c1ec54b7b5af
("drm/mediatek: Use mailbox rx_callback instead of cmdq_task_cb")
would cause numerous mtk cmdq mailbox driver warning:
WARNING: CPU: 0 PID: 0 at drivers/mailbox/mtk-cmdq-mailbox.c:198
cmdq_task_exec_done+0xb8/0xe0
This reverts commit c1ec54b7b5af25c779192253f5a9f05e95cb43d7.
Commit c1ec54b7b5af
("drm/mediatek: Use mailbox rx_callback instead of cmdq_task_cb")
would cause numerous mtk cmdq mailbox driver warning:
WARNING: CPU: 0 PID: 0 at drivers/mailbox/mtk-cmdq-mailbox.c:198
cmdq_task_exec_done+0xb8/0xe0
This reverts commit 8cdcb365342402fdeb664479b0a04e9debef8efb.
Commit c1ec54b7b5af
("drm/mediatek: Use mailbox rx_callback instead of cmdq_task_cb")
would cause numerous mtk cmdq mailbox driver warning:
WARNING: CPU: 0 PID: 0 at drivers/mailbox/mtk-cmdq-mailbox.c:198
cmdq_task_exec_done+0xb8/0xe0
This reverts commit bc9241be73d9b2b3bcb7033598521fd669639848.
Commit c1ec54b7b5af
("drm/mediatek: Use mailbox rx_callback instead of cmdq_task_cb")
would cause numerous mtk cmdq mailbox driver warning:
WARNING: CPU: 0 PID: 0 at drivers/mailbox/mtk-cmdq-mailbox.c:198
cmdq_task_exec_done+0xb8/0xe0
This reverts commit 9efb16c2fdd647d3888fd8dae84509f485cd554e.
Commit c1ec54b7b5af
("drm/mediatek: Use mailbox rx_callback instead of cmdq_task_cb")
would cause numerous mtk cmdq mailbox driver warning:
WARNING: CPU: 0 PID: 0 at drivers/mailbox/mtk-cmdq-mailbox.c:198
cmdq_task_exec_done+0xb8/0xe0
Commit c1ec54b7b5af
("drm/mediatek: Use mailbox rx_callback instead of cmdq_task_cb")
would cause numerous mtk cmdq mailbox driver warning:
WARNING: CPU: 0 PID: 0 at drivers/mailbox/mtk-cmdq-mailbox.c:198
cmdq_task_exec_done+0xb8/0xe0
So revert that patch and all the patches depend on that patch.
On Tue, Oct 05, 2021 at 04:14:23PM -0700, Matthew Brost wrote:
On Tue, Oct 05, 2021 at 10:47:11AM -0700, Umesh Nerlige Ramappa wrote:
With GuC handling scheduling, i915 is not aware of the time that a
context is scheduled in and out of the engine. Since i915 pmu relies on
this info to provide en
With GuC handling scheduling, i915 is not aware of the time that a
context is scheduled in and out of the engine. Since i915 pmu relies on
this info to provide engine busyness to the user, GuC shares this info
with i915 for all engines using shared memory. For each engine, this
info contains:
- to
In preparation for GuC pmu stats, add a name to the execlists stats
structure so that it can be differentiated from the GuC stats.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 14 +++---
drivers/gpu/drm/i915/gt/intel_engine_stats.h | 33 +++--
d
Quoting khs...@codeaurora.org (2021-10-07 13:28:12)
> On 2021-10-07 13:06, Bjorn Andersson wrote:
> > On Thu 07 Oct 12:51 PDT 2021, khs...@codeaurora.org wrote:
> >
> >> On 2021-10-06 10:31, Bjorn Andersson wrote:
> >> > On Wed 06 Oct 08:37 PDT 2021, khs...@codeaurora.org wrote:
> >> >
> >> > > On
Hi Bjorn and Stephen
On 2021-10-06 13:39, Bjorn Andersson wrote:
On Wed 06 Oct 11:59 PDT 2021, Stephen Boyd wrote:
Quoting Bjorn Andersson (2021-10-06 11:05:09)
> On Wed 06 Oct 10:19 PDT 2021, Stephen Boyd wrote:
>
> > Quoting Bjorn Andersson (2021-10-06 10:07:17)
> > > On Tue 05 Oct 21:26 PDT
On 10/4/2021 15:06, Matthew Brost wrote:
Assign contexts in parent-child relationship consecutive guc_ids. This
is accomplished by partitioning guc_id space between ones that need to
be consecutive (1/16 available guc_ids) and ones that do not (15/16 of
available guc_ids). The consecutive search
Reviewed-by: Karol Herbst
I haven't checked if other places need fixing up yet, and I still want
to test this patch, but I won't get to it until Monday. But if
everything is in place we can get this pushed next week so we can
finally fix this annoying issue :) I was also seeing some minor
graphic
Commit 64f7c698bea9 ("drm/nouveau/fifo: add engine_id hook") replaced
fifo/chang84.c g84_fifo_chan_engine() call with an indirect call of
fifo/g84.c g84_fifo_engine_id(). The G84_FIFO_ENGN_* values returned
from the later g84_fifo_engine_id() are incremented by 1 compared to
the previous g84_fifo_c
The hardware is capable of controlling any non-contiguous sequence of
LEDs specified in the DT using qcom,enabled-strings as u32
array, and this also follows from the DT-bindings documentation. The
numbers specified in this array represent indices of the LED strings
that are to be enabled and disa
Remove redundant spaces inside for loop conditions. No other double
spaces were found that are not part of indentation with `[^\s] `.
Signed-off-by: Marijn Suijten
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: Daniel Thompson
---
drivers/video/backlight/qcom-wled.c | 4 ++--
1 file c
The previous commit improves num_strings parsing to not go over the
maximum of 3 strings for WLED3 anymore. Likewise this default index for
a hypothetical 4th string is invalid and could access registers that are
not mapped to the desired purpose.
Removing this value gets rid of undesired confusio
When not specifying num-strings in the DT the default is used, but +1 is
added to it which turns WLED3 into 4 and WLED4/5 into 5 strings instead
of 3 and 4 respectively, causing out-of-bounds reads and register
read/writes. This +1 exists for a deficiency in the DT parsing code,
and is simply omit
Only WLED 3 sets a sensible default that allows operating this driver
with just qcom,num-strings in the DT; WLED 4 and 5 require
qcom,enabled-strings to be provided otherwise enabled_strings remains
zero-initialized, resuling in every string-specific register write
(currently only the setup and con
The length of qcom,enabled-strings as property array is enough to
determine the number of strings to be enabled, without needing to set
qcom,num-strings to override the default number of strings when less
than the default (which is also the maxium) is provided in DT.
Fixes: 775d2ffb4af6 ("backligh
of_property_read_u32_array takes the number of elements to read as last
argument. This does not always need to be 4 (sizeof(u32)) but should
instead be the size of the array in DT as read just above with
of_property_count_elems_of_size.
To not make such an error go unnoticed again the driver now b
The strings passed in DT may possibly cause out-of-bounds register
accesses and should be validated before use.
Fixes: 775d2ffb4af6 ("backlight: qcom-wled: Restructure the driver for WLED3")
Signed-off-by: Marijn Suijten
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/video/backlight/qcom-
The kernel already provides appropriate primitives to perform endianness
conversion which should be used in favour of manual bit-wrangling.
Signed-off-by: Marijn Suijten
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: Daniel Thompson
---
drivers/video/backlight/qcom-wled.c | 25 +
This patchset fixes WLED's handling of enabled-strings: besides some
cleanup it is now actually possible to specify a non-contiguous array of
enabled strings (not necessarily starting at zero) and the values from
DT are now validated to prevent possible unexpected out-of-bounds
register and array e
Hi Stephen,
Le mer., oct. 6 2021 at 12:38:00 -0700, Stephen Boyd
a écrit :
Use an aggregate driver instead of component ops so that we can get
proper driver probe ordering of the aggregate device with respect to
all
the component devices that make up the aggregate device.
TODO: Move the hel
On 2021-10-06 15:44:44, Daniel Thompson wrote:
> On Tue, Oct 05, 2021 at 07:34:00PM +0200, Marijn Suijten wrote:
> > On 2021-10-05 17:24:53, Daniel Thompson wrote:
> > > On Tue, Oct 05, 2021 at 05:23:26PM +0200, Marijn Suijten wrote:
> > > > Since there don't seem to be any substantial platforms/PM
Quoting Andrzej Hajda (2021-10-07 03:16:27)
> Hi Stephen,
>
> On 06.10.2021 21:37, Stephen Boyd wrote:
> > This series is from discussion we had on reordering the device lists for
> > drm shutdown paths[1]. I've introduced an 'aggregate' bus that we put
> > the aggregate device onto and then we pro
Quoting Greg Kroah-Hartman (2021-10-06 22:37:40)
> On Wed, Oct 06, 2021 at 12:37:47PM -0700, Stephen Boyd wrote:
> >
> > Let's make the component driver into an actual device driver that has
> > probe/remove/shutdown functions. The driver will only be bound to the
> > aggregate device once all comp
On 2021-10-07 13:06, Bjorn Andersson wrote:
On Thu 07 Oct 12:51 PDT 2021, khs...@codeaurora.org wrote:
On 2021-10-06 10:31, Bjorn Andersson wrote:
> On Wed 06 Oct 08:37 PDT 2021, khs...@codeaurora.org wrote:
>
> > On 2021-10-05 19:10, Bjorn Andersson wrote:
> > > On Tue 05 Oct 16:04 PDT 2021, k
On 10/4/2021 15:06, Matthew Brost wrote:
In GuC parent-child contexts the parent context controls the scheduling,
ensure only the parent does the scheduling operations.
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 13 +
On 07.10.2021 13:07, Dave Stevenson wrote:
On Tue, 5 Oct 2021 at 22:03, Andrzej Hajda wrote:
On 05.10.2021 17:32, Dave Stevenson wrote:
Hi Andrzej
Thanks for joining in the discussion.
On Tue, 5 Oct 2021 at 16:08, Andrzej Hajda wrote:
On 05.10.2021 13:23, Dave Stevenson wrote:
Hi Lauren
Quoting Stephen Boyd (2021-10-07 11:40:07)
> Quoting Saravana Kannan (2021-10-06 20:07:11)
> > On Wed, Oct 6, 2021 at 12:38 PM Stephen Boyd wrote:
> > > diff --git a/drivers/base/component.c b/drivers/base/component.c
> > > index 0a41bbe14981..d99e99cabb99 100644
> > > --- a/drivers/base/component
On Thu 07 Oct 12:51 PDT 2021, khs...@codeaurora.org wrote:
> On 2021-10-06 10:31, Bjorn Andersson wrote:
> > On Wed 06 Oct 08:37 PDT 2021, khs...@codeaurora.org wrote:
> >
> > > On 2021-10-05 19:10, Bjorn Andersson wrote:
> > > > On Tue 05 Oct 16:04 PDT 2021, khs...@codeaurora.org wrote:
> > > >
On 2021-10-06 10:31, Bjorn Andersson wrote:
On Wed 06 Oct 08:37 PDT 2021, khs...@codeaurora.org wrote:
On 2021-10-05 19:10, Bjorn Andersson wrote:
> On Tue 05 Oct 16:04 PDT 2021, khs...@codeaurora.org wrote:
>
> > On 2021-10-05 15:36, Stephen Boyd wrote:
> > > Quoting Bjorn Andersson (2021-10-0
On 10/6/21 11:47 AM, Robert Foss wrote:
On Tue, 7 Sept 2021 at 04:40, Marek Vasut wrote:
Move detach implementation from sn65dsi83_remove() to dedicated
.detach callback. There is no functional change to the code, but
that detach is now in the correct location.
Signed-off-by: Marek Vasu
On 10/4/2021 15:06, Matthew Brost wrote:
Add multi-lrc context registration H2G. In addition a workqueue and
process descriptor are setup during multi-lrc context registration as
these data structures are needed for multi-lrc submission.
v2:
(John Harrison)
- Move GuC specific fields into s
---
include/drm/drm_mode_config.h | 10 --
1 file changed, 10 deletions(-)
diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h
index 48b7de80daf5..b214b07157f2 100644
--- a/include/drm/drm_mode_config.h
+++ b/include/drm/drm_mode_config.h
@@ -383,16 +383,6 @@ struct
Functions drm_modeset_lock_all() and drm_modeset_unlock_all() are no
longer used anywhere and can be removed.
Signed-off-by: Fernando Ramos
---
drivers/gpu/drm/drm_modeset_lock.c | 94 +-
include/drm/drm_modeset_lock.h | 2 -
2 files changed, 3 insertions(+), 93
As requested in Documentation/gpu/todo.rst, replace driver calls to
drm_modeset_lock_all() with DRM_MODESET_LOCK_ALL_BEGIN() and
DRM_MODESET_LOCK_ALL_END()
NOTE:
While this change is similar to the one done two commits ago, it
contains an important extra nuances that I'm going to explain next.
T
Refactor places using drm_modeset_{lock,unlock}_all() so that they only
appear once per function.
This is needed so that in the next commit I can replace those functions
by the new macros (which use labels that can only appear once per
function).
Signed-off-by: Fernando Ramos
---
.../gpu/drm/am
As requested in Documentation/gpu/todo.rst, replace driver calls to
drm_modeset_lock_all() with DRM_MODESET_LOCK_ALL_BEGIN() and
DRM_MODESET_LOCK_ALL_END()
Signed-off-by: Fernando Ramos
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 21 ++---
1 file changed, 14 insertions(+),
As requested in Documentation/gpu/todo.rst, replace driver calls to
drm_modeset_lock_all() with DRM_MODESET_LOCK_ALL_BEGIN() and
DRM_MODESET_LOCK_ALL_END()
Signed-off-by: Fernando Ramos
---
drivers/gpu/drm/gma500/psb_device.c | 18 --
1 file changed, 12 insertions(+), 6 deletions
As requested in Documentation/gpu/todo.rst, replace driver calls to
drm_modeset_lock_all() with DRM_MODESET_LOCK_ALL_BEGIN() and
DRM_MODESET_LOCK_ALL_END()
NOTE:
While the previous two commits were a simple "search and replace", this
time I had to do a bit of refactoring as only one call to
DRM_M
As requested in Documentation/gpu/todo.rst, replace driver calls to
drm_modeset_lock_all() with DRM_MODESET_LOCK_ALL_BEGIN() and
DRM_MODESET_LOCK_ALL_END()
NOTE:
I separated this change from the rest of modifications to the i915
driver to point out something special explained next.
The only diff
As requested in Documentation/gpu/todo.rst, replace driver calls to
drm_modeset_lock_all() with DRM_MODESET_LOCK_ALL_BEGIN() and
DRM_MODESET_LOCK_ALL_END()
Signed-off-by: Fernando Ramos
---
drivers/gpu/drm/i915/display/intel_audio.c| 16 ---
.../drm/i915/display/intel_display_debugfs.c
As requested in Documentation/gpu/todo.rst, replace driver calls to
drm_modeset_lock_all() with DRM_MODESET_LOCK_ALL_BEGIN() and
DRM_MODESET_LOCK_ALL_END()
Signed-off-by: Fernando Ramos
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
As requested in Documentation/gpu/todo.rst, replace driver calls to
drm_modeset_lock_all() with DRM_MODESET_LOCK_ALL_BEGIN() and
DRM_MODESET_LOCK_ALL_END()
Signed-off-by: Fernando Ramos
Reviewed-by: Sean Paul
---
drivers/gpu/drm/nouveau/dispnv50/disp.c | 15 ++-
1 file changed, 10 i
As requested in Documentation/gpu/todo.rst, replace driver calls to
drm_modeset_lock_all() with DRM_MODESET_LOCK_ALL_BEGIN() and
DRM_MODESET_LOCK_ALL_END()
Signed-off-by: Fernando Ramos
Reviewed-by: Sean Paul
---
drivers/gpu/drm/omapdrm/omap_fb.c | 9 ++---
1 file changed, 6 insertions(+),
As requested in Documentation/gpu/todo.rst, replace driver calls to
drm_modeset_lock_all() with DRM_MODESET_LOCK_ALL_BEGIN() and
DRM_MODESET_LOCK_ALL_END()
Signed-off-by: Fernando Ramos
---
drivers/gpu/drm/radeon/radeon_device.c | 21 +++--
drivers/gpu/drm/radeon/radeon_dp_mst.c
As requested in Documentation/gpu/todo.rst, replace driver calls to
drm_modeset_lock_all() with DRM_MODESET_LOCK_ALL_BEGIN() and
DRM_MODESET_LOCK_ALL_END()
Signed-off-by: Fernando Ramos
Reviewed-by: Sean Paul
---
drivers/gpu/drm/shmobile/shmob_drm_drv.c | 6 --
1 file changed, 4 insertions(
As requested in Documentation/gpu/todo.rst, replace driver calls to
drm_modeset_lock_all() with DRM_MODESET_LOCK_ALL_BEGIN() and
DRM_MODESET_LOCK_ALL_END()
Signed-off-by: Fernando Ramos
Reviewed-by: Sean Paul
Reported-by: kernel test robot
---
drivers/gpu/drm/tegra/dsi.c | 6 --
drivers/
As requested in Documentation/gpu/todo.rst, replace driver calls to
drm_modeset_lock_all() with DRM_MODESET_LOCK_ALL_BEGIN() and
DRM_MODESET_LOCK_ALL_END()
Signed-off-by: Fernando Ramos
Reviewed-by: Sean Paul
---
drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c | 11 +++
drivers/gpu/drm/vmwgfx/vmw
As requested in Documentation/gpu/todo.rst, replace driver calls to
drm_modeset_lock_all() with DRM_MODESET_LOCK_ALL_BEGIN() and
DRM_MODESET_LOCK_ALL_END()
Signed-off-by: Fernando Ramos
Reviewed-by: Sean Paul
---
drivers/gpu/drm/drm_client_modeset.c | 5 +++--
drivers/gpu/drm/drm_crtc_helper.c
As requested in Documentation/gpu/todo.rst, replace the boilerplate code
surrounding drm_modeset_lock_all_ctx() with DRM_MODESET_LOCK_ALL_BEGIN()
and DRM_MODESET_LOCK_ALL_END()
Signed-off-by: Fernando Ramos
Reviewed-by: Sean Paul
Reported-by: kernel test robot
---
drivers/gpu/drm/msm/disp/msm_
As requested in Documentation/gpu/todo.rst, replace the boilerplate code
surrounding drm_modeset_lock_all_ctx() with DRM_MODESET_LOCK_ALL_BEGIN()
and DRM_MODESET_LOCK_ALL_END()
Signed-off-by: Fernando Ramos
Reviewed-by: Sean Paul
---
drivers/gpu/drm/i915/display/intel_display.c | 18 +--
As requested in Documentation/gpu/todo.rst, replace the boilerplate code
surrounding drm_modeset_lock_all_ctx() with DRM_MODESET_LOCK_ALL_BEGIN()
and DRM_MODESET_LOCK_ALL_END()
Signed-off-by: Fernando Ramos
---
drivers/gpu/drm/drm_client_modeset.c | 9 +++--
1 file changed, 3 insertions(+),
Hi all,
One of the things in the DRM TODO list ("Documentation/gpu/todo.rst") was to
"use DRM_MODESET_LOCAL_ALL_* helpers instead of boilerplate". That's what this
patch series is about.
You will find two types of changes here:
- Replacing "drm_modeset_lock_all_ctx()" (and surrounding boilerpl
On 10/4/2021 15:06, Matthew Brost wrote:
Introduce context parent-child relationship. Once this relationship is
created all pinning / unpinning operations are directed to the parent
context. The parent context is responsible for pinning all of its'
No need for an apostrophe.
children and itsel
On 10/4/2021 15:06, Matthew Brost wrote:
Add logical engine mapping. This is required for split-frame, as
workloads need to be placed on engines in a logically contiguous manner.
v2:
(Daniel Vetter)
- Add kernel doc for new fields
v3
(Tvrtko)
- Update comment for new logical_mask field
The "dp_debug" show function allocates a buffer and piecemeal appends
line by line, checking for buffer overflows etc.
Migrate the function to seq_file, to remove all the extra book keeping
and simplify the function.
Reviewed-by: Stephen Boyd
Signed-off-by: Bjorn Andersson
---
Changes since v1
Quoting Bjorn Andersson (2021-10-07 11:33:41)
> The "dp_debug" show function allocates a buffer and piecemeal appends
> line by line, checking for buffer overflows etc.
>
> Migrate the function to seq_file, to remove all the extra book keeping
> and simplify the function.
>
> Signed-off-by: Bjorn A
Quoting Saravana Kannan (2021-10-06 20:07:11)
> On Wed, Oct 6, 2021 at 12:38 PM Stephen Boyd wrote:
> > diff --git a/drivers/base/component.c b/drivers/base/component.c
> > index 0a41bbe14981..d99e99cabb99 100644
> > --- a/drivers/base/component.c
> > +++ b/drivers/base/component.c
[...]
> > +
Quoting Laurent Pinchart (2021-10-06 18:17:25)
> Hi Stephen,
>
> Thank you for the patch.
>
> On Wed, Oct 06, 2021 at 12:37:46PM -0700, Stephen Boyd wrote:
> > Replace 'struct master' with 'struct aggregate_device' and then rename
> > 'master' to 'adev' everywhere in the code. While we're here, put
The "dp_debug" show function allocates a buffer and piecemeal appends
line by line, checking for buffer overflows etc.
Migrate the function to seq_file, to remove all the extra book keeping
and simplify the function.
Signed-off-by: Bjorn Andersson
---
drivers/gpu/drm/msm/dp/dp_debug.c | 161 +++
On 10/7/2021 08:05, Matthew Brost wrote:
On Wed, Oct 06, 2021 at 08:06:41PM -0700, John Harrison wrote:
On 10/4/2021 15:06, Matthew Brost wrote:
Move guc_id allocation under submission state sub-struct as a future
patch will reuse the spin lock as a global submission state lock. Moving
this int
On Mon, Sep 27, 2021 at 11:36:59AM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> Linking fails when dma-buf is disabled:
>
> ld.lld: error: undefined symbol: dma_fence_release
> >>> referenced by fence.c
> >>> gpu/host1x/fence.o:(host1x_syncpt_fence_enable_signaling)
> >>>
On Mon, Oct 04, 2021 at 10:37:26PM -0700, Randy Dunlap wrote:
> Fix kernel-doc warning in host1x:
>
> ../drivers/gpu/host1x/bus.c:774: warning: Excess function parameter 'key'
> description in '__host1x_client_register'
>
> Fixes: 0cfe5a6e758f ("gpu: host1x: Split up client initalization and
>
On Thu 07 Oct 03:17 PDT 2021, Heikki Krogerus wrote:
> Hi guys,
>
> On Wed, Oct 06, 2021 at 01:26:35PM -0700, Prashant Malani wrote:
> > (CC+ Heikki)
> >
> > Hi,
> >
> > On Wed, Oct 6, 2021 at 8:19 AM Doug Anderson wrote:
> > >
> > > Hi,
> > >
> > > On Tue, Oct 5, 2021 at 7:27 PM Bjorn Anderss
On Wed, Oct 6, 2021 at 2:21 AM Lucas De Marchi wrote:
>
> When trying to bring IS_ACTIVE to linux/kconfig.h I thought it wouldn't
> provide much value just encapsulating it in a boolean context. So I also
> added the support for handling undefined macros as the IS_ENABLED()
> counterpart. However
On Thu, Oct 07, 2021 at 09:17:34AM +0100, Tvrtko Ursulin wrote:
On 06/10/2021 21:45, Umesh Nerlige Ramappa wrote:
On Wed, Oct 06, 2021 at 10:11:58AM +0100, Tvrtko Ursulin wrote:
[snip]
@@ -762,12 +764,25 @@ submission_disabled(struct intel_guc *guc)
static void disable_submission(struct in
Applied. Thanks!
Alex
On Thu, Oct 7, 2021 at 8:06 AM Colin King wrote:
>
> From: Colin Ian King
>
> The variable result is being initialized with a value that is never
> read, it is being updated immediately afterwards in both branches
> of an if statement. The assignment is redundant and can
On Wed, Oct 06, 2021 at 08:45:42PM -0700, John Harrison wrote:
> On 10/4/2021 15:06, Matthew Brost wrote:
> > Taking a PM reference to prevent intel_gt_wait_for_idle from short
> > circuiting while a scheduling of user context could be enabled.
> I'm not sure what 'while a scheduling of user contex
On Wed, Oct 06, 2021 at 08:06:41PM -0700, John Harrison wrote:
> On 10/4/2021 15:06, Matthew Brost wrote:
> > Move guc_id allocation under submission state sub-struct as a future
> > patch will reuse the spin lock as a global submission state lock. Moving
> > this into sub-struct makes ownership of
From: Arnd Bergmann
Now that SCM can be a loadable module, we have to add another
dependency to avoid link failures when ipa or adreno-gpu are
built-in:
aarch64-linux-ld: drivers/net/ipa/ipa_main.o: in function `ipa_probe':
ipa_main.c:(.text+0xfc4): undefined reference to `qcom_scm_is_available'
From: Arnd Bergmann
Compile-testing drivers that require access to a firmware layer
fails when that firmware symbol is unavailable. This happened
twice this week:
- My proposed to change to rework the QCOM_SCM firmware symbol
broke on ppc64 and others.
- The cs_dsp firmware patch added dev
Am 07.10.21 um 15:26 schrieb Thomas Hellström:
While the range notifier is executing, we have the write-side mmu interval
seqlock, and mmu_interval_read_retry() is always returning true,
which means that if amdgpu_cs_submit grabs the notifier lock during the
fence wait, it will retry anyway when
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