On Tue, 2021-08-31 at 14:47 +0200, Daniel Vetter wrote:
> On Mon, Aug 30, 2021 at 10:39:11AM +0800, guangming@mediatek.com
> wrote:
> > From: Guangming Cao
> >
> > When mapping the memory represented by a dma-buf into a device's
> > address space, it might be desireable to map the memory
Add audio HDMI codec function support, enable it through device true
flag "analogix,audio-enable".
Reviewed-by: Robert Foss
Signed-off-by: Xin Ji
---
drivers/gpu/drm/bridge/analogix/anx7625.c | 226 ++
drivers/gpu/drm/bridge/analogix/anx7625.h | 5 +
2 files changed, 231
The basic anx7625 driver only support MIPI DSI rx signal input.
This patch add MIPI DPI rx input configuration support, after apply
this patch, the driver can support DSI rx or DPI rx by adding
'bus-type' in DT.
Reviewed-by: Robert Foss
Signed-off-by: Xin Ji
---
At some time, the original code may return non zero value, force return 0
if operation finished.
Reviewed-by: Robert Foss
Signed-off-by: Xin Ji
---
drivers/gpu/drm/bridge/analogix/anx7625.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
Add 'bus-type' and 'data-lanes' define for port0. Add DP tx lane0,
lane1 swing register setting array, and audio enable flag.
The device which cannot pass DP tx PHY CTS caused by long PCB trace or
embedded MUX, adjusting ANX7625 PHY parameters can pass the CTS test. The
adjusting type include
Hi all, this patch series implement MIPI rx DPI feature. Please help to review.
This is the v11 version, rebase all patches on the latest code.
Any mistakes, please let me know, I'll fix it in the next series.
Change history:
v11: Fix Rob Herring comment
- Move swing register description in
Hi Pekka,
>
> Hi Vivek!
>
> > > On Mon, 13 Sep 2021 16:35:26 -0700
> > > Vivek Kasireddy wrote:
> > >
> > > > If a driver supports this capability, it means that there would be an
> > > > additional signalling mechanism for a page flip completion in addition
> > > > to out_fence or
On Thu, 14 Oct 2021 at 19:09, Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> Fix a pile of regression on older machines which just oops the driver
> on load.
>
For all 4:
Reviewed-by: Dave Airlie
though it would be nice if the clflushes has more justifications on
initial patch
Am Dienstag, 28. September 2021, 23:35:50 CEST schrieb Brian Norris:
> Since commit 43c2de1002d2, we perform most HW configuration in the
> bind() function. This configuration may be lost on suspend/resume, so we
> need to call it again. That may lead to errors like this after system
>
Thanks for applying.
Den 17.10.2021 kl. 19.24 skrev Sam Ravnborg:
Hi Dan,
On Wed, Aug 18, 2021 at 11:48:18PM +0200, Dan Johansen wrote:
This adjusts sync values according to the datasheet
Fixes: 1c243751c095bb95e2795f076ea7a0bcdd60a93a ("drm/panel: ilitek-ili9881c: add
support for Feixin
On Tue, 28 Sep 2021 14:35:48 -0700, Brian Norris wrote:
> The Rockchip DSI driver has had a number of bugs over time and has
> usually only worked by chance. A number of users have noticed that
> things regressed with commit 43c2de1002d2 ("drm/rockchip: dsi: move all
> lane config except LCDC mux
On Fri, 8 Oct 2021 15:31:04 -0700, Brian Norris wrote:
> If hardware is malfunctioning (e.g., misconfigured clocks?), we can get
> stuck here forever, holding various DRM locks and eventually locking up
> the entire system. It's better to complain loudly and move on, than to
> lock up the system.
Hi Sujaritha,
[...]
> > +void intel_gt_sysfs_unregister(struct intel_gt *gt)
> > +{
> > +}
>
> Is there a reason for this function to not be populated ?
yes, there is, indeed, something missing here. There has been a
fix bout this floating around from Chris about sysfs_gt kobjects.
I will
On 10/17/21 7:40 PM, Sam Ravnborg wrote:
Hi Marek,
On Sun, Oct 17, 2021 at 07:29:51PM +0200, Marek Vasut wrote:
On 10/17/21 6:49 PM, Sam Ravnborg wrote:
[...]
+ /*
+* Encoder might sample data on different clock edge than the display,
+* for example OnSemi FIN3385 has
On 10/17/21 7:52 PM, Sam Ravnborg wrote:
Hi Marek,
On Wed, Sep 08, 2021 at 08:24:20PM +0200, Daniel Vetter wrote:
On Tue, Sep 07, 2021 at 04:49:00AM +0200, Marek Vasut wrote:
The mxsfb->crtc.funcs may already be NULL when unloading the driver,
in which case calling mxsfb_irq_disable() via
On Wed, Oct 13, 2021 at 08:36:01PM +0200, Nirmoy Das wrote:
> Debugfs APIs returns encoded error on failure so use
> debugfs_lookup() instead of checking for NULL.
The commit message no longer matches up with the patch itself
(debugfs_lookup() isn't called).
My suggestion would be something
Conversion of text binding for Adreno GPU to the YAML format.
Signed-off-by: David Heidelberg
---
v2:
- added compatbile description from Rob Clark
- dropped reg description
- reg numbers increased to 3 (since we also have uncommon cx_dbgc)
- specified interconnect-names items range
-
On Sat, Oct 16, 2021 at 8:45 AM Jason Gunthorpe wrote:
>
> On Thu, Oct 14, 2021 at 06:37:35PM -0700, Dan Williams wrote:
> > On Thu, Oct 14, 2021 at 4:06 PM Jason Gunthorpe wrote:
> > >
> > > On Thu, Oct 14, 2021 at 12:01:14PM -0700, Dan Williams wrote:
> > > > > > Does anyone know why devmap is
On Sat, Oct 16, 2021 at 9:39 AM Matthew Wilcox wrote:
>
> On Sat, Oct 16, 2021 at 12:44:50PM -0300, Jason Gunthorpe wrote:
> > Assuming changing FSDAX is hard.. How would DAX people feel about just
> > deleting the PUD/PMD support until it can be done with compound pages?
>
> I think there are
Hi Mario,
Before we can apply this you need to:
- Add a description of the patch
- Add you s-o-b - see SubmittingPatches in Documentation/
Sam
On Fri, Sep 17, 2021 at 04:57:19PM +0200, Mario wrote:
> ---
> drivers/gpu/drm/drm_panel_orientation_quirks.c | 6 ++
> 1 file changed, 6
Hi Marek,
On Wed, Sep 08, 2021 at 08:24:20PM +0200, Daniel Vetter wrote:
> On Tue, Sep 07, 2021 at 04:49:00AM +0200, Marek Vasut wrote:
> > The mxsfb->crtc.funcs may already be NULL when unloading the driver,
> > in which case calling mxsfb_irq_disable() via drm_irq_uninstall() from
> >
Hi Marek,
On Sun, Oct 17, 2021 at 07:29:51PM +0200, Marek Vasut wrote:
> On 10/17/21 6:49 PM, Sam Ravnborg wrote:
>
> [...]
>
> > > + /*
> > > + * Encoder might sample data on different clock edge than the display,
> > > + * for example OnSemi FIN3385 has a dedicated strapping pin to select
>
Hi Shawn,
On Mon, Aug 09, 2021 at 01:10:06PM +0800, Shawn Guo wrote:
> It adds driver for Sony Tulip Truly NT35521 5.24" 1280x720 DSI panel,
> which can be found on Sony Xperia M4 Aqua phone.
>
> Changes for v2:
> - Add `port` node into bindings.
> - Re-create the driver using
Hi Julian,
On Sun, Aug 08, 2021 at 04:08:54PM -0400, Julian Braha wrote:
> This is a 5.7" 2160x1080 panel found on the Motorola Moto G6.
> There may be other smartphones using it, as well.
>
> Signed-off-by: Julian Braha
Sorry for coming back so late. Driver looks good and is almost
ready to
On 10/17/21 6:49 PM, Sam Ravnborg wrote:
[...]
+ /*
+* Encoder might sample data on different clock edge than the display,
+* for example OnSemi FIN3385 has a dedicated strapping pin to select
+* the sampling edge.
+*/
+ if
Hi Dan,
On Wed, Aug 18, 2021 at 11:48:18PM +0200, Dan Johansen wrote:
> This adjusts sync values according to the datasheet
>
> Fixes:1c243751c095bb95e2795f076ea7a0bcdd60a93a ("drm/panel:
> ilitek-ili9881c: add support for Feixin K101-IM2BYL02 panel")
> Co-developed-by: Marius Gripsgard
Hi AngeloGioacchino,
On Wed, Sep 01, 2021 at 07:31:14PM +0200, AngeloGioacchino Del Regno wrote:
> This adds support for the BOE BF060Y8M-AJ0 5.99" AMOLED module
> that can be found in some F(x)Tec Pro1 and Elephone U1 devices.
>
> Signed-off-by: AngeloGioacchino Del Regno
>
Applied the
Hi AngeloGioacchino,
On Wed, Sep 01, 2021 at 07:31:26PM +0200, AngeloGioacchino Del Regno wrote:
> Add a driver for panels using the Novatek NT35950 Display Driver IC,
> including support for the Sharp LS055D1SX04, found in some Sony Xperia
> Z5 Premium and XZ Premium smartphones.
>
>
Define the memory region on RK3399 VOPs containing the gamma LUT at
base+0x2000.
Signed-off-by: Hugh Cole-Baker
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
This extends the Rockchip VOP driver to support setting the gamma LUT on the
RK3399 SoC. Previously, the driver supported gamma control for the RK3288
only. On the RK3399 the method for updating the LUT is slightly different.
This implementation was based on the code and description from the
The VOP on RK3399 has a different approach from previous versions for
setting a gamma lookup table, using an update_gamma_lut register. As
this differs from RK3288, give RK3399 its own set of "common" register
definitions.
Signed-off-by: Hugh Cole-Baker
---
The RK3399 has a 1024-entry gamma LUT with 10 bits per component on its
"big" VOP and a 256-entry, 8 bit per component LUT on the "little" VOP.
Compared to the RK3288, it no longer requires disabling gamma while
updating the LUT. On the RK3399, the LUT can be updated at any time as
the hardware
Hi Marek,
On Sat, Oct 16, 2021 at 11:04:02PM +0200, Marek Vasut wrote:
> Current code always sets reset line low in .pre_enable callback and
> holds it low for 10ms. This is sub-optimal and increases the time
> between enablement of the DSI83 and valid LVDS clock.
>
> Rework the reset handling
Hi Marek,
On Sun, Oct 17, 2021 at 02:12:04AM +0200, Marek Vasut wrote:
> The OnSemi FIN3385 Parallel-to-LVDS encoder has a dedicated input line to
> select input pixel data sampling edge. Add DT property "pclk-sample", not
> the same as the one used by display timings but rather the same as used
On Fri 15 Oct 16:53 PDT 2021, abhin...@codeaurora.org wrote:
> On 2021-10-15 16:17, Bjorn Andersson wrote:
> > In the cleanup path of the MSM DP driver the DP driver's debugfs files
> > are destroyed by invoking debugfs_remove_recursive() on debug->root,
> > which during initialization has been
Hi Marek,
On Sat, Oct 16, 2021 at 11:04:46PM +0200, Marek Vasut wrote:
> The mxsfb->crtc.funcs may already be NULL when unloading the driver,
> in which case calling mxsfb_irq_disable() via drm_irq_uninstall() from
> mxsfb_unload() leads to NULL pointer dereference.
>
> Since all we care about
On Sat 16 Oct 20:32 CDT 2021, Stephen Boyd wrote:
> Quoting Bjorn Andersson (2021-10-16 15:18:43)
> > The sc8180x has 2 DP and 1 eDP controllers, add support for these to the
> > DP driver.
> >
> > Link:
> >
On Fri, 15 Oct 2021 00:42:21 +0300, Dmitry Baryshkov wrote:
> Stop using legacy clock names (with _clk suffix) for HDMI and HDMI PHY
> device tree nodes.
>
>
Applied, thanks!
[1/1] ARM: dts: qcom-apq8064: stop using legacy clock names for HDMI
commit:
Thanks for the notice. Going to take a deeper look into this tomorrow.
Basically looks like we messed up the fence ref count somehow.
Thanks,
Christian.
Am 17.10.21 um 16:40 schrieb Nicolas Frattaroli:
On Dienstag, 5. Oktober 2021 13:37:30 CEST Christian König wrote:
Simplifying the code a
On Dienstag, 5. Oktober 2021 13:37:30 CEST Christian König wrote:
> Simplifying the code a bit.
>
> v2: use dma_resv_for_each_fence
>
> Signed-off-by: Christian König
> Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/scheduler/sched_main.c | 26 ++
> 1 file changed,
On Wed, Oct 13, 2021 at 06:55:31AM -0400, Michael S. Tsirkin wrote:
> This will enable cleanups down the road.
> The idea is to disable cbs, then add "flush_queued_cbs" callback
> as a parameter, this way drivers can flush any work
> queued after callbacks have been disabled.
>
> Signed-off-by:
This is a note to let you know that I've just added the patch titled
drm/fbdev: Clamp fbdev surface size if too large
to the 5.14-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
01.10.2021 18:01, Ulf Hansson пишет:
> On Fri, 1 Oct 2021 at 16:35, Dmitry Osipenko wrote:
>>
>> 01.10.2021 17:24, Ulf Hansson пишет:
>>> On Mon, 27 Sept 2021 at 00:42, Dmitry Osipenko wrote:
The NAND on Tegra belongs to the core power domain and we're going to
enable GENPD
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