In function do_fb_ioctl(), the "arg" is the type of unsigned long,
and in "case FBIOBLANK:" this argument is casted into an int before
passig to fb_blank(). In fb_blank(), the comparision
if (blank > FB_BLANK_POWERDOWN) would be bypass if the original
"arg" is a large number, which is possible
Looks good, feel free to add:
Reviewed-by: Alistair Popple
On Saturday, 29 January 2022 7:08:16 AM AEDT Alex Sierra wrote:
> Device memory that is cache coherent from device and CPU point of view.
> This is used on platforms that have an advanced system bus (like CAPI
> or CXL). Any page of a
On Saturday, 29 January 2022 7:08:17 AM AEDT Alex Sierra wrote:
[...]
> struct migrate_vma {
> diff --git a/mm/migrate.c b/mm/migrate.c
> index cd137aedcfe5..d3cc3589e1e8 100644
> --- a/mm/migrate.c
> +++ b/mm/migrate.c
> @@ -2264,7 +2264,8 @@ static int migrate_vma_collect_pmd(pmd_t *pmdp,
>
Hi All,
Gentle Reminder! Any Review comments?
> Changing vkms driver to accomadate the change of
> drm_writeback_connector.base to a pointer the reason for which is
> explained in the Patch(drm: add writeback pointers to drm_connector).
>
> Signed-off-by: Kandpal, Suraj
> ---
>
[Public]
Thanks, the patch is already submitted.
https://www.spinics.net/lists/amd-gfx/msg73613.html
Thanks,
Lijo
Hi Peter,
Am Freitag, 7. Januar 2022, 06:13:33 CET schrieb Peter Geis:
> Some implementations do not use the reset signal, instead tying it to dvdd.
> Make the reset gpio optional to permit this.
>
> Signed-off-by: Peter Geis
> ---
> drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c | 11
From: Svyatoslav Ryhel
Add definition of the HannStar HSD101PWW2 Rev0-A00/A01 LCD
SuperIPS+ HD panel.
Signed-off-by: Svyatoslav Ryhel
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/panel/panel-simple.c | 28
1 file changed, 28 insertions(+)
diff --git
From: Svyatoslav Ryhel
Add HannStar HSD101PWW2 10.1" WXGA (1280x800) TFT-LCD LVDS panel
to the list of compatibles.
Acked-by: Rob Herring
Signed-off-by: Svyatoslav Ryhel
Signed-off-by: Dmitry Osipenko
---
.../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++
1 file
From: Anton Bambura
LQ101R1SX03 is compatible with LQ101R1SX01 from software perspective,
document it. The LQ101R1SX03 is a newer revision of LQ101R1SX01, it has
minor differences in hardware pins in comparison to the older version.
The newer version of the panel can be found on Android tablets,
This series adds support for Sharp LQ101R1SX03 and HannStar HSD101PWW2
display panels that are used by Asus Transformer tablets, which we're
planning to support since 5.17 kernel.
Changelog:
v3: - No changes. Re-sending for 5.18. Device-trees of devices that use
these panels were merge to
John, Rodrigo,
It is now clear to me just how dependent i915 is going to be on the
closed source guc software, and that's just a fact of life for our
graphics stack going forward.
In that context, it seems kind of pointless for me to make a big deal
out of this peripheral "query item" commit
Hello DRI and fbdev developers,
I've now mostly checked all queued-up patches on the fbdev mailing list:
https://patchwork.kernel.org/project/linux-fbdev/list/
and applied the ones which seemed appropriate.
IMHO there is nothing really critical/important/conflicting in there.
Shortlog is below,
This series is to add DSI PHY tuning support in Qualcomm Snapdragon
SoCs with 10nm DSI PHY e.g. SC7180
In most cases the default values of DSI PHY tuning registers
should be sufficient as they are fully optimized. However, in
some cases (for example, where extreme board parasitics cause
the eye
In most cases, the default values of DSI PHY tuning registers should be
sufficient as they are fully optimized. However, in some cases where
extreme board parasitics cause the eye shape to degrade, the override
bits can be used to improve the signal quality.
The general guidelines for DSI PHY
The clock and data lanes of the DSI PHY have a calibration circuitry
feature. As per the MSM DSI PHY tuning guidelines, the drive strength
tuning can be done by adjusting rescode offset for hstop/hsbot, and
the drive level tuning can be done by adjusting the LDO output level
for the HSTX drive.
Add support for MSM DSI PHY tuning configuration. Current design is
to support drive strength and drive level/amplitude tuning for
10nm PHY version, but this can be extended to other PHY versions.
Signed-off-by: Rajeev Nandan
Reviewed-by: Dmitry Baryshkov
---
Changes in v2:
- New.
- Split
Hi,
The Kconfig text is looking good. Just one minor nit below:
On 1/30/22 11:37, Sui Jingfeng wrote:
> diff --git a/drivers/gpu/drm/lsdc/Kconfig b/drivers/gpu/drm/lsdc/Kconfig
> new file mode 100644
> index ..8c908787b4aa
> --- /dev/null
> +++ b/drivers/gpu/drm/lsdc/Kconfig
> @@ -0,0
Add support for MSM DSI PHY tuning configuration. Current design is
to support drive strength and drive level/amplitude tuning for
10nm PHY version, but this can be extended to other PHY versions.
Signed-off-by: Rajeev Nandan
Reviewed-by: Dmitry Baryshkov
---
Changes in v2:
- New.
- Split
This series is to add DSI PHY tuning support in Qualcomm Snapdragon
SoCs with 10nm DSI PHY e.g. SC7180
In most cases the default values of DSI PHY tuning registers
should be sufficient as they are fully optimized. However, in
some cases (for example, where extreme board parasitics cause
the eye
In most cases, the default values of DSI PHY tuning registers should be
sufficient as they are fully optimized. However, in some cases where
extreme board parasitics cause the eye shape to degrade, the override
bits can be used to improve the signal quality.
The general guidelines for DSI PHY
The clock and data lanes of the DSI PHY have a calibration circuitry
feature. As per the MSM DSI PHY tuning guidelines, the drive strength
tuning can be done by adjusting rescode offset for hstop/hsbot, and
the drive level tuning can be done by adjusting the LDO output level
for the HSTX drive.
From: suijingfeng
There is a display controller in loongson's LS2K1000 SoC and LS7A1000
bridge, and the DC in those chip is a PCI device. This display controller
have two display pipes but with only one hardware cursor. Each way has a
DVO output interface and the CRTC is able to scanout from
v3: fix more grammar mistakes in Kconfig reported by Randy Dunlap and give
more details about lsdc.
v2: fixup warnings reported by kernel test robot
There is a display controller in loongson's LS2K1000 SoC and LS7A1000
bridge, and the DC in those chip is a PCI device. This display controller
https://bugzilla.kernel.org/show_bug.cgi?id=215549
--- Comment #1 from techxga...@outlook.com ---
Created attachment 300353
--> https://bugzilla.kernel.org/attachment.cgi?id=300353=edit
Xorg log
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https://bugzilla.kernel.org/show_bug.cgi?id=215549
techxga...@outlook.com changed:
What|Removed |Added
Hardware|All |x86-64
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https://bugzilla.kernel.org/show_bug.cgi?id=215549
Bug ID: 215549
Summary: My 6900XT can't recover while it's idle (but not
asleep), and sometimes doesn't show at boot
Product: Drivers
Version: 2.5
Kernel Version:
Hello again,
I am facing the exact same symptoms as last September:
https://lists.freedesktop.org/archives/dri-devel/2021-September/324008.html
…meaning my (headless) Raspberry Pi 3 B and Raspberry Pi 3 B+ no longer
boot with Linux 5.16.3, while the (headless) Raspberry Pi 4 still boots.
This
https://bugzilla.kernel.org/show_bug.cgi?id=214197
vele...@gmail.com changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugzilla.kernel.org/show_bug.cgi?id=214197
--- Comment #8 from vele...@gmail.com ---
Recent kernels in 5.15.* and 5.16.* fix the issue for me.
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Am 29.01.22 um 08:35 schrieb zhanglianjie:
after the buffer object is successfully mapped, call radeon_bo_kunmap before
the function returns.
Signed-off-by: zhanglianjie
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c
b/drivers/gpu/drm/radeon/radeon_uvd.c
index
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