It's unclear what reference the initial vma kref refernce refers to.
A vma can have multiple weak references, the object vma list,
the vm's bound list and the GT's closed_list, and the initial vma
reference can be put from lookups of all these lists.
With the current implementation this means
that
Am 10.02.22 um 04:17 schrieb Andrey Grodzovsky:
Seems I forgot to add this to the relevant commit
when submitting.
Rebase/merge issue? Looks like it.
Signed-off-by: Andrey Grodzovsky
Reported-by: kernel test robot
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_re
Hello Sascha,
On 2/9/22 10:53, Sascha Hauer wrote:
> From: Andy Yan
>
> The VOP2 unit is found on Rockchip SoCs beginning with rk3566/rk3568.
> It replaces the VOP unit found in the older Rockchip SoCs.
>
> This driver has been derived from the downstream Rockchip Kernel and
> heavily modified:
Display Stream Compression (DSC) is one of the hw blocks in dpu, so add
support by adding hw blocks for DSC
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/Makefile | 1 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 13 ++
drivers/gpu/drm/
When DSC is enabled, we need to pass the DSC parameters to panel driver
as well, so add a dsc parameter in panel and set it when DSC is enabled
Also, fetch and pass DSC configuration for DSI panels to DPU encoder,
which will enable and configure DSC hardware blocks accordingly.
Signed-off-by: Dmi
Display Stream Compression (DSC) parameters need to be calculated. Add
helpers and struct msm_display_dsc_config in msm_drv for this
msm_display_dsc_config uses drm_dsc_config for DSC parameters.
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 132 +
Display Stream Compression (DSC) compresses the display stream in host which
is later decoded by panel. This series enables this for Qualcomm msm driver.
This was tested on Google Pixel3 phone which use LGE SW43408 panel.
The changes include DSC data and hardware block enabling for DPU1 then
supp
On Tue, 2022-02-08 at 11:02 +0100, Marek Vasut wrote:
> On 2/8/22 03:41, Liu Ying wrote:
>
> Hello everyone,
>
> > > > > There are many blank areas which are undocumented, this LCDIF
> > > > > CRC32
> > > > > feature, i.MX8M Mini Arteris NOC at 0x3270 , the ARM GPV
> > > > > NIC-
> > > > > 30
Hello Laurent,
On Tue, 2022-02-08 at 05:03 +0200, Laurent Pinchart wrote:
> Hello Liu Ying,
>
> On Tue, Feb 08, 2022 at 10:41:59AM +0800, Liu Ying wrote:
> > On Mon, 2022-02-07 at 11:43 +0100, Marek Vasut wrote:
> > > On 2/7/22 10:18, Liu Ying wrote:
> > > > > > On Sun, 2022-02-06 at 19:56 +0100,
Hi Abhinav,
On Wed, Feb 09, 2022 at 05:40:29PM -0800, Abhinav Kumar wrote:
> Hi Laurent
>
> Gentle reminder on this.
I won't have time before next week I'm afraid.
> On 2/6/2022 11:20 PM, Abhinav Kumar wrote:
> > Hi Laurent
> >
> > On 2/6/2022 3:32 PM, Dmitry Baryshkov wrote:
> >> On Wed, 2 Fe
Hi Dave, Daniel,
Fixes for 5.17.
The following changes since commit dfd42facf1e4ada021b939b4e19c935dcdd55566:
Linux 5.17-rc3 (2022-02-06 12:20:50 -0800)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-5.17-2022-02-09
for you to fe
On 2022/2/9 20:00, Jiaxun Yang wrote:
Hi Jingfeng,
Could you please keep me CCed for the for the whole thread when you
respin
the patch? Cuz I'm maintain MIPS/LOONGSON64 stuff and I believe this
series
is partially based on my work at Lemote.
I will help with reviewing and explain some Loo
On Wed, Feb 9, 2022 at 10:17 PM Andrey Grodzovsky
wrote:
>
> Seems I forgot to add this to the relevant commit
> when submitting.
>
> Signed-off-by: Andrey Grodzovsky
> Reported-by: kernel test robot
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h | 3 +--
> 1 file c
Seems I forgot to add this to the relevant commit
when submitting.
Signed-off-by: Andrey Grodzovsky
Reported-by: kernel test robot
---
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
b/dri
On Thursday, 10 February 2022 4:48:36 AM AEDT Christoph Hellwig wrote:
> On Mon, Feb 07, 2022 at 04:19:29PM -0500, Felix Kuehling wrote:
> >
> > Am 2022-02-07 um 01:32 schrieb Christoph Hellwig:
> >> Move the check for the actual pgmap types that need the free at refcount
> >> one behavior into the
Hi Laurent
Gentle reminder on this.
Thanks
Abhinav
On 2/6/2022 11:20 PM, Abhinav Kumar wrote:
Hi Laurent
On 2/6/2022 3:32 PM, Dmitry Baryshkov wrote:
On Wed, 2 Feb 2022 at 16:26, Laurent Pinchart
wrote:
Hi Jani,
On Wed, Feb 02, 2022 at 03:15:03PM +0200, Jani Nikula wrote:
On Wed, 02 Fe
Replace all occurance of cache_clflush_range with
drm_clflush_virt_range. This will prevent compile errors on non-x86
platforms.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++--
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function call, and prevent complier errors when
building for non-x86 architectures.
v2(Michael Cheng): Drop invalidate_csb_entries function and directly
invoke drm_clflush_virt_range.
Use drm_clflush_virt_range instead of directly invoking clflush. This
will prevent compiler errors when building for non-x86 architectures.
v2(Michael Cheng): Remove extra clflush
v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range
takes care of it.
Signed-of
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu
This patch series re-work a few i915 functions to use drm_clflush_virt_range
instead of calling clflush or clflushopt directly. This will prevent errors
when building for non-x86 architectures.
Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/intel_engine.h | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/driv
Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc
performs a flush by first performing a clean, follow by an invalidation
operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the
dcache.
v3 (Michael Cheng): Remove ifdef for asm/cach
Quoting Sankeerth Billakanti (2022-02-09 00:55:32)
> Add support in the DP driver to utilize the custom eDP panels
> from drm/panels.
>
> An eDP panel is always connected to the platform. So, the eDP
> connector can be reported as always connected. The display mode
> will be sourced from the panel.
Quoting Sankeerth Billakanti (2022-02-09 00:55:31)
> Add support for the 14" sharp,lq140m1jw46 eDP panel.
>
> Signed-off-by: Sankeerth Billakanti
> ---
Can you share the edid-decode for this panel here under the cut "---"?
It would help to see the timings and make sure everything matches.
Quoting Sankeerth Billakanti (2022-02-09 00:55:30)
> Enable the eDP display panel support without HPD on sc7280 platform.
>
> Signed-off-by: Sankeerth Billakanti
> ---
>
> Changes in v3:
> - Sort the nodes alphabetically
> - Use - instead of _ as node names
> - Place the backlight and panel
Quoting Sankeerth Billakanti (2022-02-09 00:55:29)
> Add support for sharp LQ140M1JW46 display panel. It is a 14" eDP panel
> with 1920x1080 display resolution.
>
> Signed-off-by: Sankeerth Billakanti
> ---
Reviewed-by: Stephen Boyd
Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function call, and prevent complier errors when
building for non-x86 architectures.
v2(Michael Cheng): Drop invalidate_csb_entries function and directly
invoke drm_clflush_virt_range.
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu
On Mon, 31 Jan 2022 17:54:39 +0100, quentin.sch...@theobroma-systems.com wrote:
> From: Quentin Schulz
>
> Heiko does not work at Theobroma Systems anymore and the boards using
> those panels are downstream, maintained internally by the company, so
> let's relieve Heiko of maintainership duties.
Use drm_clflush_virt_range instead of directly invoking clflush. This
will prevent compiler errors when building for non-x86 architectures.
v2(Michael Cheng): Remove extra clflush
v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range
takes care of it.
Signed-of
Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc
performs a flush by first performing a clean, follow by an invalidation
operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the
dcache.
v3 (Michael Cheng): Remove ifdef for asm/cach
Replace all occurance of cache_clflush_range with
drm_clflush_virt_range. This will prevent compile errors on non-x86
platforms.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++--
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/intel_engine.h | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/driv
This patch series re-work a few i915 functions to use drm_clflush_virt_range
instead of calling clflush or clflushopt directly. This will prevent errors
when building for non-x86 architectures.
On 1/21/2022 1:06 PM, Dmitry Baryshkov wrote:
INTF blocks are not really handled by resource manager, they are
assigned at dpu_encoder_setup_display using dpu_encoder_get_intf().
Then this allocation is passed to RM and then returned to then
dpu_encoder.
So allocate them outside of RM and use
Hi Sascha,
Something with port and endpoint gives notifications.
Somehow with the conversion of rockchip,dw-hdmi.txt to YAML not all SoC
options were checked/covered (see rk3328 and rk3568).
Allow multiple vop:
port or
port@0
1x vop -> endpoint
2x vop -> endpoint@0
-> endpoint@1
Also all
On 1/21/2022 1:06 PM, Dmitry Baryshkov wrote:
Add missing calls to dpu_hw_dspp_destroy() to free resources allocated
for DSPP hardware blocks.
Fixes: e47616df008b ("drm/msm/dpu: add support for color processing blocks in dpu
driver")
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Stephen Boyd
On 1/21/2022 1:06 PM, Dmitry Baryshkov wrote:
No code uses lm_max_width from resource manager, so drop it. Instead of
calculating the lm_max_width, code can use max_mixer_width field from
the hw catalog.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Stephen Boyd
Reviewed-by: Abhinav Kumar
On Tue, 08 Feb 2022 18:18:23 +0100, Krzysztof Kozlowski wrote:
> Convert the S3C/S5P/Exynos FIMD bindings to DT schema format.
>
> The conversion includes also updates to the bindings, matching the
> current DTS and Linux driver: adding optional iommus and power-domains.
>
> Signed-off-by: Krzysz
On Tue, 08 Feb 2022 18:18:22 +0100, Krzysztof Kozlowski wrote:
> Convert the Exynos5433 MIC bindings to DT schema format.
>
> The conversion includes also updates to the bindings, matching the
> current DTS and Linux driver: adding optional power-domains.
>
> Signed-off-by: Krzysztof Kozlowski
>
On Tue, 08 Feb 2022 18:18:21 +0100, Krzysztof Kozlowski wrote:
> Convert the Exynos HDMI bindings to DT schema format.
>
> The conversion includes also updates to the bindings, matching the
> current DTS and Linux driver:
> 1. Add required properties: VDD supplies, power-domains.
> 2. Add optional
On Tue, 08 Feb 2022 18:18:20 +0100, Krzysztof Kozlowski wrote:
> Convert the Exynos Mixer bindings to DT schema format.
>
> The conversion includes also updates to the bindings, matching the
> current DTS and Linux driver:
> 1. Add clocks required on Exynos4210 and Exynos4212 types of Mixer.
> 2.
On Tue, 08 Feb 2022 18:18:19 +0100, Krzysztof Kozlowski wrote:
> Convert the Exynos HDMI DDC bindings to DT schema format.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> .../display/exynos/exynos_hdmiddc.txt | 15 ---
> .../samsung/samsung,exynos-hdmi-ddc.yaml | 42 +
i915_drm.h now defines the format of the returned
DRM_I915_QUERY_HWCONFIG_BLOB query item. Since i915 receives this from
the black box GuC software, it should verify that the data matches
that format before sending it to user-space.
The verification makes a single simple pass through the blob cont
Also, document DRM_I915_QUERY_HWCONFIG_BLOB with this struct.
v3:
* Add various changes suggested by Tvrtko
Cc: Daniel Vetter
Signed-off-by: Jordan Justen
Acked-by: Jon Bloomfield
---
include/uapi/drm/i915_drm.h | 35 +++
1 file changed, 35 insertions(+)
diff
From: Rodrigo Vivi
The DRM_I915_QUERY_HWCONFIG_BLOB query item returns a blob of data
which it receives from the GuC software. This blob provides some
useful data about the hardware for drivers.
Although the blob is not fully documented at this time, the basic
format is an array of u32 values. T
From: John Harrison
Implement support for fetching the hardware description table from the
GuC. The call is made twice - once without a destination buffer to
query the size and then a second time to fill in the buffer.
Note that the table is only available on ADL-P and later platforms.
Cc: Mich
This is John/Rodrigo's 2 patches with some minor changes, and I added
2 patches.
"drm/i915/uapi: Add query for hwconfig blob" was changed:
* Rename DRM_I915_QUERY_HWCONFIG_TABLE to DRM_I915_QUERY_HWCONFIG_BLOB
as requested by Joonas.
* Reword commit message
* I added Acked-by to this patc
On Tue, 08 Feb 2022 18:18:18 +0100, Krzysztof Kozlowski wrote:
> Convert the Exynos7 DECON display controller bindings to DT schema
> format.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> .../bindings/display/exynos/exynos7-decon.txt | 65 --
> .../samsung/samsung,exynos7-decon.yaml
On Tue, 08 Feb 2022 18:18:17 +0100, Krzysztof Kozlowski wrote:
> Convert the Exynos5433 DECON display controller bindings to DT schema
> format.
>
> The conversion includes also updates to the bindings, matching the
> current DTS and Linux driver:
> 1. Require "fifo" interrupt.
> 2. Add "dsd" as a
On Tue, 08 Feb 2022 18:18:16 +0100, Krzysztof Kozlowski wrote:
> Convert the Exynos HDMI PHY bindings to DT schema format and put them
> next to other PHYs.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> .../display/exynos/exynos_hdmiphy.txt | 15 ---
> .../bindings/phy/samsung,exyno
On 14/01/2022 21:57, Rob Clark wrote:
From: Rob Clark
For newer devices which deprecate gpu-id and do matching based on
chip-id, we need this information in cmdstream dumps so that the
decoding tools know how to decode them.
Signed-off-by: Rob Clark
Reviewed-by: Dmitry Baryshkov
---
dr
On 21/12/2021 17:42, cgel@gmail.com wrote:
From: Changcheng Deng
Fix the following coccicheck warning:
./drivers/gpu/drm/msm/msm_debugfs.c: 132: 0-23: WARNING: shrink_fops
should be defined with DEFINE_DEBUGFS_ATTRIBUTE
Use DEFINE_DEBUGFS_ATTRIBUTE rather than DEFINE_SIMPLE_ATTRIBUTE for
d
On 09/02/2022 11:37, Qing Wang wrote:
From: Wang Qing
do_div() does a 64-by-32 division.
When the divisor is u64, do_div() truncates it to 32 bits, this means it
can test non-zero and be truncated to zero for division.
fix do_div.cocci warning:
do_div() does a 64-by-32 division, please conside
On Fri, 04 Feb 2022 14:43:47 +0100, Javier Martinez Canillas wrote:
> The ssd130x DRM driver also makes use of this Device Tree binding to allow
> existing users of the fbdev driver to migrate without the need to change
> their Device Trees.
>
> Add myself as another maintainer of the binding, to
On 01/02/2022 20:47, Daniel Thompson wrote:
Quoting the header comments, IRQF_ONESHOT is "Used by threaded interrupts
which need to keep the irq line disabled until the threaded handler has
been run.". When applied to an interrupt that doesn't request a threaded
irq then IRQF_ONESHOT has a lesser
On 01/02/2022 20:47, Daniel Thompson wrote:
Quoting the header comments, IRQF_ONESHOT is "Used by threaded interrupts
which need to keep the irq line disabled until the threaded handler has
been run.". When applied to an interrupt that doesn't request a threaded
irq then IRQF_ONESHOT has a lesser
On 13/01/2022 17:51, Jami Kettunen wrote:
From: AngeloGioacchino Del Regno
Bringup functionality for MSM8998 in the DPU, driver which is mostly
the same as SDM845 (just a few variations).
Signed-off-by: AngeloGioacchino Del Regno
Signed-off-by: Jami Kettunen
Reviewed-by: Dmitry Baryshkov
From: Alex Bee
RK356x SoCs have a second thermal sensor for the GPU. This adds the
cooling map and trip points for it to make use of its contribution as
a cooling device.
Signed-off-by: Alex Bee
Signed-off-by: Michael Riesch
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 27 ++
Enable the GPU core on the Rockchip RK3568 EVB1.
Signed-off-by: Michael Riesch
---
arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dt
From: Ezequiel Garcia
Enable the GPU core on the Pine64 Quartz64 Model A.
Signed-off-by: Ezequiel Garcia
Signed-off-by: Alex Bee
Signed-off-by: Michael Riesch
---
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/r
Hi all,
This series aims to bring the GPU support for the RK356x mainline. In
conjunction with the VOP2/HDMI TX patches v4 [0]) it has been tested
successfully on a RK3568 EVB1 with weston and glmark2-es2-wayland.
It should be noted that on the RK3568 EVB1 the supply of the GPU power
domain needs
From: Ezequiel Garcia
Rockchip SoCs RK3566 and RK3568 have a Mali Gondul core
which is based on the Bifrost architecture. It has
one shader core and two execution engines.
Quoting the datasheet:
Mali-G52 1-Core-2EE
* Support 1600Mpix/s fill rate when 800MHz clock frequency
* Support 38.4GLOPs w
From: Alex Bee
The Bifrost GPU in Rockchip RK356x SoCs has a core and a bus clock.
Reflect this in the SoC specific part of the binding.
Signed-off-by: Alex Bee
[move the changes to the SoC section]
Signed-off-by: Michael Riesch
---
.../devicetree/bindings/gpu/arm,mali-bifrost.yaml | 15 +
On 02/08, Igor Torrente wrote:
> Hi Melissa,
>
> On 2/8/22 07:40, Melissa Wen wrote:
> > On 01/21, Igor Torrente wrote:
> > > Currently the blend function only accepts XRGB_ and ARGB_
> > > as a color input.
> > >
> > > This patch refactors all the functions related to the plane compositi
On 05/11/2021 06:04, Sean Paul wrote:
From: Sean Paul
This patch adds HDCP 1.x support to msm DP connectors using the new HDCP
helpers.
Sean, is this something that you'd like to pursue further?
We have picked up patches 8-11, which were independent from the rest of
the changes. The rest see
On 2022-02-09 03:40, Christian König wrote:
This is provided by TTM now.
Also switch man->size to bytes instead of pages and fix the double
printing of size and usage in debugfs.
Signed-off-by: Christian König
Tested-by: Bas Nieuwenhuizen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c |
On 2/9/22 19:54, Sam Ravnborg wrote:
> On Wed, Feb 09, 2022 at 08:48:10AM +, cgel@gmail.com wrote:
>> From: Changcheng Deng
>>
>> Use min() in order to make code cleaner.
>>
>> Reported-by: Zeal Robot
>> Signed-off-by: Changcheng Deng
> Reviewed-by: Sam Ravnborg
>
> I had preferred in m
On 2022-02-08 20:39, Yang Li wrote:
Eliminate the following coccicheck warning:
./drivers/gpu/drm/amd/amdkfd/kfd_chardev.c:2087:27-38: ERROR: bo_buckets
is NULL but dereferenced.
Reported-by: Abaci Robot
Signed-off-by: Yang Li
Thank you. I already picket up Tom Rix's patch for the same iss
On Fri, 28 Jan 2022 11:54:36 +0800, Yunfei Dong wrote:
> Adds decoder dt-bindings for mt8195.
>
> Signed-off-by: Yunfei Dong
> Reviewed-by: Macpaul Lin
> ---
> .../bindings/media/mediatek,vcodec-subdev-decoder.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring
On Fri, Jan 28, 2022 at 11:54:34AM +0800, Yunfei Dong wrote:
> Adds decoder dt-bindings for compatible "mediatek,mtk-vcodec-lat-soc".
What's lat soc? How does this relate to what's already there in this
binding.
The subject space is limited, avoid saying the same thing twice
(dt-bindings).
>
On 2022-02-09 09:52, t...@redhat.com wrote:
From: Tom Rix
clang static analysis reports this problem
kfd_chardev.c:2092:2: warning: 1st function call argument
is an uninitialized value
kvfree(bo_privs);
^~~~
When bo_buckets alloc fails, it jumps to an error h
On 2022-02-09 13:09, Dan Carpenter wrote:
If copy_to_user() fails, it returns the number of bytes remaining to
be copied but we want to return a negative error code (-EFAULT) to the
user.
Fixes: 9d5dabfeff3c ("drm/amdkfd: CRIU Save Shared Virtual Memory ranges")
Signed-off-by: Dan Carpenter
Hi Sascha
tested full v5 Series + 3 clk-Patches from v4 on 5.17-rc2 on my rk3568 based
Bananapi R2 Pro
1280x720-32@60Hz
1920x1080-32@60Hz
3840x2160-32@60Hz
with fb console
Tested-by: Frank Wunderlich
regards Frank
On 2/9/22 9:04 AM, Jani Nikula wrote:
> On Wed, 09 Feb 2022, Christoph Hellwig wrote:
>> On Tue, Feb 08, 2022 at 05:15:00PM +0200, Jani Nikula wrote:
#ifdef CONFIG_DRM_I915_GVT
+
+#define D_BDW (1 << 0)
+#define D_SKL (1 << 1)
+#define D_KBL (1 << 2)
+#defi
On 2/9/22 7:28 AM, Christoph Hellwig wrote:
> On Tue, Feb 08, 2022 at 05:15:00PM +0200, Jani Nikula wrote:
>>> #ifdef CONFIG_DRM_I915_GVT
>>> +
>>> +#define D_BDW (1 << 0)
>>> +#define D_SKL (1 << 1)
>>> +#define D_KBL (1 << 2)
>>> +#define D_BXT (1 << 3)
>>> +#define D_CFL (
On 2/9/22 7:32 AM, Christoph Hellwig wrote:
> On Tue, Feb 08, 2022 at 06:11:50AM -0500, Zhi Wang wrote:
>> +struct drm_i915_private *dev_priv = iter->i915;
>> +u32 *mmio, i;
>> +
>> +for (i = offset; i < offset + size; i += 4) {
>> +mmio = iter->data + i;
>> +*mm
Acked-by: Jon Bloomfield
> -Original Message-
> From: Intel-gfx On Behalf Of
> Jordan Justen
> Sent: Tuesday, February 8, 2022 1:05 PM
> To: intel-gfx
> Cc: dri-devel
> Subject: [Intel-gfx] [PATCH v3 0/4] GuC HWCONFIG with documentation
>
> This is John/Rodrigo's 2 patches with some m
On Wed, 09 Feb 2022 14:25:29 +0530, Sankeerth Billakanti wrote:
> Add support for sharp LQ140M1JW46 display panel. It is a 14" eDP panel
> with 1920x1080 display resolution.
>
> Signed-off-by: Sankeerth Billakanti
> ---
>
> Changes in v3:
> None
>
> Documentation/devicetree/bindings/display/
On Wed, 09 Feb 2022 10:53:50 +0100, Sascha Hauer wrote:
> The VOP2 is found on newer Rockchip SoCs like the rk3568 or the rk3566.
> The binding differs slightly from the existing VOP binding, so add a new
> binding file for it.
>
> Signed-off-by: Sascha Hauer
> ---
>
> Notes:
> Changes since
On Wed, Feb 09, 2022 at 08:48:10AM +, cgel@gmail.com wrote:
> From: Changcheng Deng
>
> Use min() in order to make code cleaner.
>
> Reported-by: Zeal Robot
> Signed-off-by: Changcheng Deng
Reviewed-by: Sam Ravnborg
I had preferred in minmax.h was included, but it has an indirect inc
From: Christian König
[ Upstream commit e8ae38720e1a685fd98cfa5ae118c9d07b45ca79 ]
We probably never trigger this, but the logic inside the check is
inverted.
Signed-off-by: Christian König
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/d
From: Christian König
[ Upstream commit e8ae38720e1a685fd98cfa5ae118c9d07b45ca79 ]
We probably never trigger this, but the logic inside the check is
inverted.
Signed-off-by: Christian König
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/d
From: Christian König
[ Upstream commit e8ae38720e1a685fd98cfa5ae118c9d07b45ca79 ]
We probably never trigger this, but the logic inside the check is
inverted.
Signed-off-by: Christian König
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/d
From: Mario Limonciello
[ Upstream commit 04ef860469fda6a646dc841190d05b31fae68e8c ]
This will cause misconfigured systems to not run the GPU suspend
routines.
* In APUs that are properly configured system will go into s2idle.
* In APUs that are intended to be S3 but user selects
s2idle the G
From: Mario Limonciello
[ Upstream commit f52a2b8badbd24faf73a13c9c07fdb9d07352944 ]
This will be used to help make decisions on what to do in
misconfigured systems.
v2: squash in semicolon fix from Stephen Rothwell
Signed-off-by: Mario Limonciello
Reviewed-by: Alex Deucher
Signed-off-by: Al
From: Mario Limonciello
[ Upstream commit a6ed2035878e5ad2e43ed175d8812ac9399d6c40 ]
On some OEM setups users can configure the BIOS for S3 or S2idle.
When configured to S3 users can still choose 's2idle' in the kernel by
using `/sys/power/mem_sleep`. Before commit 6dc8265f9803 ("drm/amdgpu:
al
From: Christian König
[ Upstream commit e8ae38720e1a685fd98cfa5ae118c9d07b45ca79 ]
We probably never trigger this, but the logic inside the check is
inverted.
Signed-off-by: Christian König
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/d
From: Mario Limonciello
[ Upstream commit 04ef860469fda6a646dc841190d05b31fae68e8c ]
This will cause misconfigured systems to not run the GPU suspend
routines.
* In APUs that are properly configured system will go into s2idle.
* In APUs that are intended to be S3 but user selects
s2idle the G
From: Mario Limonciello
[ Upstream commit f52a2b8badbd24faf73a13c9c07fdb9d07352944 ]
This will be used to help make decisions on what to do in
misconfigured systems.
v2: squash in semicolon fix from Stephen Rothwell
Signed-off-by: Mario Limonciello
Reviewed-by: Alex Deucher
Signed-off-by: Al
From: Mario Limonciello
[ Upstream commit a6ed2035878e5ad2e43ed175d8812ac9399d6c40 ]
On some OEM setups users can configure the BIOS for S3 or S2idle.
When configured to S3 users can still choose 's2idle' in the kernel by
using `/sys/power/mem_sleep`. Before commit 6dc8265f9803 ("drm/amdgpu:
al
It is illegal to add a dma_fence_chain as timeline point. Flatten out
the fences into a dma_fence_array instead.
Signed-off-by: Christian König
---
drivers/gpu/drm/drm_syncobj.c | 61 ---
1 file changed, 56 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/d
If copy_to_user() fails, it returns the number of bytes remaining to
be copied but we want to return a negative error code (-EFAULT) to the
user.
Fixes: 9d5dabfeff3c ("drm/amdkfd: CRIU Save Shared Virtual Memory ranges")
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 6 +
The kfd_process_device_data_by_id() does not return error pointers,
it returns NULL.
Fixes: bef153b70c6e ("drm/amdkfd: CRIU implement gpu_id remapping")
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/d
All comments are fixed and code pushed. Thanks for everyone
who helped reviewing.
Andrey
On 2022-02-09 02:53, Christian König wrote:
Am 09.02.22 um 01:23 schrieb Andrey Grodzovsky:
Before we initialize schedulers we must know which reset
domain are we in - for single device there iis a single
On Wed, Feb 09, 2022 at 09:51:06AM +0100, Michael Riesch wrote:
> From: Alex Bee
>
> The Bifrost GPU in Rockchip RK356x SoCs has a core and a bus clock.
> Reflect this in the SoC specific part of the binding.
>
> Signed-off-by: Alex Bee
> [move the changes to the SoC section]
> Signed-off-by: M
Hi Sascha
tested full v5 Series + 3 clk-Patches from v4 on 5.17-rc2 on my rk3568 based
Bananapi R2 Pro
1280x720-32@60Hz
1920x1080-32@60Hz
3840x2160-32@60Hz
with fb console
Tested-by: Frank Wunderlich
regards Frank
On Wed, Feb 09, 2022 at 05:28:05PM +0100, Heiko Stübner wrote:
> Hi Michael,
>
> Am Mittwoch, 9. Februar 2022, 16:46:28 CET schrieb Michael Riesch:
> > Hi Rob,
> >
> > On 2/9/22 16:35, Rob Herring wrote:
> > > On Wed, 09 Feb 2022 09:51:06 +0100, Michael Riesch wrote:
> > >> From: Alex Bee
> > >>
Hi!
Dne sreda, 09. februar 2022 ob 06:53:27 CET je Pin-Yen Lin napisal(a):
> The length of EDID block can be longer than 256 bytes, so we should use
> `int` instead of `u8` for the `edid_pos` variable.
>
> Signed-off-by: Pin-Yen Lin
Please add "Fixes" tag. With that:
Reviewed-by: Jernej Skrabec
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