Dear Richard,
Am 21.04.22 um 03:12 schrieb Gong, Richard:
On 4/20/2022 3:29 PM, Paul Menzel wrote:
Am 19.04.22 um 23:46 schrieb Gong, Richard:
On 4/14/2022 2:52 AM, Paul Menzel wrote:
[Cc: -kernel test robot ]
[…]
Am 13.04.22 um 15:00 schrieb Alex Deucher:
On Wed, Apr 13, 2022 at
On Thu, 2022-04-21 at 08:12 +0300, Maxim Levitsky wrote:
> ---
> arch/x86/kvm/mmu/mmu.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
> index 23f895d439cf5..b63398dfdac3b 100644
> --- a/arch/x86/kvm/mmu/mmu.c
> +++
* Arnd Bergmann [220420 19:18]:
> On Wed, Apr 20, 2022 at 3:46 PM Aaro Koskinen wrote:
> >
> > Hi,
> >
> > On Tue, Apr 19, 2022 at 03:37:08PM +0200, Arnd Bergmann wrote:
> > > From: Arnd Bergmann
> > >
> > > The address range 0xfee0-0xfeff is used for PCI and
> > > PCMCIA I/O port
Allow optionally to make KVM not update is_running unless it is
functionally needed which is only when a vCPU halts,
or is in the guest mode.
This means security wise that if a vCPU is scheduled out,
other vCPUs could still send doorbell messages to the
last physical CPU where this vCPU was last
This implements initial support of using the AVIC in a nested guest
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/avic.c | 850 +-
arch/x86/kvm/svm/nested.c | 131 +-
arch/x86/kvm/svm/svm.c| 18 +
arch/x86/kvm/svm/svm.h| 150 +++
This will be used on SVM to reload shadow page of the AVIC physid table
No functional change intended
Signed-off-by: Maxim Levitsky
---
arch/x86/include/asm/kvm-x86-ops.h | 2 +-
arch/x86/include/asm/kvm_host.h| 3 +--
arch/x86/kvm/vmx/vmx.c | 8
arch/x86/kvm/x86.c
This will make the code a bit easier to read when nested AVIC support
is added.
No functional change intended.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/avic.c | 49 +++--
arch/x86/kvm/svm/svm.h | 14 +++-
2 files changed, 36 insertions(+),
Now that KVM doesn't allow to change APIC ID in case AVIC is
enabled, remove buggy AVIC code that tried to do so.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/avic.c | 35 ---
1 file changed, 35 deletions(-)
diff --git a/arch/x86/kvm/svm/avic.c
No normal guest has any reason to change physical APIC IDs, and
allowing this introduces bugs into APIC acceleration code.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/lapic.c | 28 +++-
1 file changed, 23 insertions(+), 5 deletions(-)
diff --git
---
arch/x86/kvm/mmu/mmu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index 23f895d439cf5..b63398dfdac3b 100644
--- a/arch/x86/kvm/mmu/mmu.c
+++ b/arch/x86/kvm/mmu/mmu.c
@@ -5315,8 +5315,8 @@ int
This is a tiny refactoring, and can be useful to check
if a GPA/GFN is within a memslot a bit more cleanly.
Signed-off-by: Maxim Levitsky
---
include/linux/kvm_host.h | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/include/linux/kvm_host.h
This allows to enable the write tracking only when KVMGT is
actually used and doesn't carry any penalty otherwise.
Tested by booting a VM with a kvmgt mdev device.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/Kconfig | 3 ---
arch/x86/kvm/mmu/mmu.c | 2 +-
This will be used to enable write tracking from nested AVIC code
and can also be used to enable write tracking in GVT-g module
when it actually uses it as opposed to always enabling it,
when the module is compiled in the kernel.
No functional change intended.
Signed-off-by: Maxim Levitsky
---
This patch series implement everything that is needed to
use AMD's AVIC while a nested guest is running including
ability of the nested guest to use it, and brings feature
parity vs APICv.
Compared to v1 of the series, there are lot of fixes,
and refactoring.
This version still use unconditional
Adding support for writeback transcoder to start capturing frames using
interrupt mechanism
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_acpi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 89 +-
Adding WD Types, WD transcoder to enum list and WD Transcoder offsets
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_display.h | 6 ++
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/i915_reg.h| 2 ++
3 files
Changes to create a i915 private pipeline to enable the WD transcoder
without relying on the current drm_writeback framework.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/display/intel_display_types.h| 4 +
A patch series was floated in the drm mailing list which aimed to change
the drm_connector and drm_encoder fields to pointer in the
drm_connector_writeback structure, this received a huge pushback from
the community but since i915 expects each connector present in the
drm_device list to be a
On 4/20/22 8:00 PM, Jason Gunthorpe wrote:
> On Wed, Apr 20, 2022 at 02:46:00PM -0300, Jason Gunthorpe wrote:
>> On Wed, Apr 20, 2022 at 11:40:33AM -0600, Alex Williamson wrote:
>>> On Wed, 20 Apr 2022 13:43:51 -0300
>>> Jason Gunthorpe wrote:
>>>
On Wed, Apr 20, 2022 at 04:34:47PM +,
It's typical for the bootloader to bring up the display for showing a
boot splash or efi framebuffer. But in some cases the kernel driver ends
up only partially configuring (in particular) the DPU, which might
result in e.g. that two different data paths attempts to push data to
the interface -
Add an optional reference to the MDSS_CORE reset, which when specified
can be used by the implementation to reset the hardware blocks.
Reviewed-by: Dmitry Baryshkov
Acked-by: Krzysztof Kozlowski
Signed-off-by: Bjorn Andersson
---
Changes since v3:
- None
[AMD Official Use Only]
From: Kuehling, Felix
Sent: Thursday, April 21, 2022 5:21 AM
To: Lazar, Lijo ; Koenig, Christian
; Wang, Yang(Kevin) ;
Christian König ;
dri-devel@lists.freedesktop.org ;
amd-...@lists.freedesktop.org
Subject: Re: [PATCH] drm/ttm:
On Wed, Mar 09, 2022 at 10:58:09AM -0500, Alex Deucher wrote:
On Mon, Mar 7, 2022 at 3:30 PM Niranjana Vishwanathapura
wrote:
VM_BIND design document with description of intended use cases.
Signed-off-by: Niranjana Vishwanathapura
---
Documentation/gpu/rfc/i915_vm_bind.rst | 210
Hi Paul,
On 4/20/2022 3:29 PM, Paul Menzel wrote:
Dear Richard,
Am 19.04.22 um 23:46 schrieb Gong, Richard:
On 4/14/2022 2:52 AM, Paul Menzel wrote:
[Cc: -kernel test robot ]
[…]
Am 13.04.22 um 15:00 schrieb Alex Deucher:
On Wed, Apr 13, 2022 at 3:43 AM Paul Menzel wrote:
Thank you
On 4/20/2022 3:58 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-04-15 17:06:48)
On 4/14/2022 4:34 PM, Dmitry Baryshkov wrote:
I'm not sure how should the driver react if the client doesn't disable
the output, but then the sink gets reattached?
I do not know that either.
But it should
add dpu encoder APIs to prepare and cleanup writeback job
for the writeback encoder. These shall be invoked from the
prepare_wb_job/cleanup_wb_job hooks of the drm_writeback
framework.
changes in v3:
- none
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
kms_writeback test cases also verify with a null fb for the
writeback connector job. In addition there are also other
commit paths which can result in kickoffs without a valid
framebuffer like while closing the fb which results in the
callback to drm_atomic_helper_dirtyfb() which internally
Add writeback block information while capturing the display
snapshot.
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
Make changes to dpu_encoder to support virtual encoder needed
to support writeback for dpu.
changes in v3:
- fix a debug print statement
- leave a FIXME comment to separate intf_idx and wb_idx
- leave a TODO to improve the dpu_encoder_helper_phys_cleanup()
Signed-off-by:
Add a reset_intf_cfg operation for dpu_hw_ctl to reset the
entire CTL path by disabling each component namely layer mixer,
3d-merge and interface blocks.
changes in v3:
- none
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c |
_dpu_plane_get_qos_lut() is not specific to just dpu_plane.
It can take any fill level and return the LUT matching it.
This can be used even for other modules like dpu_writeback.
Move _dpu_plane_get_qos_lut() to the common dpu_hw_util file
and rename it to _dpu_hw_get_qos_lut().
Signed-off-by:
Initialize dpu encoder and connector for writeback if the
target supports it in the catalog.
changes in v2:
- start initialing the encoder for writeback since we
have migrated to using drm_writeback_connector_init_with_encoder()
- instead of checking for WB_2 inside
Add changes to support writeback module in the dpu_hw_ctl
interface.
changes in v3:
- read the intf_active and wb_active before writing
to preserve existing bits
- add the update_pending_flush_wb for non-v1 targets
Signed-off-by: Abhinav Kumar
---
Introduce the dpu_writeback module which serves as the
interface between dpu operations and the drm_writeback.
This module manages the connector related operations for
dpu writeback.
changes in v2:
- start using drm_writeback_connector_init_with_encoder()
- drop unnecessary
Add the dpu_hw_wb abstraction to program registers related to the
writeback block. These will be invoked once all the configuration
is set and ready to be programmed to the registers.
changes in v3:
- start using the common struct dpu_hw_cdp_cfg
- leave a comment about DPU
Add an API to reset the encoder related hw blocks to ensure
a proper teardown of the pipeline. At the moment this is being
used only for the writeback encoder but eventually we can start
using this for all interfaces.
changes in v3:
- none
Signed-off-by: Abhinav Kumar
Reviewed-by:
Add writeback blocks to DPU resource manager so that
the encoders can directly request them through RM.
changes in v3:
- use IS_ERR() instead of IS_ERR_OR_NULL()
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 22 ++
Rename dpu_hw_pipe_cdp_cfg to dpu_hw_cdp_cfg and move it
to dpu_hw_utils file so that other modules in addition to
SSPP such as writeback can use it as all the fields can
be used by writeback as well.
Suggested-by: Dmitry Baryshkov
Signed-off-by: Abhinav Kumar
---
Introduce the dpu_encoder_phys_* for the writeback interface
to handle writeback specific hardware programming.
changes in v3:
- start using the now generic struct dpu_hw_cdp_cfg
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Makefile
Add writeback blocks to the sm8250 DPU hardware catalog. Other
chipsets support writeback too but add it to sm8250 to prototype
the feature so that it can be easily extended to other chipsets.
changes in v3:
- none
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
For vendors drivers which pass an already allocated and
initialized encoder especially for cases where the encoder
hardware is shared OR the writeback encoder shares the resources
with the rest of the display pipeline introduce a new API,
drm_writeback_connector_init_with_encoder() which expects
For some vendor driver implementations, display hardware can
be shared between the encoder used for writeback and the physical
display.
In addition resources such as clocks and interrupts can
also be shared between writeback and the real encoder.
To accommodate such vendor drivers and hardware,
This series adds support for writeback block on DPU. Writeback
block is extremely useful to validate boards having no physical displays
in addition to many other use-cases where we want to get the output
of the display pipeline to examine whether issue is with the display
pipeline or with the
Clients of drm_writeback_connector_init() initialize the
possible_crtcs and then invoke the call to this API.
To simplify things, allow passing possible_crtcs as a parameter
to drm_writeback_connector_init() and make changes to the
other drm drivers to make them compatible with this change.
On Wed 20 Apr 16:12 PDT 2022, Bjorn Andersson wrote:
Sorry, I missed Jagan and Linus, author and reviewer of the reverted
patch 2, among the recipients.
Regards,
Bjorn
> Commit '80253168dbfd ("drm: of: Lookup if child node has panel or
> bridge")' introduced the ability to describe a panel
Commit '80253168dbfd ("drm: of: Lookup if child node has panel or
bridge")' attempted to simplify the case of expressing a simple panel
under a DSI controller, by assuming that the first non-graph child node
was a panel or bridge.
Unfortunately for non-trivial cases the first child node might not
Commit '80253168dbfd ("drm: of: Lookup if child node has panel or
bridge")' introduced the ability to describe a panel under a display
controller without having to use a graph to connect the controller to
its single child panel (or bridge).
The implementation of this would find the first
Hey! Figured I'd check if there's been any status updates here since it's been
a while, just to make sure I haven't dropped this issue from my radar. No
problem if you're busy :)
On Wed, 2022-03-16 at 10:46 +, Lin, Wayne wrote:
> [Public]
>
> > -Original Message-
> > From: Lyude Paul
Quoting Kuogee Hsieh (2022-04-15 17:06:48)
>
> On 4/14/2022 4:34 PM, Dmitry Baryshkov wrote:
> >
> > I'm not sure how should the driver react if the client doesn't disable
> > the output, but then the sink gets reattached?
>
> I do not know that either.
>
> But it should not happen as long as
On Thu, Mar 31, 2022 at 01:37:08PM +0200, Daniel Vetter wrote:
One thing I've forgotten, since it's only hinted at here: If/when we
switch tlb flushing from the current dumb implementation
we now have in i915 in upstream to one with batching using dma_fence,
then I think that should be something
On Thu, Mar 31, 2022 at 10:28:48AM +0200, Daniel Vetter wrote:
Adding a pile of people who've expressed interest in vm_bind for their
drivers.
Also note to the intel folks: This is largely written with me having my
subsystem co-maintainer hat on, i.e. what I think is the right thing to do
here
On 21/04/2022 00:28, Abhinav Kumar wrote:
On 4/20/2022 12:23 AM, Dmitry Baryshkov wrote:
On 20/04/2022 04:46, Abhinav Kumar wrote:
Add an API to reset the encoder related hw blocks to ensure
a proper teardown of the pipeline. At the moment this is being
used only for the writeback encoder
The smu_v1X_0_set_allowed_mask() uses bitmap_copy() to convert
bitmap to 32-bit array. This may be wrong due to endianness issues.
Fix it by switching to bitmap_{from,to}_arr32.
Signed-off-by: Yury Norov
---
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 2 +-
On 21/04/2022 01:06, Abhinav Kumar wrote:
Hi Dmitry
On 4/20/2022 11:46 AM, Abhinav Kumar wrote:
On 4/20/2022 11:37 AM, Dmitry Baryshkov wrote:
On Wed, 20 Apr 2022 at 20:41, Abhinav Kumar
wrote:
On 4/20/2022 12:44 AM, Dmitry Baryshkov wrote:
On 20/04/2022 04:46, Abhinav Kumar wrote:
Quoting Kuogee Hsieh (2022-04-14 14:03:43)
> Two stages are required to setup up main link to be ready to transmit
> video stream.
> Stage 1: dp_hpd_plug_handle() perform link training to set up main link
> stage 2: user space framework (msm_dp_display_enable()) to enable pixel
> clock and
Hi Dmitry
On 4/20/2022 11:46 AM, Abhinav Kumar wrote:
On 4/20/2022 11:37 AM, Dmitry Baryshkov wrote:
On Wed, 20 Apr 2022 at 20:41, Abhinav Kumar
wrote:
On 4/20/2022 12:44 AM, Dmitry Baryshkov wrote:
On 20/04/2022 04:46, Abhinav Kumar wrote:
Make changes to dpu_encoder to support
On Wed, Apr 20, 2022 at 10:05:34AM +0300, Tomi Valkeinen wrote:
> Hi,
>
> On 19/04/2022 17:20, Rob Herring wrote:
> > On Tue, Apr 19, 2022 at 12:33:01PM +0530, Aradhya Bhatia wrote:
> > > The DSS IP on the ti-am65x soc supports an additional register space,
> > > named "common1". Further. the IP
On 4/20/2022 12:23 AM, Dmitry Baryshkov wrote:
On 20/04/2022 04:46, Abhinav Kumar wrote:
Add an API to reset the encoder related hw blocks to ensure
a proper teardown of the pipeline. At the moment this is being
used only for the writeback encoder but eventually we can start
using this for
On 2022-04-20 09:23, Lazar, Lijo wrote:
On 4/20/2022 6:26 PM, Christian König wrote:
Am 20.04.22 um 14:54 schrieb Wang, Yang(Kevin):
[AMD Official Use Only]
Hi Chris,
1) Change the test case to use something larger than 1TiB.
sure, we can increase the size of BO and make test pass,
but
[Public]
> -Original Message-
> From: Alex Deucher
> Sent: Wednesday, April 20, 2022 16:14
> To: Paul Menzel
> Cc: Gong, Richard ; Dave Airlie ;
> Pan, Xinhui ; LKML ;
> Maling list - DRI developers ; amd-gfx list
> ; Daniel Vetter ; Deucher,
> Alexander ; Koenig, Christian
> ;
On Wed, Apr 20, 2022 at 5:13 PM Gong, Richard wrote:
>
>
> On 4/20/2022 4:02 PM, Paul Menzel wrote:
> > Dear Richard,
> >
> >
> > Am 20.04.22 um 22:56 schrieb Gong, Richard:
> >
> >> On 4/20/2022 3:48 PM, Paul Menzel wrote:
> >
> >>> Am 20.04.22 um 22:40 schrieb Alex Deucher:
> On Wed, Apr
On Wed, Apr 20, 2022 at 5:02 PM Paul Menzel wrote:
>
> Dear Richard,
>
>
> Am 20.04.22 um 22:56 schrieb Gong, Richard:
>
> > On 4/20/2022 3:48 PM, Paul Menzel wrote:
>
> >> Am 20.04.22 um 22:40 schrieb Alex Deucher:
> >>> On Wed, Apr 20, 2022 at 4:29 PM Paul Menzel
> >>> wrote:
> >>
> Am
On 4/20/2022 4:02 PM, Paul Menzel wrote:
Dear Richard,
Am 20.04.22 um 22:56 schrieb Gong, Richard:
On 4/20/2022 3:48 PM, Paul Menzel wrote:
Am 20.04.22 um 22:40 schrieb Alex Deucher:
On Wed, Apr 20, 2022 at 4:29 PM Paul Menzel
wrote:
Am 19.04.22 um 23:46 schrieb Gong, Richard:
On
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: f1244c81da13009dbf61cb807f45881501c44789 Add linux-next specific
files for 20220420
Error/Warning reports:
https://lore.kernel.org/linux-mm/202204081656.6x4pfen4-...@intel.com
https
Dear Richard,
Am 20.04.22 um 22:56 schrieb Gong, Richard:
On 4/20/2022 3:48 PM, Paul Menzel wrote:
Am 20.04.22 um 22:40 schrieb Alex Deucher:
On Wed, Apr 20, 2022 at 4:29 PM Paul Menzel
wrote:
Am 19.04.22 um 23:46 schrieb Gong, Richard:
On 4/14/2022 2:52 AM, Paul Menzel wrote:
[Cc:
Hi Paul,
On 4/20/2022 3:48 PM, Paul Menzel wrote:
Dear Alex,
Am 20.04.22 um 22:40 schrieb Alex Deucher:
On Wed, Apr 20, 2022 at 4:29 PM Paul Menzel
wrote:
Am 19.04.22 um 23:46 schrieb Gong, Richard:
On 4/14/2022 2:52 AM, Paul Menzel wrote:
[Cc: -kernel test robot ]
[…]
Am 13.04.22
On Tue, Apr 5, 2022 at 10:01 AM Thierry Reding wrote:
>
> On Fri, Apr 01, 2022 at 09:44:46AM +0200, Paul Kocialkowski wrote:
> > Hi Bjorn,
> >
> > On Thu 31 Mar 22, 20:16, Bjorn Andersson wrote:
> > > On Tue 29 Mar 06:27 PDT 2022, Paul Kocialkowski wrote:
> > >
> > > > While bridge/panel
On Thu, Apr 14, 2022 at 10:19 AM xiazhengqiao
wrote:
> Add dt-bindings for 10.1" TFT LCD module called STARRY 2081101
> QFH032011-53G.
>
> Signed-off-by: xiazhengqiao
> Reviewed-by: Rob Herring
(...)
> + enable-gpios:
> +description: a GPIO spec for the enable pin
The way this is used
Dear Alex,
Am 20.04.22 um 22:40 schrieb Alex Deucher:
On Wed, Apr 20, 2022 at 4:29 PM Paul Menzel wrote:
Am 19.04.22 um 23:46 schrieb Gong, Richard:
On 4/14/2022 2:52 AM, Paul Menzel wrote:
[Cc: -kernel test robot ]
[…]
Am 13.04.22 um 15:00 schrieb Alex Deucher:
On Wed, Apr 13,
On Thu, Apr 14, 2022 at 10:19 AM xiazhengqiao
wrote:
> Add STARRY 2081101QFH032011-53G 10.1" WUXGA TFT LCD panel
>
> Signed-off-by: xiazhengqiao
> Tested-by: Hsin-Yi Wang
> Reviewed-by: Hsin-Yi Wang
OK cool... Do you know the name of the display controller
used in this panel? We tend to name
On Wed, Apr 20, 2022 at 4:29 PM Paul Menzel wrote:
>
> Dear Richard,
>
>
> Am 19.04.22 um 23:46 schrieb Gong, Richard:
>
> > On 4/14/2022 2:52 AM, Paul Menzel wrote:
> >> [Cc: -kernel test robot ]
>
> […]
>
> >> Am 13.04.22 um 15:00 schrieb Alex Deucher:
> >>> On Wed, Apr 13, 2022 at 3:43 AM Paul
Dear Richard,
Am 19.04.22 um 23:46 schrieb Gong, Richard:
On 4/14/2022 2:52 AM, Paul Menzel wrote:
[Cc: -kernel test robot ]
[…]
Am 13.04.22 um 15:00 schrieb Alex Deucher:
On Wed, Apr 13, 2022 at 3:43 AM Paul Menzel wrote:
Thank you for sending out v4.
Am 12.04.22 um 23:50 schrieb
On Wed, Mar 30, 2022 at 02:51:41PM +0200, Daniel Vetter wrote:
On Mon, Mar 07, 2022 at 12:31:46PM -0800, Niranjana Vishwanathapura wrote:
VM_BIND und related uapi definitions
Signed-off-by: Niranjana Vishwanathapura
---
Documentation/gpu/rfc/i915_vm_bind.h | 176 +++
Hi Dave & Daniel,
One more fix for v5.18.. actually a revert to fix iommu breakage on
older devices
The following changes since commit 390d645877ffd6dcb55f162d618045b2779217b3:
drm/msm/gpu: Avoid -Wunused-function with !CONFIG_PM_SLEEP
(2022-04-11 18:35:31 -0700)
are available in the Git
On Wed, Apr 20, 2022 at 02:46:00PM -0300, Jason Gunthorpe wrote:
> On Wed, Apr 20, 2022 at 11:40:33AM -0600, Alex Williamson wrote:
> > On Wed, 20 Apr 2022 13:43:51 -0300
> > Jason Gunthorpe wrote:
> >
> > > On Wed, Apr 20, 2022 at 04:34:47PM +, Wang, Zhi A wrote:
> > > > Hi folks:
> > > >
On Wed, Apr 20, 2022 at 7:08 PM Aaro Koskinen wrote:
> On Tue, Apr 19, 2022 at 03:36:42PM +0200, Arnd Bergmann wrote:
> > From: Arnd Bergmann
> >
> > This is the full series for converting OMAP1 to multiplatform, rebased
> > from my 2019 attempt to do the same thing. The soc tree contains
This driver supports the MIPI DSI encoder found in the RZ/G2L
SoC. It currently supports DSI mode only.
Signed-off-by: Biju Das
---
v2->v3:
* pass rzg2l_mipi_dsi pointer to {Link,Phy} register rd/wr function instead
of the memory pointer
* Fixed the comment in rzg2l_mipi_dsi_startup()
*
The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It
can operate in DSI mode, with up to four data lanes.
Signed-off-by: Biju Das
Reviewed-by: Rob Herring
Reviewed-by: Laurent Pinchart
Reviewed-by: Geert Uytterhoeven
---
v2->v3:
* Added Rb tag from Geert and Laurent
*
This patch series aims to support the MIPI DSI encoder found in the RZ/G2L
SoC. It currently supports DSI mode only.
This unit supports MIPI Alliance Specification for Display Serial Interface
(DSI) Specification. This unit provides a
solution for transmitting MIPI DSI compliant digital video
On Wed, 20 Apr 2022 at 22:36, Abhinav Kumar wrote:
>
>
>
> On 4/20/2022 12:26 PM, Dmitry Baryshkov wrote:
> > On 20/04/2022 21:17, Abhinav Kumar wrote:
> >>
> >>
> >> On 4/20/2022 12:49 AM, Dmitry Baryshkov wrote:
> >>> On 20/04/2022 04:46, Abhinav Kumar wrote:
> Introduce the
On 4/20/2022 12:26 PM, Dmitry Baryshkov wrote:
On 20/04/2022 21:17, Abhinav Kumar wrote:
On 4/20/2022 12:49 AM, Dmitry Baryshkov wrote:
On 20/04/2022 04:46, Abhinav Kumar wrote:
Introduce the dpu_encoder_phys_* for the writeback interface
to handle writeback specific hardware
On Wed, 2022-04-20 at 20:56 +0200, Christian König wrote:
> ⚠ External Email
>
> Am 20.04.22 um 20:49 schrieb Christian König:
> > Am 20.04.22 um 20:41 schrieb Zack Rusin:
> > > On Wed, 2022-04-20 at 19:40 +0200, Christian König wrote:
> > > > Am 20.04.22 um 19:38 schrieb Zack Rusin:
> > > > > On
On 20/04/2022 04:46, Abhinav Kumar wrote:
Introduce the dpu_writeback module which serves as the
interface between dpu operations and the drm_writeback.
This module manages the connector related operations for
dpu writeback.
changes in v2:
- start using
On 20/04/2022 22:10, Abhinav Kumar wrote:
On 4/20/2022 12:52 AM, Dmitry Baryshkov wrote:
On 20/04/2022 04:46, Abhinav Kumar wrote:
Introduce the dpu_writeback module which serves as the
interface between dpu operations and the drm_writeback.
This module manages the connector related
On 20/04/2022 21:17, Abhinav Kumar wrote:
On 4/20/2022 12:49 AM, Dmitry Baryshkov wrote:
On 20/04/2022 04:46, Abhinav Kumar wrote:
Introduce the dpu_encoder_phys_* for the writeback interface
to handle writeback specific hardware programming.
changes in v2:
- rebase on msm-next and fix
On Wed, Apr 20, 2022 at 3:46 PM Aaro Koskinen wrote:
>
> Hi,
>
> On Tue, Apr 19, 2022 at 03:37:08PM +0200, Arnd Bergmann wrote:
> > From: Arnd Bergmann
> >
> > The address range 0xfee0-0xfeff is used for PCI and
> > PCMCIA I/O port mappings, but OMAP1 has its static mappings
> > there as
On 4/20/2022 12:52 AM, Dmitry Baryshkov wrote:
On 20/04/2022 04:46, Abhinav Kumar wrote:
Introduce the dpu_writeback module which serves as the
interface between dpu operations and the drm_writeback.
This module manages the connector related operations for
dpu writeback.
changes in v2:
Am 20.04.22 um 20:49 schrieb Christian König:
Am 20.04.22 um 20:41 schrieb Zack Rusin:
On Wed, 2022-04-20 at 19:40 +0200, Christian König wrote:
Am 20.04.22 um 19:38 schrieb Zack Rusin:
On Wed, 2022-04-20 at 09:37 +0200, Christian König wrote:
⚠ External Email
Hi Zack,
Am 20.04.22 um 05:56
Am 20.04.22 um 20:41 schrieb Zack Rusin:
On Wed, 2022-04-20 at 19:40 +0200, Christian König wrote:
Am 20.04.22 um 19:38 schrieb Zack Rusin:
On Wed, 2022-04-20 at 09:37 +0200, Christian König wrote:
⚠ External Email
Hi Zack,
Am 20.04.22 um 05:56 schrieb Zack Rusin:
On Thu, 2022-04-07 at
On Wed, 20 Apr 2022 at 21:11, Abhinav Kumar wrote:
>
> Hi Dmitry
>
> Sorry, I missed answering one question.
>
> On 4/20/2022 10:49 AM, Dmitry Baryshkov wrote:
> > On Wed, 20 Apr 2022 at 20:01, Abhinav Kumar
> > wrote:
> >>
> >>
> >>
> >> On 4/20/2022 12:20 AM, Dmitry Baryshkov wrote:
> >>> On
On Wed, 20 Apr 2022 at 20:16, Abhinav Kumar wrote:
>
>
>
> On 4/19/2022 11:59 PM, Dmitry Baryshkov wrote:
> > On 20/04/2022 04:46, Abhinav Kumar wrote:
> >> Add changes to support writeback module in the dpu_hw_ctl
> >> interface.
> >>
> >> changes in v2:
> >> - keep only the wb specific
On 4/20/2022 11:37 AM, Dmitry Baryshkov wrote:
On Wed, 20 Apr 2022 at 20:41, Abhinav Kumar wrote:
On 4/20/2022 12:44 AM, Dmitry Baryshkov wrote:
On 20/04/2022 04:46, Abhinav Kumar wrote:
Make changes to dpu_encoder to support virtual encoder needed
to support writeback for dpu.
From: Martin Krastev
From: Zack Rusin
Date: Wed, 20 Apr 2022 at 07:03
Subject: [PATCH v2] drm/vmwgfx: Fix gem refcounting and memory evictions
To:
Cc: ,
From: Zack Rusin
v2: Add the last part of the ref count fix which was spotted by
Philipp Sieweck where the ref count of cpu writers
On Wed, 2022-04-20 at 19:40 +0200, Christian König wrote:
>
> Am 20.04.22 um 19:38 schrieb Zack Rusin:
> > On Wed, 2022-04-20 at 09:37 +0200, Christian König wrote:
> > > ⚠ External Email
> > >
> > > Hi Zack,
> > >
> > > Am 20.04.22 um 05:56 schrieb Zack Rusin:
> > > > On Thu, 2022-04-07 at
On Wed, 20 Apr 2022 at 20:41, Abhinav Kumar wrote:
>
>
>
> On 4/20/2022 12:44 AM, Dmitry Baryshkov wrote:
> > On 20/04/2022 04:46, Abhinav Kumar wrote:
> >> Make changes to dpu_encoder to support virtual encoder needed
> >> to support writeback for dpu.
> >>
> >> changes in v2:
> >> - add the
On 4/20/2022 12:49 AM, Dmitry Baryshkov wrote:
On 20/04/2022 04:46, Abhinav Kumar wrote:
Introduce the dpu_encoder_phys_* for the writeback interface
to handle writeback specific hardware programming.
changes in v2:
- rebase on msm-next and fix related dependencies namely
the irq
Ensure we check that the size is compatible with the requested
page_size. For tiny objects that are automatically annotated with
TTM_PL_FLAG_CONTIGUOUS(since they fit within a single page), we
currently end up silently overriding the min_page_size, which ends up
hiding bugs elsewhere.
Trying to cast the region id into the region type doesn't work too well,
since the i915_vm_min_alignment() won't give us the correct value for
the stolen-lmem case.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Nirmoy Das
Cc: Ramalingam C
---
The compact-pt layout restrictions should only apply to the ppGTT. Also
make this play nice on platforms that only have the 64K GTT restriction,
and not the compact-pt thing.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Nirmoy Das
Cc: Ramalingam C
---
We can only force migrate an object if the existing object size is
compatible with the new destinations min_page_size for the region.
Currently we blow up with something like:
[ 2857.497462] kernel BUG at drivers/gpu/drm/i915/gt/intel_migrate.c:431!
[ 2857.497497] invalid opcode: [#1]
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