On Tue, Jan 03, 2023 at 12:36:51AM +0200, Abel Vesa wrote:
> On 23-01-02 09:21:40, Johan Hovold wrote:
> > On Sun, Jan 01, 2023 at 10:58:42PM -0600, Steev Klimaszewski wrote:
> > > On Sat, Dec 31, 2022 at 8:27 AM Abel Vesa wrote:
> > > >
> > > > The actual name is R133NW4K-R0.
> > > >
> > > > Fixe
Add document vendor prefix for Microtips Technology USA (microtips).
Signed-off-by: Aradhya Bhatia
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml
b/Documentation/devicetree/b
Add document vendor prefix for Lincoln Technology Solutions
(lincolntech).
Signed-off-by: Aradhya Bhatia
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml
b/Documentation/device
Dual-link LVDS interfaces have 2 links, with even pixels traveling on
one link, and odd pixels on the other. These panels are also generic in
nature, with no documented constraints, much like their single-link
counterparts, "panel-lvds".
Add a new compatible, "panel-dual-lvds", and a dt-binding do
Add a new compatible, "panel-dual-lvds".
Dual-link LVDS interfaces have 2 links, with even pixels traveling on
one link, and odd pixels on the other. These panels are also generic in
nature, with no documented constraints, much like their single-link
counterparts, "panel-lvds".
Signed-off-by: Ara
Hi all,
Microtips Technology Solutions USA, and Lincoln Technology Solutions are
2 display panel vendors, and the first 2 patches add their vendor
prefixes.
The fourth patch, simply introduces the new compatible for the generic
dual-link panels in the panel-lvds driver. This new compatible is bas
On Wed, Dec 28, 2022 at 06:18:12AM -0500, Rodrigo Vivi wrote:
> On Tue, Dec 27, 2022 at 11:36:13PM +0530, Deepak R Varma wrote:
> > On Tue, Dec 27, 2022 at 12:13:56PM -0500, Rodrigo Vivi wrote:
> > > On Tue, Dec 27, 2022 at 01:30:53PM +0530, Deepak R Varma wrote:
> > > > Using DEFINE_SIMPLE_ATTRIBU
From: Kamil Trzciński
The driver is for panels based on the Himax HX8394 controller, such as the
HannStar HSD060BHW4 720x1440 TFT LCD panel that uses a MIPI-DSI interface.
Signed-off-by: Kamil Trzciński
Co-developed-by: Ondrej Jirman
Signed-off-by: Ondrej Jirman
Co-developed-by: Javier Martin
Add myself as maintainer for the driver and devicetree bindings schema.
Signed-off-by: Javier Martinez Canillas
Acked-by: Sam Ravnborg
---
Changes in v5:
- List Ondrej Jirman as a maintainer in the driver's MAINTAINERS entry.
Changes in v4:
- Add Sam Ravnborg's Acked-by tag.
MAINTAINERS | 8
Add device tree bindings for panels based on the Himax HX8394 controller,
such as the HannStar HSD060BHW4 720x1440 TFT LCD panel that is connected
through a MIPI-DSI video interface.
Signed-off-by: Javier Martinez Canillas
Reviewed-by: Krzysztof Kozlowski
---
Changes in v5:
- List Ondrej Jirman
This series adds support for the display present in the PinePhone Pro.
Patch #1 adds a devicetree binding schema for panels based on the Himax
HX8394 controller, such as the HSD060BHW4 720x1440 TFT LCD panel present
in the PinePhone Pro. Patch #2 adds the panel driver for this controller
and final
On 23-01-02 09:21:40, Johan Hovold wrote:
> On Sun, Jan 01, 2023 at 10:58:42PM -0600, Steev Klimaszewski wrote:
> > On Sat, Dec 31, 2022 at 8:27 AM Abel Vesa wrote:
> > >
> > > The actual name is R133NW4K-R0.
> > >
> > > Fixes: 0f9fa5f58c784 ("drm/panel-edp: add IVO M133NW4J-R3 panel entry")
> > >
On Mon, Jan 02, 2023 at 09:25:41PM +0100, Javier Martinez Canillas wrote:
> Change made using a `clang-format -i include/drm/drm_mipi_dsi.h` command.
>
> Suggested-by: Sam Ravnborg
> Signed-off-by: Javier Martinez Canillas
Thanks,
Reviewed-by: Sam Ravnborg
> ---
>
> Changes in v2:
> - New pa
Many panel drivers define dsi_dcs_write_seq() and dsi_generic_write_seq()
macros to send DCS commands and generic write packets respectively, with
the payload specified as a list of parameters instead of using arrays.
There's already a macro for the former, introduced by commit 2a9e9daf75231
("drm
Change made using a `clang-format -i include/drm/drm_mipi_dsi.h` command.
Suggested-by: Sam Ravnborg
Signed-off-by: Javier Martinez Canillas
---
Changes in v2:
- New patch in v2.
include/drm/drm_mipi_dsi.h | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --gi
On 1/2/23 20:00, Sam Ravnborg wrote:
> Hi Javier.
>
> On Wed, Dec 28, 2022 at 02:47:43AM +0100, Javier Martinez Canillas wrote:
>> Hello,
>>
>> This series contains cleanups for DRM panel drivers that define their own
>> DSI write macros instead of using what's already in .
>>
>> The changes are q
On 1/2/23 19:53, Sam Ravnborg wrote:
[...]
>> }
>>
>> -#define dsi_generic_write_seq(dsi, cmd, seq...) do {
>> \
>> -static const u8 b[] = { cmd, seq }; \
>> -int ret;\
>> -
Hi Javier,
> > (If you align '\' under each other it would be nicer, but I could see
> > that mipi_dsi_dcs_write_seq() do not do so).
>
> Yeah, I was actually thinking about doing like you suggested for this macro
> but preferred to keep it consistent with the existing mipi_dsi_dcs_write_seq()
>
Hi Javier.
On Wed, Dec 28, 2022 at 02:47:43AM +0100, Javier Martinez Canillas wrote:
> Hello,
>
> This series contains cleanups for DRM panel drivers that define their own
> DSI write macros instead of using what's already in .
>
> The changes are quite trivial but I've only tested this with all
Hello Sam,
Thanks a lot for your feedback.
On 1/2/23 19:39, Sam Ravnborg wrote:
> Hi Javier.
>
> On Wed, Dec 28, 2022 at 02:47:44AM +0100, Javier Martinez Canillas wrote:
>> Many panel drivers define dsi_dcs_write_seq() and dsi_generic_write_seq()
>> macros to send DCS commands and generic write
On Wed, Dec 28, 2022 at 02:47:55AM +0100, Javier Martinez Canillas wrote:
> There is a macro for this already in the header, use
> that instead and delete the custom DSI write macro defined in the driver.
>
> Signed-off-by: Javier Martinez Canillas
Reviewed-by: Sam Ravnborg
> ---
>
> .../gpu/
On Wed, Dec 28, 2022 at 02:47:53AM +0100, Javier Martinez Canillas wrote:
> There is a macro for this already in the header, use
> that instead and delete the custom DSI write macro defined in the driver.
>
> Signed-off-by: Javier Martinez Canillas
Reviewed-by: Sam Ravnborg
> ---
>
> drivers/
On Wed, Dec 28, 2022 at 02:47:50AM +0100, Javier Martinez Canillas wrote:
> There is a macro for this already in the header, use
> that instead and delete the custom DSI write macro defined in the driver.
>
> Signed-off-by: Javier Martinez Canillas
Reviewed-by: Sam Ravnborg
> ---
>
> drivers/
Hi Javier.
On Wed, Dec 28, 2022 at 02:47:57AM +0100, Javier Martinez Canillas wrote:
> There is a macro for this already in the header, use
> that instead and delete the custom DSI write macro defined in the driver.
>
> Signed-off-by: Javier Martinez Canillas
> ---
>
> .../gpu/drm/panel/panel
Hi Javier,
On Wed, Dec 28, 2022 at 02:47:56AM +0100, Javier Martinez Canillas wrote:
> There is a macro for this already in the header, use
> that instead and delete the custom DSI write macro defined in the driver.
>
> Signed-off-by: Javier Martinez Canillas
> ---
>
> .../panel/panel-sony-tu
On 1/2/23 16:20, Ondřej Jirman wrote:
> On Mon, Jan 02, 2023 at 02:51:42PM +0100, Javier Martinez Canillas wrote:
>> Hello Ondřej,
>>
>> [...]
>>
>> My goal was to have some initial support in mainline even if there could be
>> some
>> issues. IMO it is better to use upstream as a baseline and att
On Wed, Dec 28, 2022 at 02:47:54AM +0100, Javier Martinez Canillas wrote:
> There is a macro for this already in the header, use
> that instead and delete the custom DSI write macro defined in the driver.
>
> Signed-off-by: Javier Martinez Canillas
This is a nice patch - where you benefit from
On Wed, Dec 28, 2022 at 02:47:52AM +0100, Javier Martinez Canillas wrote:
> There is a macro for this already in the header, use
> that instead and delete the custom DSI write macro defined in the driver.
>
> Signed-off-by: Javier Martinez Canillas
> ---
>
> .../panel/panel-samsung-s6e88a0-ams
Hi Javier,
On Wed, Dec 28, 2022 at 02:47:51AM +0100, Javier Martinez Canillas wrote:
> There are macros for these already in the header, use
> that instead and delete the custom DSI write macros defined in the driver.
>
> Signed-off-by: Javier Martinez Canillas
> ---
>
> drivers/gpu/drm/panel
Hi Javier,
On Wed, Dec 28, 2022 at 02:47:49AM +0100, Javier Martinez Canillas wrote:
> There is a macro for this already in the header, use
> that instead and delete the custom DSI write macro defined in the driver.
>
> Signed-off-by: Javier Martinez Canillas
> ---
>
> .../gpu/drm/panel/panel
Hi Javier,
On Wed, Dec 28, 2022 at 02:47:48AM +0100, Javier Martinez Canillas wrote:
> There is a macro for this already in the header, use
> that instead and delete the custom DSI write macro defined in the driver.
>
> Signed-off-by: Javier Martinez Canillas
> ---
>
> drivers/gpu/drm/panel/p
Hi Javier,
On Wed, Dec 28, 2022 at 02:47:47AM +0100, Javier Martinez Canillas wrote:
> There is a macro for this already in the header, use
> that instead and delete the custom DSI write macro defined in the driver.
>
> Signed-off-by: Javier Martinez Canillas
> ---
>
> .../drm/panel/panel-lea
Hi Javier,
On Wed, Dec 28, 2022 at 02:47:46AM +0100, Javier Martinez Canillas wrote:
> There are macros for these already in the header, use
> that instead and delete the custom DSI write macros defined in the driver.
>
> Signed-off-by: Javier Martinez Canillas
> ---
>
> drivers/gpu/drm/panel
Hi Javier.
On Wed, Dec 28, 2022 at 02:47:44AM +0100, Javier Martinez Canillas wrote:
> Many panel drivers define dsi_dcs_write_seq() and dsi_generic_write_seq()
> macros to send DCS commands and generic write packets respectively, with
> the payload specified as a list of parameters instead of usi
On Fri, Dec 30, 2022 at 12:03:25PM +0200, Mikko Perttunen wrote:
> On 12/30/22 12:01, Mikko Perttunen wrote:
> > On 12/30/22 11:15, Stanislaw Gruszka wrote:
> > > On Wed, Dec 28, 2022 at 03:17:59PM +0200, Mikko Perttunen wrote:
> > > > On 12/28/22 15:08, Deepak R Varma wrote:
> > > > > On Wed, Dec
On Fri, 30 Dec 2022 at 17:12, Krzysztof Kozlowski
wrote:
>
> On 30/12/2022 16:35, Robert Foss wrote:
> > Use two interconnect cells in order to optionally
> > support a path tag.
> >
> > Signed-off-by: Robert Foss
> > Reviewed-by: Konrad Dybcio
> > ---
> > arch/arm64/boot/dts/qcom/sm8350.dtsi |
[AMD Official Use Only - General]
Sorry for the messed up mail. We currently have mail problems here at AMD.
Von: Oleksii Moisieiev
Gesendet: Montag, 2. Januar 2023 14:41
An: jgr...@suse.com
Cc: Oleksii Moisieiev ; Stefano Stabellini
; Oleksandr Tyshchenko ;
x
On 02/01/2023 03:39, Rob Clark wrote:
On Sun, Jan 1, 2023 at 7:57 AM Dmitry Baryshkov
wrote:
Support loading A200 firmware generated from the iMX firmware header
files. The firmware lacks protection support, however it allows GPU to
function properly while using the firmware files with clear l
On 02/01/2023 13:06, Marijn Suijten wrote:
On 2023-01-01 15:32:11, Dmitry Baryshkov wrote:
On 31/12/2022 23:50, Marijn Suijten wrote:
Since DPU 5.0.0 the TEARCHECK registers and interrupts moved out of the
PINGPONG block and into the INTF. Implement the necessary callbacks in
the INTF block, a
The frame event callback is always set to dpu_crtc_frame_event_cb() (or
to NULL) and the data is always either the CRTC itself or NULL
(correpondingly). Thus drop the event callback registration, call the
dpu_crtc_frame_event_cb() directly and gate on the dpu_enc->crtc
assigned using dpu_encoder_as
Struct dpu_encoder_virt_ops is used to provide several callbacks to the
phys_enc backends. However these ops are static and are not supposed to
change in the foreseeble future. Drop the indirection and call
corresponding functions directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm
Hi
Am 02.01.23 um 16:39 schrieb Maíra Canal:
On 1/2/23 12:21, Thomas Zimmermann wrote:
Hi
Am 02.01.23 um 15:29 schrieb Maíra Canal:
Hi,
On 1/2/23 11:20, Thomas Zimmermann wrote:
Hi
Am 02.01.23 um 14:57 schrieb Maíra Canal:
Currently, vc4 is not checking valid formats before creating a
fra
Am 30.12.22 um 06:21 schrieb Mario Limonciello:
If SDMA microcode is not available during early init, the firmware
framebuffer will have already been released and the screen will
freeze.
Move the request from SDMA microcode into the IP discovery phase
so that if it's not available, IP discove
On 1/2/23 12:21, Thomas Zimmermann wrote:
Hi
Am 02.01.23 um 15:29 schrieb Maíra Canal:
Hi,
On 1/2/23 11:20, Thomas Zimmermann wrote:
Hi
Am 02.01.23 um 14:57 schrieb Maíra Canal:
Currently, vc4 is not checking valid formats before creating a
framebuffer, which is triggering the IGT test
igt@
On 12/30/22 07:35, Hang Zhang wrote:
In do_fb_ioctl(), user specified "fb_info" can be freed in the callee
fbcon_get_con2fb_map_ioctl() -> set_con2fb_map() ->
con2fb_release_oldinfo(), this free operation is protected by
console_lock() in fbcon_set_con2fb_map_ioctl(), it also results in
the chang
Hi
Am 02.01.23 um 15:29 schrieb Maíra Canal:
Hi,
On 1/2/23 11:20, Thomas Zimmermann wrote:
Hi
Am 02.01.23 um 14:57 schrieb Maíra Canal:
Currently, vc4 is not checking valid formats before creating a
framebuffer, which is triggering the IGT test
igt@kms_addfb_basic@addfb25-bad-modifier to fai
On Mon, Jan 02, 2023 at 04:18:30PM +0530, Akhil P Oommen wrote:
> Remove the unused 'reset' interface which was supposed to help to ensure
> that cx gdsc has collapsed during gpu recovery. This is was not enabled
> so far due to missing gpucc driver support. Similar functionality using
> genpd fram
On Mon, Jan 02, 2023 at 02:51:42PM +0100, Javier Martinez Canillas wrote:
> Hello Ondřej,
>
> [...]
>
> My goal was to have some initial support in mainline even if there could be
> some
> issues. IMO it is better to use upstream as a baseline and attempt to support
> the
> PPP incrementally.
>
On Mon, 02 Jan 2023 15:14, AngeloGioacchino Del Regno
wrote:
>Il 02/01/23 14:38, Guillaume Ranquet ha scritto:
>> On Mon, 26 Dec 2022 06:18, CK Hu (胡俊光) wrote:
>>> Hi, Guillaume:
>>>
>>> On Fri, 2022-11-04 at 15:09 +0100, Guillaume Ranquet wrote:
Add mt8195 SoC bindings for hdmi and hdmi-ddc
On 1/2/23 17:17, youling 257 wrote:
> which patch?
https://patchwork.freedesktop.org/patch/512652/
I applied it to next-fixes
--
Best regards,
Dmitry
On 11/23/22 03:13, Dmitry Osipenko wrote:
> The drm_sched_entity_kill() is invoked twice by drm_sched_entity_destroy()
> while userspace process is exiting or being killed. First time it's invoked
> when sched entity is flushed and second time when entity is released. This
> causes a lockup within
On 11/9/22 12:19, Xiu Jianfeng wrote:
> The virtio_gpu_object_shmem_init() will alloc memory and save it in
> @ents, so when virtio_gpu_array_alloc() fails, this memory should be
> freed, this patch fixes it.
>
> Fixes: e7fef0923303 ("drm/virtio: Simplify error handling of
> virtio_gpu_object_cre
On 11/30/22 03:08, Rob Clark wrote:
> From: Rob Clark
>
> Add a sequence # for more easily matching up cmd/resp, and the # of free
> slots in the virtqueue to more easily see starvation issues.
>
> v2: Fix handling of string fields as well
>
> Signed-off-by: Rob Clark
> Reviewed-by: Dmitry Osi
On 1/2/23 2:21 AM, Johan Hovold wrote:
On Sun, Jan 01, 2023 at 10:58:42PM -0600, Steev Klimaszewski wrote:
On Sat, Dec 31, 2022 at 8:27 AM Abel Vesa wrote:
The actual name is R133NW4K-R0.
Fixes: 0f9fa5f58c784 ("drm/panel-edp: add IVO M133NW4J-R3 panel entry")
Signed-off-by: Abel Vesa
---
On 1/2/23 14:57, Paul Menzel wrote:
Commit 62d89a7d49af ("video: fbdev: matroxfb: set maxvram of vbG200eW to
the same as vbG200 to avoid black screen") accidently decreases the
maximum memory size for the Matrox G200eW (102b:0532) from 8 MB to 1 MB
by missing one zero. This caused the driver init
Hi,
On 1/2/23 11:20, Thomas Zimmermann wrote:
Hi
Am 02.01.23 um 14:57 schrieb Maíra Canal:
Currently, vc4 is not checking valid formats before creating a
framebuffer, which is triggering the IGT test
igt@kms_addfb_basic@addfb25-bad-modifier to fail, as vc4 accepts
to create a framebuffer with
On Fri, Dec 30, 2022 at 07:35:00PM +0100, Nirmoy Das wrote:
> Switch to %zu for printing size_t which will
> fix compilation warning for 32-bit build.
>
> Reported-by: kernel test robot
> Signed-off-by: Nirmoy Das
Reviewed-by: Andi Shyti
Andi
> ---
> drivers/gpu/drm/i915/gem/i915_gem_shmem.
Hi
Am 02.01.23 um 14:57 schrieb Maíra Canal:
Currently, vc4 is not checking valid formats before creating a
framebuffer, which is triggering the IGT test
igt@kms_addfb_basic@addfb25-bad-modifier to fail, as vc4 accepts
to create a framebuffer with an invalid modifier. Therefore, check
for valid
which patch?
2023-01-02 17:24 GMT+08:00, Dmitry Osipenko :
> On 1/1/23 21:29, youling257 wrote:
>> Linux 6.2-rc1 has memory leak on amdgpu, git bisect bad commit is
>> "drm/scheduler: rework entity flush, kill and fini".
>> git bisect start
>> # status: waiting for both good and bad commits
>> # g
Il 02/01/23 14:38, Guillaume Ranquet ha scritto:
On Mon, 26 Dec 2022 06:18, CK Hu (胡俊光) wrote:
Hi, Guillaume:
On Fri, 2022-11-04 at 15:09 +0100, Guillaume Ranquet wrote:
Add mt8195 SoC bindings for hdmi and hdmi-ddc
On mt8195 the ddc i2c controller is part of the hdmi IP block and
thus has n
[Cc: Back to dal...@libc.org]
Dear Linux folks,
Please ignore version 2.
Am 02.01.23 um 15:02 schrieb Paul Menzel:
[…]
---
Update Rich’s address.
I should have read the undelivered message better:
```
: host brightrain.aerifal.cx[216.12.86.13] said:
550-Message
blocked for policy r
Commit 62d89a7d49af ("video: fbdev: matroxfb: set maxvram of vbG200eW to
the same as vbG200 to avoid black screen") accidently decreases the
maximum memory size for the Matrox G200eW (102b:0532) from 8 MB to 1 MB
by missing one zero. This caused the driver initialization to fail with
the messages b
Commit 62d89a7d49af ("video: fbdev: matroxfb: set maxvram of vbG200eW to
the same as vbG200 to avoid black screen") accidently decreases the
maximum memory size for the Matrox G200eW (102b:0532) from 8 MB to 1 MB
by missing one zero. This caused the driver initialization to fail with
the messages b
On 02/01/2023 12:25, Marijn Suijten wrote:
On 2023-01-01 06:28:23, Dmitry Baryshkov wrote:
On 31/12/2022 23:50, Marijn Suijten wrote:
Since hardware revision 5.0.0 the TE configuration moved out of the
PINGPONG block into the INTF block. Writing these registers has no
effect, and is omitted do
Currently, vc4 is not checking valid formats before creating a
framebuffer, which is triggering the IGT test
igt@kms_addfb_basic@addfb25-bad-modifier to fail, as vc4 accepts
to create a framebuffer with an invalid modifier. Therefore, check
for valid formats before creating framebuffers on vc4 and
On Tue, 27 Dec 2022 20:40:03 +0300
Alexey Lukyachuk wrote:
> On Tue, 27 Dec 2022 11:39:25 -0500
> Rodrigo Vivi wrote:
>
> > On Sun, Dec 25, 2022 at 09:55:08PM +0300, Alexey Lukyanchuk wrote:
> > > dell wyse 3040 doesn't peform poweroff properly, but instead remains in
> > > turned power on sta
Hello Ondřej,
On 1/2/23 11:59, Ondřej Jirman wrote:
[...]
>> Yes, because as you said were debug printks. Feel free to propose adding the
>> debug printks if you consider useful for normal usage and not just for devel
>> purposes.
>
> I already did, and used them do debug and fix the issues. Th
On Mon, 26 Dec 2022 06:18, CK Hu (胡俊光) wrote:
>Hi, Guillaume:
>
>On Fri, 2022-11-04 at 15:09 +0100, Guillaume Ranquet wrote:
>> Add mt8195 SoC bindings for hdmi and hdmi-ddc
>>
>> On mt8195 the ddc i2c controller is part of the hdmi IP block and
>> thus has no
>> specific register range, power dom
Hello Ondřej,
On 1/2/23 11:57, Ondřej Jirman wrote:
[...]
>>
>> You tell me, it is your patch :) I just cherry-picked this from your tree:
>
> I have other patches to goodix driver that do power off the touch sensor chip
> during sleep, so that it doesn't consume excessinve amounts of power whe
Hi Rahul,
Thank you for the patch.
On Mon, Jan 02, 2023 at 03:39:42PM +0530, Rahul T R wrote:
> Add support for wrapper settings for DSI bridge on
> j721e. Also enable DPI0
>
> --- ---
> | ---| |--- |
> | DSS | DPI2 |->| DP
Hi Rahul,
Thank you for the patch.
On Mon, Jan 02, 2023 at 03:39:41PM +0530, Rahul T R wrote:
> Create a header file for cdns dsi and move
> register offsets and structure to header,
> to prepare for adding j721e wrapper support
You don't have to wrap lines at 43 characters, you can go all the w
Nirmoy, thanks for fixing it
Reviewed-by: Gwan-gyeong Mun
On 12/30/22 8:35 PM, Nirmoy Das wrote:
Switch to %zu for printing size_t which will
fix compilation warning for 32-bit build.
Reported-by: kernel test robot
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem/i915_gem_shmem.c |
Hi Rahul,
Thank you for the patch.
On Mon, Jan 02, 2023 at 03:39:40PM +0530, Rahul T R wrote:
> Move the cadence dsi bridge under drm/bridge/cadence
> directory, to prepare for adding j721e wrapper
> support
>
> Signed-off-by: Rahul T R
> Reviewed-by: Tomi Valkeinen
> ---
> drivers/gpu/drm/br
Hi Rahul,
Thank you for the patch.
On Mon, Jan 02, 2023 at 03:39:39PM +0530, Rahul T R wrote:
> Add compatible to support dsi bridge on j721e
>
> Signed-off-by: Rahul T R
> Reviewed-by: Rob Herring
Reviewed-by: Laurent Pinchart
> ---
> .../bindings/display/bridge/cdns,dsi.yaml | 25 +++
Hi Rahul,
Thank you for the patch.
On Mon, Jan 02, 2023 at 03:39:38PM +0530, Rahul T R wrote:
> Convert cdns,dsi.txt binding to yaml format
>
> Signed-off-by: Rahul T R
> Reviewed-by: Rob Herring
> ---
> .../bindings/display/bridge/cdns,dsi.txt | 112 -
> .../bindings/display
The array of BOs that are lookup up at the start of exec doesn't need
to be instantiated as drm_gem_dma_object, as it doesn't benefit
from its attributes. So, simplify the code by replacing the array of
drm_gem_dma_object for an array of drm_gem_object in the struct
vc4_exec_info.
Suggested-by: Me
As vc4_cl_lookup_bos() performs the same steps as drm_gem_objects_lookup(),
replace the open-coded implementation in vc4 to simply use the DRM function.
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/vc4/vc4_gem.c | 43 ++-
1 file changed, 2 insertions(+), 41 dele
Currently, the array of BOs that are lookup up at the start of exec is being
instantiated as drm_gem_dma_object, which is not needed and makes it difficult
to use the drm_gem_objects_lookup() helper. Therefore, replace
drm_gem_dma_object for drm_gem_object and then replace obj lookup steps with
drm
On 02.01.2023 13:01, Maxime Ripard wrote:
Commit 5ea6b1702781 ("drm/panel: Add prepare_prev_first flag to
drm_panel") introduced an access to the bridge pointer in the
devm_drm_panel_bridge_add_typed() function.
However, due to the unusual ERR_PTR check when getting that pointer, the
pointer
Hi Maxime,
Thank you for the patch.
On Mon, Jan 02, 2023 at 01:01:23PM +0100, Maxime Ripard wrote:
> Commit 5ea6b1702781 ("drm/panel: Add prepare_prev_first flag to
> drm_panel") introduced an access to the bridge pointer in the
> devm_drm_panel_bridge_add_typed() function.
>
> However, due to t
Commit 5ea6b1702781 ("drm/panel: Add prepare_prev_first flag to
drm_panel") introduced an access to the bridge pointer in the
devm_drm_panel_bridge_add_typed() function.
However, due to the unusual ERR_PTR check when getting that pointer, the
pointer access is done even though the pointer might be
On Mon, 02 Jan 2023, Thomas Zimmermann wrote:
> Hi
>
> Am 22.12.22 um 23:21 schrieb Matthew Brost:
>> Hello,
>>
>> This is a submission for Xe, a new driver for Intel GPUs that supports both
>> integrated and discrete platforms starting with Tiger Lake (first platform
>> with
>> Intel Xe Archite
Drivers only emulate XRGB framebuffers. Remove all conversion
helpers that do not use XRGB as their source format. Also remove
some special cases for alpha formats in the blit helper.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Javier Martinez Canillas
---
drivers/gpu/drm/drm_format_h
Fix the color-format selection of the single-probe helper. Go
through all user-specified values and test each for compatibility
with the driver. If none is supported, use the driver-provided
default. This guarantees that the console is always available in
any color format at least.
Until now, the
The DRM helper drm_fb_build_fourcc_list() creates a list of color
formats for primary planes of the generic drivers. Simplify the helper:
- It used to mix and filter native and emulated formats as provided
by the driver. Now the only emulated format is XRGB, which is
required as fallbac
Split the single-probe helper's implementation into multiple
functions and get locking and overallocation out of the way of
the surface setup. Simplifies later changes to the setup code.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Javier Martinez Canillas
---
drivers/gpu/drm/drm_fb_helper.c |
Upcoming changes to the format conversion will mostly blit from
XRGB to some other format. So put the source format in blit's
outer branches to make the code more readable. For cases where
a format only changes its endianness, such as XRGB565, introduce
dedicated branches that handle this for a
Add dedicated helper to convert from XRGB to ARGB2101010. Sets
all alpha bits to make pixels fully opaque.
v2:
* set correct format in struct drm_framebuffer (Javier)
* use cpubuf_to_le32()
* type fixes
Signed-off-by: Thomas Zimmermann
Reviewed-by: Javier Martinez Can
Add conversion from XRGB to XRGB1555, ARGB1555 and RGBA5551, which
are the formats currently supported by the simplefb infrastructure. The
new helpers allow the output of XRGB framebuffers to firmware
scanout buffers in one of the 15-bit formats.
v3:
* use __le* for destination buf
Change the source-buffer type of le32buf_to_cpu() to __le32* to
reflect endianness. Result buffers are converted to local endianness,
so instantiate them from regular u8 or u32 types.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Maíra Canal
Reviewed-by: José Expósito
---
drivers/gpu/drm/tests
Convert test input for format helpers from host byte order to
little-endian order. The current code does it the other way around,
but there's no effective difference to the result.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Maíra Canal
Reviewed-by: José Expósito
---
.../gpu/drm/tests/drm_fo
RGB888 is different than the other formats as most of its pixels are
unaligned and therefore helper functions do not use endianness conversion
helpers. Comment on this in the source code.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Maíra Canal
Reviewed-by: José Expósito
---
drivers/gpu/drm/d
Fix to-RGB565 conversion helpers to store the result in little-
endian byte order. Update test cases as well.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Maíra Canal
Reviewed-by: José Expósito
---
drivers/gpu/drm/drm_format_helper.c | 9 +
.../gpu/drm/tests/drm_format_help
Add dedicated helper to convert from XRGB to ARGB. Sets
all alpha bits to make pixels fully opaque.
v3:
* use __le32 for destination buffer (Jose, kernel test robot)
v2:
* use cpubuf_to_le32()
* type fixes
Signed-off-by: Thomas Zimmermann
Reviewed-by: Javier Marti
Select color format for EFI/VESA firmware scanout buffer from the
number of bits per pixel and the position of the individual color
components. Fixes the selected format for the buffer in several odd
cases. For example, XRGB1555 has been reported as ARGB1555 because
of the different use of depth an
Fix the selection of the fbdev emulation's color format and make
XRGB the only emulated color format. Resolves the blank screen
in cases where video= specifies an unsupported color format. Also
resolves the issues around current format-conversion helpers.
Version 2 of the patchset fixes the fo
On 2023-01-01 15:32:11, Dmitry Baryshkov wrote:
> On 31/12/2022 23:50, Marijn Suijten wrote:
> > Since DPU 5.0.0 the TEARCHECK registers and interrupts moved out of the
> > PINGPONG block and into the INTF. Implement the necessary callbacks in
> > the INTF block, and use these callbacks together w
Hello Javier,
On Sat, Dec 31, 2022 at 04:15:24PM +0100, Javier Martinez Canillas wrote:
> Hello Ondřej,
>
> Thanks a lot for your comments.
>
> On 12/30/22 16:40, Ondřej Jirman wrote:
> > Hi Javier,
> >
> > On Fri, Dec 30, 2022 at 12:31:52PM +0100, Javier Martinez Canillas wrote:
> >> From: Kam
Hello Javier,
On Sat, Dec 31, 2022 at 04:29:49PM +0100, Javier Martinez Canillas wrote:
> Hello Ondřej,
>
> Thanks a lot for your feedback.
>
> On 12/30/22 16:37, Ondřej Jirman wrote:
>
> [...]
>
> >> &i2c0 {
> >>clock-frequency = <40>;
> >>i2c-scl-rising-time-ns = <168>;
> >> @@
On 1/2/2023 3:32 PM, Konrad Dybcio wrote:
> So far the adreno quirks have all been assigned with an OR operator,
> which is problematic, because they were assigned consecutive integer
> values, which makes checking them with an AND operator kind of no bueno..
>
> Switch to using BIT(n) so that only
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