Enable SDP error detection configuration, this will set CRC16 in
128b/132b link layer.
For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is
added to enable/disable SDP CRC applicable for DP2.0 only, but the
default value of this bit will enable CRC16 in 128b/132b hence
skipping
DP2.0 E11 defines a new register to facilitate SDP error detection by a
128B/132B capable DPRX device.
v2: Update the macro name to reflect the DP spec(Harry)
Signed-off-by: Arun R Murthy
Reviewed-by: Harry Wentland
---
include/drm/display/drm_dp.h | 3 +++
1 file changed, 3 insertions(+)
*** BLURB HERE ***
Arun R Murthy (2):
drm: Add SDP Error Detection Configuration Register
i915/display/dp: SDP CRC16 for 128b132b link layer
.../gpu/drm/i915/display/intel_dp_link_training.c| 12
include/drm/display/drm_dp.h | 3 +++
2 files
From: John Harrison
Update a bunch more debug prints to use the new GT based scheme.
Signed-off-by: John Harrison
Reviewed-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/intel_gt_print.h | 3 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 3 +--
From: John Harrison
Update a bunch more debug prints to use the new GT based scheme.
v2: Also change prints to use %pe for error values (MichalW).
Signed-off-by: John Harrison
Acked-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c | 9 -
From: John Harrison
Update more print messages to the new scheme.
v2: Also change all errors to %pe rather than %d (MichalW).
Few other tweaks.
Signed-off-by: John Harrison
John Harrison (6):
drm/i915/guc: More debug print updates - UC firmware
drm/i915/guc: More debug print updates -
From: John Harrison
Update a bunch more debug prints to use the new GT based scheme.
v2: Upgrade the no node found message to a warning on the grounds of
it being quite important if the error capture can't find any register
state information.
Signed-off-by: John Harrison
Reviewed-by: Alan
From: John Harrison
Update a bunch more debug prints to use the new GT based scheme.
v2: Also change prints to use %pe for error values (MichalW).
Fix a context leak on error due to a -- being too early.
Use the correct header file for the debug macros.
Signed-off-by: John Harrison
---
From: John Harrison
Update a bunch more debug prints to use the new GT based scheme.
v2: Also change prints to use %pe for error values (MichalW).
Signed-off-by: John Harrison
Acked-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 8 +--
From: John Harrison
Update a bunch more debug prints to use the new GT based scheme.
v2: Also change prints to use %pe for error values (MichalW).
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c| 42
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 116
On Mon, Feb 06, 2023 at 11:35:32AM +, Daniel Thompson wrote:
> On Tue, Jan 31, 2023 at 02:57:06PM -0800, Dmitry Torokhov wrote:
> > Switch the driver from legacy gpio API that is deprecated to the newer
> > gpiod API that respects line polarities described in ACPI/DT.
> >
> > This makes driver
On 2/3/2023 23:29, Teres Alexis, Alan Previn wrote:
I see you are inferring that a guc-id of zero can be valid.
I am guessing that might have contributed to some lost captures?
Thanks for catching this.
I'm not inferring anything. I might be implying something, though. The
patch description
On 2/4/2023 00:19, Teres Alexis, Alan Previn wrote:
So i do have one request - but its a nit - for the following case, should it be
a guc_warn instead of a guc_dbg?
(last hunk in this patch)
"No register capture node found for 0x%04X / 0x%08X\n",
ce->guc_id.id, ce->lrc.lrca);"
Hi,
On Thu, Feb 2, 2023 at 4:45 PM Doug Anderson wrote:
>
> Hi,
>
> On Mon, Jan 23, 2023 at 8:05 AM Laurent Pinchart
> wrote:
> >
> > Hi John,
> >
> > On Mon, Jan 23, 2023 at 12:16:45PM +, John Keeping wrote:
> > > On Sun, Jan 22, 2023 at 05:01:27PM +0200, Laurent Pinchart wrote:
> > > > On
On 2/6/2023 4:27 PM, Dmitry Baryshkov wrote:
On 07/02/2023 00:40, Abhinav Kumar wrote:
On 2/3/2023 10:21 AM, Dmitry Baryshkov wrote:
Since the driver uses clipped src coordinates, there is no need to check
against the fb coordinates. Remove corresponding checks and inline
On Wed, 2023-02-01 at 17:04 +0200, Imre Deak wrote:
>
> Yes, this patch should have no functional change, so please check what
> would apply to other drivers as well.
>
> Could you also check Ville's comment about storing start_slot elsewhere
> than the atomic state (leaving only time_slots
On 07/02/2023 00:40, Abhinav Kumar wrote:
On 2/3/2023 10:21 AM, Dmitry Baryshkov wrote:
Since the driver uses clipped src coordinates, there is no need to check
against the fb coordinates. Remove corresponding checks and inline
dpu_plane_validate_src().
Signed-off-by: Dmitry Baryshkov
Can
On 2/3/2023 10:21 AM, Dmitry Baryshkov wrote:
Split pipe-dependent code from dpu_plane_sspp_atomic_update() into the
sspp-dependent?
separate function dpu_plane_sspp_update_pipe(). This is one of
preparational steps to add r_pipe support.
Signed-off-by: Dmitry Baryshkov
Just a couple
On 2/3/2023 10:21 AM, Dmitry Baryshkov wrote:
Since the driver uses clipped src coordinates, there is no need to check
against the fb coordinates. Remove corresponding checks and inline
dpu_plane_validate_src().
Signed-off-by: Dmitry Baryshkov
Can you please explain how the clipping in
On Mon, Feb 6, 2023 at 2:36 PM Arnd Bergmann wrote:
>
> From: Arnd Bergmann
>
> A conversion from 'bool' to 'enum odm_combine_mode' was incomplete,
> and gcc warns about this with many instances of
>
> display/dc/dml/dcn20/display_mode_vba_20.c:3899:44: warning: implicit
> conversion from 'enum
On Thu, Feb 02, 2023 at 03:13:09PM +0100, Greg Kroah-Hartman wrote:
> When calling debugfs_lookup() the result must have dput() called on it,
> otherwise the memory will leak over time. To make things simpler, just
> call debugfs_lookup_and_remove() instead which handles all of the logic
> at
Applied. Thanks!
On Fri, Feb 3, 2023 at 10:27 PM Randy Dunlap wrote:
>
> The path for the "mod_info_packet.h" header file is
> incomplete, so add its location to the header search path
> in the amdgpu Makefile.
>
> See on ARCH=alpha (275 times in one build).
>
> In file included from
On 6.02.2023 15:57, Dmitry Baryshkov wrote:
> Add define for another power saving state used on SM8350 for the GPU.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Konrad Dybcio
Konrad
> include/dt-bindings/power/qcom-rpmpd.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
PMI8950 contains WLED of version 4. Add support for it to the driver.
Signed-off-by: Luca Weiss
---
While adding dt-bindings and dts in a previous series I forgot to add the
compatible to the driver. Fix that now.
---
drivers/video/backlight/qcom-wled.c | 1 +
1 file changed, 1 insertion(+)
This patch changes the headers defined in drm_dp.h to match
the DP 2.1 spec.
Signed-off-by: Jasdeep Dhillon
---
drivers/gpu/drm/tegra/dp.c | 2 +-
include/drm/display/drm_dp.h | 13 +++--
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/tegra/dp.c
From: Arnd Bergmann
A conversion from 'bool' to 'enum odm_combine_mode' was incomplete,
and gcc warns about this with many instances of
display/dc/dml/dcn20/display_mode_vba_20.c:3899:44: warning: implicit
conversion from 'enum ' to 'enum
odm_combine_mode' [-Wenum-conversion]
3899 |
On 2/3/2023 10:21 AM, Dmitry Baryshkov wrote:
Now as all accesses to pipe_cfg and pstate have been cleaned, re-add
struct dpu_hw_pipe_cfg back to dpu_plane_state, so that
dpu_plane_atomic_check() and dpu_plane_atomic_update() do not have a
chance to disagree about src/dst rectangles
On 2/3/2023 12:59 AM, Michal Wajdeczko wrote:
Like we did it for GuC, introduce some helper print macros for
HuC to have unified format of messages that also include GT#.
While around improve some messages and use %pe if possible.
v2: update GSC/PXP timeout message
Signed-off-by: Michal
On Tue, Feb 07, 2023 at 12:12:18AM +0530, Deepak R Varma wrote:
> On Mon, Feb 06, 2023 at 10:33:13AM +, Matthew Auld wrote:
> > On 06/02/2023 09:45, Tvrtko Ursulin wrote:
> > >
> > > Hi,
> > >
> > > Adding Matt & Thomas as potential candidates to review.
> > >
> > > Regards,
> > >
> > >
On 2/3/2023 10:21 AM, Dmitry Baryshkov wrote:
Rework bandwidth/clock calculation functions to use mode directly rather
than fetching it through the plane data.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 39
Hello Lina,
On 2/5/23 13:51, Asahi Lina wrote:
> Other functions touching shmem->sgt take the pages lock, so do that here
> too. drm_gem_shmem_get_pages() & co take the same lock, so move to the
> _locked() variants to avoid recursive locking.
>
> Discovered while auditing locking to write the
On Mon, Feb 06, 2023 at 10:33:13AM +, Matthew Auld wrote:
> On 06/02/2023 09:45, Tvrtko Ursulin wrote:
> >
> > Hi,
> >
> > Adding Matt & Thomas as potential candidates to review.
> >
> > Regards,
> >
> > Tvrtko
> >
> > On 03/02/2023 19:30, Deepak R Varma wrote:
> > > The macro definition
On 2/6/23 17:14, Christian König wrote:
Concentrating this discussion on a very big misunderstanding first.
Am 06.02.23 um 14:27 schrieb Danilo Krummrich:
[SNIP]
My understanding is that userspace is fully responsible on the parts
of the GPU VA space it owns. This means that userspace needs
From: Aravind Iddamsetty
During module load the punit might still be busy with its booting
routines. During this time we try to communicate with it but we
fail because we don't receive any feedback from it and we return
immediately with a -EINVAL fatal error.
At this point the driver load is
On 26.01.2023 16:16, Konrad Dybcio wrote:
> Currently we only utilize the OPP table connected to the GPU for
> getting (available) frequencies. We do however need to scale the
> voltage rail(s) accordingly to ensure that we aren't trying to
> run the GPU at 1GHz with a VDD_LOW vote, as that
Am 06.02.23 um 19:21 schrieb Rob Clark:
On Mon, Feb 6, 2023 at 8:05 AM Christian König wrote:
Am 06.02.23 um 16:52 schrieb Rob Clark:
On Mon, Feb 6, 2023 at 2:15 AM Christian König wrote:
Am 03.02.23 um 19:10 schrieb Rob Clark:
From: Rob Clark
If userspace calls the AMDGPU_CS ioctl from
On Mon, Feb 6, 2023 at 8:05 AM Christian König wrote:
>
> Am 06.02.23 um 16:52 schrieb Rob Clark:
> > On Mon, Feb 6, 2023 at 2:15 AM Christian König
> > wrote:
> >> Am 03.02.23 um 19:10 schrieb Rob Clark:
> >>> From: Rob Clark
> >>>
> >>> If userspace calls the AMDGPU_CS ioctl from multiple
On 06/02/2023 19:34, Aradhya Bhatia wrote:
On 06-Feb-23 18:35, Tomi Valkeinen wrote:
On 05/02/2023 15:08, Aradhya Bhatia wrote:
Hi Tomi,
Thanks for the review!
On 03-Feb-23 16:53, Tomi Valkeinen wrote:
On 25/01/2023 13:35, Aradhya Bhatia wrote:
Make DSS Video Ports agnostic of output bus
On 06-Feb-23 19:12, Tomi Valkeinen wrote:
> On 05/02/2023 15:42, Aradhya Bhatia wrote:
>> Hi Tomi,
>>
>> On 03-Feb-23 20:42, Tomi Valkeinen wrote:
>>> On 25/01/2023 13:35, Aradhya Bhatia wrote:
The newer version of DSS (AM625-DSS) has 2 OLDI TXes at its disposal.
These can be
On 06-Feb-23 18:35, Tomi Valkeinen wrote:
> On 05/02/2023 15:08, Aradhya Bhatia wrote:
>> Hi Tomi,
>>
>> Thanks for the review!
>>
>> On 03-Feb-23 16:53, Tomi Valkeinen wrote:
>>> On 25/01/2023 13:35, Aradhya Bhatia wrote:
Make DSS Video Ports agnostic of output bus types.
DSS
On 2/4/23 02:33, Ryan Neph wrote:
> An interrupted dma_fence_wait() becomes an -ERESTARTSYS returned
> to userspace ioctl(DRM_IOCTL_VIRTGPU_EXECBUFFER) calls, prompting to
> retry the ioctl(), but the passed exbuf->fence_fd has been reset to -1,
> making the retry attempt fail at
On 2/6/23 04:47, Ville Syrjälä wrote:
> On Sat, Feb 04, 2023 at 06:09:45AM +, Joshua Ashton wrote:
>>
>>
>> On 2/3/23 19:34, Ville Syrjälä wrote:
>>> On Fri, Feb 03, 2023 at 09:25:38PM +0200, Ville Syrjälä wrote:
On Fri, Feb 03, 2023 at 08:56:55PM +0200, Ville Syrjälä wrote:
> On
On Mon, Feb 06, 2023 at 08:54:10AM -0800, Lucas De Marchi wrote:
> INF_UNIT_LEVEL_CLKGATE is not replicated, but since it's not actually
> used it can just be removed.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
Looks like the only reference to the register was removed in
On Mon, 06 Feb 2023 02:27:30 +0200, Dmitry Baryshkov wrote:
> Add Adreno A660 to the A635 clause to define all version-specific
> properties. There is no need to add it to the top-level clause, since
> top-level compatible uses pattern to define compatible strings.
>
> Signed-off-by: Dmitry
On Mon, 06 Feb 2023 02:27:27 +0200, Dmitry Baryshkov wrote:
> The GPU clock controller bindings for the Qualcomm sm8350 platform are
> not correct. The driver uses .fw_name instead of using indices to bind
> parent clocks, thus demanding the clock-names usage. With the proper
> clock-names in
Hi Tomi,
On 06-Feb-23 16:28, Tomi Valkeinen wrote:
> On 05/02/2023 16:31, Aradhya Bhatia wrote:
>>
>>
>> On 03-Feb-23 21:03, Tomi Valkeinen wrote:
>>> On 25/01/2023 13:35, Aradhya Bhatia wrote:
Add support for the DSS controller on TI's new AM625 SoC in the tidss
driver.
The
INF_UNIT_LEVEL_CLKGATE is not replicated, but since it's not actually
used it can just be removed.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
Register 0x9424 is not replicated on any platform, so it shouldn't be
declared with REG_MCR(). Declaring it with _MMIO() is basically
duplicate of the GEN7 version, so just remove the GEN8 and change all
the callers to use the right functions.
Old versions of the gen8 bspec page used to contain a
On Fri, Feb 03, 2023 at 05:02:13PM +0700, Bagas Sanjaya wrote:
> Stephen Rothwell reported htmldocs warnings:
>
> Documentation/gpu/i915:64: drivers/gpu/drm/i915/gt/intel_workarounds.c:32:
> WARNING: Inline emphasis start-string without end-string.
> Documentation/gpu/i915:64:
Concentrating this discussion on a very big misunderstanding first.
Am 06.02.23 um 14:27 schrieb Danilo Krummrich:
[SNIP]
My understanding is that userspace is fully responsible on the parts
of the GPU VA space it owns. This means that userspace needs to take
care to *not* ask the kernel to
Hi Sascha,
On Mon, 6 Feb 2023 at 15:49, Sascha Hauer wrote:
> On Mon, Feb 06, 2023 at 03:04:48PM +0100, Sascha Hauer wrote:
> > I guess a first step would be to limit the maximum resolution of vopl
> > to what the hardware can do. We would likely end up with 1080p by
> > default then for the
Am 06.02.23 um 16:52 schrieb Rob Clark:
On Mon, Feb 6, 2023 at 2:15 AM Christian König wrote:
Am 03.02.23 um 19:10 schrieb Rob Clark:
From: Rob Clark
If userspace calls the AMDGPU_CS ioctl from multiple threads, because
the vm is global to the drm_file, you can end up with multiple threads
On Mon, Feb 06, 2023 at 06:59:40AM +1000, Dave Airlie wrote:
> On Sat, 4 Feb 2023 at 09:09, Bjorn Helgaas wrote:
> > From: Bjorn Helgaas
> >
> > This reverts commit 145eed48de278007f646b908fd70ac59d24ed81a.
> >
> > Zeno Davatz reported that 145eed48de27 ("fbdev: Remove conflicting devices
> > on
On Mon, Feb 6, 2023 at 2:15 AM Christian König wrote:
>
> Am 03.02.23 um 19:10 schrieb Rob Clark:
> > From: Rob Clark
> >
> > If userspace calls the AMDGPU_CS ioctl from multiple threads, because
> > the vm is global to the drm_file, you can end up with multiple threads
> > racing in
On Mon, Feb 06, 2023 at 03:04:48PM +0100, Sascha Hauer wrote:
> On Wed, Feb 01, 2023 at 09:23:56AM +0900, FUKAUMI Naoki wrote:
> > hi,
> >
> > I'm trying this patch series with 6.1.x kernel. it works fine on rk356x
> > based boards (ROCK 3), but it has a problem on rk3399 boards (ROCK 4).
> >
>
On Sun, Feb 5, 2023 at 8:12 AM Heiko Stübner wrote:
>
> Hi,
>
> Am Freitag, 3. Februar 2023, 20:02:54 CET schrieb Johan Jonker:
> >
> > On 2/3/23 19:21, Rob Herring wrote:
> > > On Thu, Dec 22, 2022 at 03:22:14PM +0100, Johan Jonker wrote:
> > >> Convert rockchip-lvds.txt to YAML.
> > >>
> > >>
Add the control path component that talks to the management processor (QSM)
to load workloads onto the AIC100 device. This implements the KMD portion
of the NNC protocol over the QAIC_CONTROL MHI channel and the
DRM_IOCTL_QAIC_MANAGE IOCTL to userspace. With this functionality, QAIC
clients are
From: Pranjal Ramajor Asha Kanojiya
Some of the MHI channels for an AIC100 device need to be routed to
userspace so that userspace can communicate directly with QSM. The MHI
bus does not support this, and while the WWAN subsystem does (for the same
reasons), AIC100 is not a WWAN device. Also,
Add the datapath component that manages BOs and submits them to running
workloads on the qaic device via the dma_bridge hardware. This allows
QAIC clients to interact with their workloads (run inferences) via the
following ioctls along with mmap():
DRM_IOCTL_QAIC_CREATE_BO
DRM_IOCTL_QAIC_MMAP_BO
Add MAINTAINERS entry for the Qualcomm Cloud AI 100 driver.
Signed-off-by: Jeffrey Hugo
Reviewed-by: Carl Vanderlip
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 263d37a..0a264f1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@
Now that we have all the components of a minimum QAIC which can boot and
run an AIC100 device, add the infrastructure that allows the QAIC driver
to be built.
Signed-off-by: Jeffrey Hugo
Reviewed-by: Carl Vanderlip
---
drivers/accel/Kconfig | 1 +
drivers/accel/Makefile | 1 +
From: Jeffrey Hugo
This series introduces a driver under the accel subsystem (QAIC -
Qualcomm AIC) for the Qualcomm Cloud AI 100 product (AIC100). AIC100 is
a PCIe adapter card that hosts a dedicated machine learning inference
accelerator.
Regarding the open userspace (see the documentation
Add the QAIC driver uapi file and core driver file that binds to the PCIe
device. The core driver file also creates the accel device and manages
all the interconnections between the different parts of the driver.
The driver can be built as a module. If so, it will be called "qaic.ko".
The Qualcomm Cloud AI 100 (AIC100) device is an Artificial Intelligence
accelerator PCIe card. It contains a number of components both in the
SoC and on the card which facilitate running workloads:
QSM: management processor
NSPs: workload compute units
DMA Bridge: dedicated data mover for the
An AIC100 device contains a MHI interface with a number of different
channels for controlling different aspects of the device. The MHI
controller works with the MHI bus to enable and drive that interface.
AIC100 uses the BHI protocol in PBL to load SBL. The MHI controller
expects the sbl to be
Add device nodes required to enable GPU on the SM8350 platform.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 178 +++
1 file changed, 178 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
Finish reordering DT nodes. Move PDC, tsens, AOSS, SRAM, SPMI and TLMM
nodes to the proper position.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 764 +--
1 file changed, 382 insertions(+), 382 deletions(-)
diff --git
Continue ordering DT nodes. Move RNG, UFS, system NoC and SLPI nodes
to the proper position.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 314 +--
1 file changed, 157 insertions(+), 157 deletions(-)
diff --git
Enable the GPU on the SM8350-HDK device. The ZAP shader is required for
the GPU to function properly.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
Start ordering DT nodes according to agreed order. Move apps SMMU, GIC,
timer, apps RSC, cpufreq ADSP and cDSP nodes to the end to the proper
position at the end of /soc/.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 1228 +-
1 file changed,
Add Adreno A660 to the A635 clause to define all version-specific
properties. There is no need to add it to the top-level clause, since
top-level compatible uses pattern to define compatible strings.
Signed-off-by: Dmitry Baryshkov
---
Documentation/devicetree/bindings/display/msm/gmu.yaml | 1
Add define for another power saving state used on SM8350 for the GPU.
Signed-off-by: Dmitry Baryshkov
---
include/dt-bindings/power/qcom-rpmpd.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/power/qcom-rpmpd.h
b/include/dt-bindings/power/qcom-rpmpd.h
index
The GPU clock controller bindings for the Qualcomm sm8350 platform are
not correct. The driver uses .fw_name instead of using indices to bind
parent clocks, thus demanding the clock-names usage. With the proper
clock-names in place, the bindings becomes equal to the bindings defined
by
Add A660 device to the Qualcomm SM8350 platform and enable it for the
sm8350-hdk board. Unfortunately while adding the GPU & related devices I
noticed that DT nodes on SM8350 are greatly out of the preagreed order,
so patches 4-6 reorder DT nodes to follow the agreement.
Changes since v1:
- Fixed
On Thu, Jan 19, 2023 at 7:24 AM Matthew Brost wrote:
>
> On Thu, Jan 19, 2023 at 05:04:32AM +0100, Danilo Krummrich wrote:
> > On 1/18/23 20:48, Christian König wrote:
> > > Am 18.01.23 um 20:17 schrieb Dave Airlie:
> > > > On Thu, 19 Jan 2023 at 02:54, Alex Deucher
> > > > wrote:
> > > > > On
Hello,
ping here, this one got forgotten.
It still applies on drm-misc-next and v6.2-rc7
On 18.08.22 14:45, Dominik Haller wrote:
> Add support for the EDT ETML1010G0DKA 10.1" 1280x800 LVDS panel.
>
> Signed-off-by: Dominik Haller
> ---
> drivers/gpu/drm/panel/panel-simple.c | 29
On 2/6/23 14:35, Christian König wrote:
Am 03.02.23 um 18:37 schrieb Matthew Brost:
On Wed, Jan 18, 2023 at 07:12:45AM +0100, Danilo Krummrich wrote:
This adds the infrastructure for a manager implementation to keep track
of GPU virtual address (VA) mappings.
New UAPIs, motivated by Vulkan
On 2/6/23 10:48, Christian König wrote:
Am 02.02.23 um 19:31 schrieb Danilo Krummrich:
On 2/2/23 12:53, Christian König wrote:
Am 01.02.23 um 09:10 schrieb Dave Airlie:
[SNIP]
For drivers that don't intend to merge at all and (somehow) are
capable of dealing with sparse regions without
On Wed, Feb 01, 2023 at 09:23:56AM +0900, FUKAUMI Naoki wrote:
> hi,
>
> I'm trying this patch series with 6.1.x kernel. it works fine on rk356x
> based boards (ROCK 3), but it has a problem on rk3399 boards (ROCK 4).
>
> on rk3399 with this patch, I can see large noise area (about one third
On 06/02/2023 12:51, Konrad Dybcio wrote:
On 6.02.2023 01:27, Dmitry Baryshkov wrote:
Add device nodes required to enable GPU on the SM8350 platform.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 179 +++
1 file changed, 179
On 05/02/2023 15:42, Aradhya Bhatia wrote:
Hi Tomi,
On 03-Feb-23 20:42, Tomi Valkeinen wrote:
On 25/01/2023 13:35, Aradhya Bhatia wrote:
The newer version of DSS (AM625-DSS) has 2 OLDI TXes at its disposal.
These can be configured to support the following modes:
1.
Am 03.02.23 um 18:37 schrieb Matthew Brost:
On Wed, Jan 18, 2023 at 07:12:45AM +0100, Danilo Krummrich wrote:
This adds the infrastructure for a manager implementation to keep track
of GPU virtual address (VA) mappings.
New UAPIs, motivated by Vulkan sparse memory bindings graphics drivers
Hi,
any feedback on this?
Best regards
Alexander
Am Dienstag, 17. Januar 2023, 12:08:01 CET schrieb Alexander Stein:
> From: Matthias Schiffer
>
> The PIXCLK needs to be enabled in SCFG before accessing certain DCU
> registers, or the access will hang.
>
> Signed-off-by: Matthias Schiffer
>
On 05/02/2023 15:08, Aradhya Bhatia wrote:
Hi Tomi,
Thanks for the review!
On 03-Feb-23 16:53, Tomi Valkeinen wrote:
On 25/01/2023 13:35, Aradhya Bhatia wrote:
Make DSS Video Ports agnostic of output bus types.
DSS controllers have had a 1-to-1 coupling between its VPs and its
output ports.
On 06/02/2023 13:23, Konrad Dybcio wrote:
On 6.02.2023 12:22, Dmitry Baryshkov wrote:
On 06/02/2023 12:44, Konrad Dybcio wrote:
On 6.02.2023 01:27, Dmitry Baryshkov wrote:
Add another power saving state used on SM8350.
Signed-off-by: Dmitry Baryshkov
---
On 06/02/2023 14:36, Neil Armstrong wrote:
On 06/02/2023 12:20, Dmitry Baryshkov wrote:
On 06/02/2023 12:33, Krzysztof Kozlowski wrote:
On 06/02/2023 11:17, Neil Armstrong wrote:
The SM8450 & SM350 shares the same DT TX IP version, use the
SM8350 compatible as fallback for SM8450.
On 06/02/2023 12:20, Dmitry Baryshkov wrote:
On 06/02/2023 12:33, Krzysztof Kozlowski wrote:
On 06/02/2023 11:17, Neil Armstrong wrote:
The SM8450 & SM350 shares the same DT TX IP version, use the
SM8350 compatible as fallback for SM8450.
Signed-off-by: Neil Armstrong
---
On 06/02/2023 12:03, Konrad Dybcio wrote:
subject: s/dst/dts here and in 5/5
On 6.02.2023 11:17, Neil Armstrong wrote:
The QMP PHY is a USB3/DP combo phy, switch to the newly
documented bindings and register the clocks to the GCC
and DISPCC controllers.
Signed-off-by: Neil Armstrong
---
On Sat, Feb 04, 2023 at 09:30:40PM +0800, Pin-yen Lin wrote:
> Register USB Type-C mode switches when the "mode-switch" property and
> relevant port are available in Device Tree. Configure the "lane_swap"
> state based on the entered alternate mode for a specific Type-C
> connector, which ends up
On Sat, Feb 04, 2023 at 09:30:37PM +0800, Pin-yen Lin wrote:
> Register USB Type-C mode switches when the "mode-switch" property and
> relevant ports are available in Device Tree. Configure the crosspoint
> switch based on the entered alternate mode for a specific Type-C
> connector.
>
>
On Mon, 06 Feb 2023, Andy Shevchenko wrote:
> On Sat, Feb 04, 2023 at 09:30:34PM +0800, Pin-yen Lin wrote:
>> Add helpers to register and unregister Type-C "switches" for bridges
>> capable of switching their output between two downstream devices.
>>
>> The helper registers USB Type-C mode
On Sat, Feb 04, 2023 at 09:30:36PM +0800, Pin-yen Lin wrote:
> The output port endpoints can be connected to USB-C connectors.
> Running drm_of_find_panel_or_bridge() with such endpoints leads to
> a continuous return value of -EPROBE_DEFER, even though there is
> no panel present.
>
> To avoid
On Sat, Feb 04, 2023 at 09:30:34PM +0800, Pin-yen Lin wrote:
> Add helpers to register and unregister Type-C "switches" for bridges
> capable of switching their output between two downstream devices.
>
> The helper registers USB Type-C mode switches when the "mode-switch"
> and the "reg"
Add a function to get the old MST topology state, required by a
follow-up i915 patch.
While at it clarify the code comment of
drm_atomic_get_new_mst_topology_state() and add _new prefix
to the new state pointer to remind about its difference from the old
state.
v2: Use old_/new_ prefixes for the
Atm, drm_dp_remove_payload() uses the same payload state to both get the
vc_start_slot required for the payload removal DPCD message and to
deduct time_slots from vc_start_slot of all payloads after the one being
removed.
The above isn't always correct, as vc_start_slot must be the up-to-date
On Tue, Jan 31, 2023 at 02:57:07PM -0800, Dmitry Torokhov wrote:
> There is no need for this driver to be OF-specific, so switch it to
> use device_get_match_data() and stop including various of-related
> headers.
>
> Signed-off-by: Dmitry Torokhov
Reviewed-by: Daniel Thompson
Daniel.
On 06-02-2023 15:21, Tvrtko Ursulin wrote:
>
>
> On 03/02/2023 13:52, Aravind Iddamsetty wrote:
>> Obj flags for shmem objects is not being set correctly. Fixes in setting
>> BO_ALLOC_USER flag which applies to shmem objs as well.
>>
>> Fixes: 13d29c823738 ("drm/i915/ehl: unconditionally
On Tue, Jan 31, 2023 at 02:57:06PM -0800, Dmitry Torokhov wrote:
> Switch the driver from legacy gpio API that is deprecated to the newer
> gpiod API that respects line polarities described in ACPI/DT.
>
> This makes driver use standard property name for the reset gpio
> ("reset-gpios" vs
On 6.02.2023 12:22, Dmitry Baryshkov wrote:
> On 06/02/2023 12:44, Konrad Dybcio wrote:
>>
>>
>> On 6.02.2023 01:27, Dmitry Baryshkov wrote:
>>> Add another power saving state used on SM8350.
>>>
>>> Signed-off-by: Dmitry Baryshkov
>>> ---
>>> include/dt-bindings/power/qcom-rpmpd.h | 1 +
>>
On 06/02/2023 12:44, Konrad Dybcio wrote:
On 6.02.2023 01:27, Dmitry Baryshkov wrote:
Add another power saving state used on SM8350.
Signed-off-by: Dmitry Baryshkov
---
include/dt-bindings/power/qcom-rpmpd.h | 1 +
Wrong patch?
And this patch is correct. sm8350 GPU OPP table uses this
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