Hi, Javier,
Is there any way to get this patch to be merged?
Huacai
On Tue, Nov 29, 2022 at 10:10 PM Huacai Chen wrote:
>
> Ping?
>
> On Tue, Jul 5, 2022 at 12:22 AM Huacai Chen wrote:
> >
> > Consider a configuration like this:
> > 1, efifb (or simpledrm) is built-in;
> > 2, a native display
On Sun, May 07, 2023 at 02:16:36AM +0530, Akhil P Oommen wrote:
> On Sat, May 06, 2023 at 08:16:21PM +0530, Akhil P Oommen wrote:
> > On Fri, May 05, 2023 at 12:35:18PM +0200, Konrad Dybcio wrote:
> > >
> > >
> > > On 5.05.2023 10:46, Akhil P Oommen wrote:
> > > > On Thu, May 04, 2023 at 08:34:07
On Sat, May 06, 2023 at 08:16:21PM +0530, Akhil P Oommen wrote:
> On Fri, May 05, 2023 at 12:35:18PM +0200, Konrad Dybcio wrote:
> >
> >
> > On 5.05.2023 10:46, Akhil P Oommen wrote:
> > > On Thu, May 04, 2023 at 08:34:07AM +0200, Konrad Dybcio wrote:
> > >>
> > >>
> > >> On 3.05.2023 22:32, Akhi
On 04/25, Maíra Canal wrote:
Perform the correct casting of the intermediate coefficients of the
RGB565 pixel conversion. Currently, the pixel conversion is using s64
for the intermediate coefficients, which is causing the IGT pixel-format
tests to fail. So, cast the operands to s32 in order to i
The high-speed clock is hard-coded to the burst-clock
frequency specified in the device tree. However, when
using devices like certain bridge chips without burst mode
and varying resolutions and refresh rates, it may be
necessary to set the high-speed clock dynamically based
on the desired pixel c
The DPHY timings are currently hard coded. Since the input
clock can be variable, the phy timings need to be variable
too. Add an additional variable to the driver data to enable
this feature to prevent breaking boards that don't support it.
The phy_mipi_dphy_get_default_config function configure
In order to support variable DPHY timings, it's necessary
to enable GENERIC_PHY_MIPI_DPHY so phy_mipi_dphy_get_default_config
can be used to determine the nominal values for a given resolution
and refresh rate.
Signed-off-by: Adam Ford
Tested-by: Frieder Schrempf
Reviewed-by: Frieder Schrempf
-
According to Table 13-45 of the i.MX8M Mini Reference Manual, the min
and max values for M and the frequency range for the VCO_out
calculator were incorrect. This information was contradicted in other
parts of the mini, nano and plus manuals. After reaching out to my
NXP Rep, when confronting him
Make the pll-clock-frequency optional. If it's present, use it
to maintain backwards compatibility with existing hardware. If it
is absent, read clock rate of "sclk_mipi" to determine the rate.
Since it can be optional, change the message from an error to
dev_info.
Signed-off-by: Adam Ford
Test
From: Lucas Stach
Scale the blanking packet sizes to match the ratio between HS clock
and DPI interface clock. The controller seems to do internal scaling
to the number of active lanes, so we don't take those into account.
Signed-off-by: Lucas Stach
Signed-off-by: Adam Ford
Tested-by: Chen-Yu
This series fixes the blanking packet size and the PMS calculation.
According to Lucas, "The blanking packets are MIPI long packets,
so 4 byte header, payload, 2 bytes footer."
It also dds support to allows the DSIM to dynamically DPHY clocks, and
support non-burst mode while allowing the removal o
On Fri, May 5, 2023 at 8:09 PM Adam Ford wrote:
>
> Make the pll-clock-frequency optional. If it's present, use it
> to maintain backwards compatibility with existing hardware. If it
> is absent, read clock rate of "sclk_mipi" to determine the rate.
>
> Signed-off-by: Adam Ford
> Tested-by: Che
to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url:
https://github.com/intel-lab-lkp/linux/commits/AngeloGioacchino-Del-Regno/drm-mediatek-gamma-Adjust-mtk_drm_gamma_set_common-parameters/20230506-203713
base: git://anongit.freed
On Fri, May 05, 2023 at 12:35:18PM +0200, Konrad Dybcio wrote:
>
>
> On 5.05.2023 10:46, Akhil P Oommen wrote:
> > On Thu, May 04, 2023 at 08:34:07AM +0200, Konrad Dybcio wrote:
> >>
> >>
> >> On 3.05.2023 22:32, Akhil P Oommen wrote:
> >>> On Tue, May 02, 2023 at 11:40:26AM +0200, Konrad Dybcio
Newer Gamma IP have got multiple LUT banks: support specifying the
size of the LUT banks and handle bank-switching before programming
the LUT in mtk_gamma_set_common() in preparation for adding support
for MT8195 and newer SoCs.
Suggested-by: Jason-JH.Lin
[Angelo: Refactored original commit]
Sign
Disable relay mode at the end of LUT programming to make sure that the
processed image goes through.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
b/drive
Add support for 12-bit gamma lookup tables and introduce the first
user for it: MT8195.
While at it, also reorder the variables in mtk_gamma_set_common()
and rename `lut_base` to `lut0_base` to improve readability.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_disp_
All of the SoCs that don't have dithering control in the gamma IP
have got a GAMMA_LUT_TYPE bit that tells to the IP if the LUT is
"descending" (bit set) or "rising" (bit cleared): make sure to set
it correctly after programming the LUT.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu
Make the code more robust and improve readability by using bitfield
macros instead of open coding bit operations.
While at it, also add a definition for LUT_BITS_DEFAULT.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 41 ++-
1 file
New SoCs, like MT8195, not only may support bigger lookup tables, but
have got a different register layout to support bigger precision:
support specifying the number of `lut_bits` for each SoC and use it
in mtk_gamma_set_common() to perform the right calculation.
Signed-off-by: AngeloGioacchino De
Move the write to DISP_GAMMA_CFG to enable the Gamma LUT to after
programming the actual table to avoid potential visual glitches during
table modification.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 13 -
1 file changed, 8 insertions(+
From: "Jason-JH.Lin"
Adjust the parameters in mtk_drm_gamma_set_common()
- add (struct device *dev) to get lut_diff from gamma's driver data
- remove (bool lut_diff) and use false as default value in the function
Signed-off-by: Jason-JH.Lin
Signed-off-by: AngeloGioacchino Del Regno
---
d
Use drm_color_lut_extract() to avoid open-coding the bits reduction
calculations for each color channel and use a struct drm_color_lut
to temporarily store the information instead of an array of u32.
Also, slightly improve the precision of the HW LUT calculation in the
LUT DIFF case by performing
Newer SoCs support a bigger Gamma LUT table: wire up a callback
to retrieve the correct LUT size for each different Gamma IP.
Co-developed-by: Jason-JH.Lin
Signed-off-by: Jason-JH.Lin
[Angelo: Rewritten commit message/description + porting]
Signed-off-by: AngeloGioacchino Del Regno
---
driver
Invert the check for state->gamma_lut and move it at the beginning
of the function to reduce indentation: this prepares the code for
keeping readability on later additions.
This commit brings no functional changes.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_disp
Changes in v3:
- Fixed issues due to variables renaming during cleanup (oops)
- This is actually the right series, since v2 was taken from the
wrong kernel tree :-)
Changes in v2:
- Added explicit inclusion of linux/bitfield.h in patch [06/11]
This series adds support for GAMMA IP requi
On 5/2/2023 8:05 AM, Dmitry Baryshkov wrote:
Get rid of intermediatory configuration structure and defines. Pass the
format and the enablement bit directly to the new helper. The
WB_CDP_CNTL register ignores BIT(2), so we can write it for both SSPP
and WB CDP settings.
Signed-off-by: Dmitry B
On 5/2/2023 8:05 AM, Dmitry Baryshkov wrote:
The function dpu_plane_sspp_update_pipe() contains code to skip enabling
the QoS and OT limitis for CURSOR pipes. However all DPU since sdm845
repurpose DMA SSPP for the cursor planes because they lack the real
CURSOR SSPP. Fix the condition to actu
On 5/2/2023 8:05 AM, Dmitry Baryshkov wrote:
Now as the struct dpu_hw_pipe_qos_cfg consists of only one bool field,
drop the structure and use corresponding bool directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 10 +++---
drivers/gpu/drm/msm/
On 5/2/2023 8:05 AM, Dmitry Baryshkov wrote:
Drop support for DPU_PLANE_QOS_VBLANK_CTRL flag. It is not used both
in upstream driver and in vendor SDE driver.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw
Hi,
On 5/5/23 21:39, Hamza Mahfooz wrote:
Hey Huacai,
On 5/5/23 07:32, Huacai Chen wrote:
Now LoongArch provides kernel_fpu_begin() and kernel_fpu_end() in commit
2b3bd32ea3a22ea2d ("LoongArch: Provide kernel fpu functions"), so we can
enable DC_FP for DCN devices.
Have you had the chance t
From: Maximilian Weigand
Use display_is_blank() to determine if the led strings should be turned
off in the update_status() functions of both strings.
Signed-off-by: Maximilian Weigand
---
drivers/video/backlight/lm3630a_bl.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff
On 5/2/2023 8:05 AM, Dmitry Baryshkov wrote:
Reorder SSPP register definitions to sort them in the ascending order.
Move register bitfields after the register definitions.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 66 +++--
1 file ch
On 5/2/2023 8:05 AM, Dmitry Baryshkov wrote:
Rework SSPP and WB code to use common helper for programming QoS
settings.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 31 ++-
drivers/gpu/drm/m
On 5/2/2023 8:05 AM, Dmitry Baryshkov wrote:
This flag is always passed to _dpu_plane_set_qos_ctrl(), so drop it and
remove corresponding conditions from the mentioned function.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 27 +++
1 f
On 5/6/23 02:00, Alex Deucher wrote:
On Fri, May 5, 2023 at 1:57 PM WANG Xuerui wrote:
On a side note, I had to modprobe amdgpu with runpm=0, otherwise my
dmesg gets flooded with PSP getting resumed every 8~10 seconds or so. I
currently have none of the connectors plugged in. I didn't notice a
On 5/2/2023 8:05 AM, Dmitry Baryshkov wrote:
After removal of DPU_PLANE_QOS_VBLANK_CTRL, several fields of struct
dpu_hw_pipe_qos_cfg are fixed to false/0. Drop them from the structure
(and drop the corresponding code from the functions).
The DPU_PLANE_QOS_VBLANK_AMORTIZE flag is also removed
On Fri, May 05, 2023 at 10:47:58AM +0800, kernel test robot wrote:
> tree/branch:
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
> branch HEAD: 145e5cddfe8b4bf607510b2dcf630d95f4db420f Add linux-next
> specific files for 20230504
>
> Error/Warning reports:
>
> https
On 5/2/2023 8:05 AM, Dmitry Baryshkov wrote:
Slightly rearrainge code in dpu_plane_sspp_update_pipe() to group
QoS/LUT related functions.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff
Hi, Hamza,
On Fri, May 5, 2023 at 9:37 PM Hamza Mahfooz wrote:
>
>
> Hey Huacai,
>
> On 5/5/23 07:32, Huacai Chen wrote:
> > Now LoongArch provides kernel_fpu_begin() and kernel_fpu_end() in commit
> > 2b3bd32ea3a22ea2d ("LoongArch: Provide kernel fpu functions"), so we can
> > enable DC_FP for D
Optimize flickering problem and power off sequence GOP timing at sleep in mode.
When display sleep in raise the potential of all GOP signals to VGHO and then
lower to GND.
Signed-off-by: Cong Yang
---
.../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 397 +++---
1 file changed, 235 ins
On 04 5月 23 09:12:40, Oded Gabbay wrote:
> On Thu, May 4, 2023 at 6:00 AM Cai Huoqing wrote:
> >
> > On 30 4月 23 09:36:29, Oded Gabbay wrote:
> > > On Fri, Apr 28, 2023 at 5:49 PM Cai Huoqing wrote:
> > > >
> > > > Using rhashtable to accelerate the search for userptr by address,
> > > > instead
Optimize flickering problem and power off sequence GOP timing at sleep in mode.
When display sleep in raise the potential of all GOP signals to VGHO and then
lower to GND.
Signed-off-by: Cong Yang
---
.../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 391 +++---
1 file changed, 232 ins
Hi,
Ah, I did't notice this.
The disorder is because during developing phase,
it is more easy amend new changes to the top of the commits.
So, I put another patch of this series on the top of this.
Will be fixed at next version, thanks for you point out that.
On 2023/5/6 11:09, Huacai Chen
Variable golden_settings_gc_9_4_3 is not effectively used, so delete it.
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c:48:38: warning:
‘golden_settings_gc_9_4_3’ defined but not used.
Reported-by: Abaci Robot
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=4877
Signed-off-by: Jiapeng Chong
---
static u64 mtl_pte_encode(dma_addr_t addr,
- enum i915_cache_level level,
+ unsigned int pat_index,
u32 flags)
>>> Prototype and implementation changed here for mtl_pte_encode.
>>>
>>> And we have:
>>>
>>
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 83e5775d7afda68f6d7576d21f7a080fbfeecc4f Add linux-next specific
files for 20230505
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202304102354.q4voxgte-...@intel.com
https://lore
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