On Fri, 19 May 2023 14:19:41 -0700 Justin Chen wrote:
> Add support for the Broadcom ASP 2.0 Ethernet controller which is first
> introduced with 72165. This controller features two distinct Ethernet
> ports that can be independently operated.
>
> This patch supports:
>
> - Wake-on-LAN using
The pull request you sent on Sat, 20 May 2023 11:09:38 +1000:
> git://anongit.freedesktop.org/drm/drm tags/drm-fixes-2023-05-20
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/d635f6cc934bcd467c5d67148ece74632fd96abf
Thank you!
--
Deet-doot-dot, I am a bot.
Hi,Doug, Thank you very much for your suggestion. It seems that this
cannot be changed on the hardware(already discussed with vendor, TDDI's IC
design is this) we really want the touchscreen to power on and off
together with the panel, where the panel is in charge and the touchscreen
always
On 19/05/2023 20:04, Konrad Dybcio wrote:
It got broken at some point, fix it up.
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On 19/05/2023 20:04, Konrad Dybcio wrote:
Add support for MDSS on SM6375.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/msm_mdss.c | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
On 19/05/2023 20:04, Konrad Dybcio wrote:
Add basic SM6375 support to the DPU1 driver to enable display output.
Signed-off-by: Konrad Dybcio
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 153 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
On 15/05/2023 06:02, Bjorn Andersson wrote:
The dp_power module keeps track of both the DP controller's struct
platform_device and struct device - with the prior pulled out of the
dp_parser module.
Clean up the duplication by dropping the platform_device reference and
just track the passed
On 15/05/2023 06:02, Bjorn Andersson wrote:
The clk_bulk API already provides error messages indicating which
specific clock in the request for which the operation failed, further
more these errors are associated with the specific DisplayPort
controller (rather than the shared drm_device). The
On 15/05/2023 06:02, Bjorn Andersson wrote:
The dp_hpd module is a remnant from the downstream design and is now
completely unused. Drop it and all references to it.
Signed-off-by: Bjorn Andersson
---
drivers/gpu/drm/msm/dp/dp_debug.c | 8 ++-
drivers/gpu/drm/msm/dp/dp_debug.h | 12
Hi Linus,
Regular fixes pull, amdgpu and msm make up most of these, nothing too
serious, also one i915 and one exynos. I didn't get a misc fixes pull
this week (one of the maintainers is off, so have to engage the
backup) so I think there are a few outstanding patches that will show
up next week,
Simplify calculatoins around pixel_clk_rate division. Replace common
pattern of doing 64-bit multiplication and then a do_div() call with
simpler mult_frac call.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 11 ---
1 file changed, 4 insertions(+), 7
In dsi_calc_clk_rate_v2() there is no need to call dsi_get_pclk_rate().
This functions has just been called and it's result is stored at
msm_host->pixel_clk_rate. Use this variable directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 2 +-
1 file changed, 1
On 5/19/2023 11:45 AM, John Harrison wrote:
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
Before we add the second step of the MTL HuC auth (via GSC), we need to
have the ability to differentiate between them. To do so, the huc
authentication check is duplicated for GuC and GSC auth,
On 5/19/2023 11:03 AM, John Harrison wrote:
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
In the previous patch we extracted the offset of the legacy-style HuC
binary located within the GSC-enabled blob, so now we can use that to
load the HuC via DMA if the fuse is set that way.
Note
On msm8998/sdm845 some LM blocks do not have corresponding PINGPONG
block. Currently the driver uses PINGPONG_MAX for such cases. Switch
that to use PINGPONG_NONE instead, which is more logical.
Reviewed-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
dpu_rm_init() contains checks for block->id values. These were logical
in the vendor driver, when one can not be sure which values were passed
from DT. In the upstream driver this is not necessary: the catalog is a
part of the driver, we control specified IDs.
Suggested-by: Marijn Suijten
Using IS_ERR_OR_NULL() together with PTR_ERR() is a typical mistake. If
the value is NULL, then the function will return 0 instead of a proper
return code. Moreover dpu_hw_dsc_init() can not return NULL.
Replace the IS_ERR_OR_NULL() call with IS_ERR().
This follows the commit 740828c73a36
Move the check for lm->pingpong being not NONE from dpu_rm_init() to
dpu_lm_init(), following the change to dpu_hw_intf_init().
Suggested-by: Marijn Suijten
Reviewed-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 5 +
Implement several small simplifications for the DPU resource manager.
The ideas behind these patches were suggested by Marijn.
Changes since v1:
- Reworded commit message for the patch 1 (Marijn)
- Fixed documentation for dpu_lm_cfg::pingpong (Marijn)
- Added Suggested-by to the last patch
On 20/05/2023 00:16, Rodrigo Vivi wrote:
On Fri, May 19, 2023 at 07:55:47PM +0300, Dmitry Baryshkov wrote:
On 19/04/2023 18:43, Mark Yacoub wrote:
Hi all,
This is v10 of the HDCP patches. The patches are authored by Sean Paul.
I rebased and addressed the review comments in v6-v10.
Main change
On 5/19/2023 2:24 PM, Marijn Suijten wrote:
On 2023-05-19 14:17:30, Jessica Zhang wrote:
Currently, slice_count is being used to calculate word count and
pkt_per_line. In downstream, these values are calculated using slice per
packet, which is not the same as slice_count.
Slice count
On 20.05.2023 00:00, Abhinav Kumar wrote:
>
>
> On 5/19/2023 11:49 AM, Konrad Dybcio wrote:
>> DPU5 and newer targets enable this unconditionally. Move it from the
>> SC7280 mask to the SC7180 one.
>>
>
> You mean DPU 5.0.0 right?
Yep!
>
>> Fixes: 7e6ee55320f0 ("drm/msm/disp/dpu1: enable
https://bugzilla.kernel.org/show_bug.cgi?id=217464
Bug ID: 217464
Summary: Radeon Driver Crash
Product: Drivers
Version: 2.5
Hardware: AMD
OS: Linux
Status: NEW
Severity: high
Priority: P3
On 5/19/2023 11:49 AM, Konrad Dybcio wrote:
DPU5 and newer targets enable this unconditionally. Move it from the
SC7280 mask to the SC7180 one.
You mean DPU 5.0.0 right?
Fixes: 7e6ee55320f0 ("drm/msm/disp/dpu1: enable DATA_HCTL_EN for sc7280 target")
Reviewed-by: Dmitry Baryshkov
On 2023-05-19 14:17:28, Jessica Zhang wrote:
> Add DATA_COMPRESS feature flag to DPU INTF block.
>
> In DPU 7.x and later, DSC/DCE enablement registers have been moved from
> PINGPONG to INTF.
>
> Reviewed-by: Marijn Suijten
> Signed-off-by: Jessica Zhang
> ---
>
On 2023-05-19 14:17:26, Jessica Zhang wrote:
> Currently, when compression is enabled, hdisplay is reduced via integer
> division. This causes issues for modes where the original hdisplay is
> not a multiple of 3.
The "issue" probably being some kind of underflow, because the stream
size is too
On 2023-05-19 14:17:30, Jessica Zhang wrote:
> Currently, slice_count is being used to calculate word count and
> pkt_per_line. In downstream, these values are calculated using slice per
> packet, which is not the same as slice_count.
>
> Slice count represents the number of soft slices per
On 2023-05-19 12:04:00, Jessica Zhang wrote:
> >>> + /* If DSC is enabled, divide hdisplay by compression ratio */
> >>> + if (dsc) {
> >>> + int new_hdisplay = DIV_ROUND_UP(mode->hdisplay *
> >>> msm_dsc_get_bpp_int(dsc),
> >>> + dsc->bits_per_component * 3);
>
Currently, slice_count is being used to calculate word count and
pkt_per_line. In downstream, these values are calculated using slice per
packet, which is not the same as slice_count.
Slice count represents the number of soft slices per interface, and its
value will not always match that of slice
Add a DPU INTF op to set DATA_COMPRESS register if the
DPU_INTF_DATA_COMPRESS feature is enabled. This bit needs to be set in
order for DSC v1.2 to work.
Note: For now, this op is called for command mode encoders only. Changes to
set DATA_COMPRESS for video mode encoders will be posted along with
Currently, when compression is enabled, hdisplay is reduced via integer
division. This causes issues for modes where the original hdisplay is
not a multiple of 3.
To fix this, use DIV_ROUND_UP to divide hdisplay.
Reported-by: Marijn Suijten
Fixes: f3a99460406b ("drm/msm/dsi: update hdisplay
Add DATA_COMPRESS feature flag to DPU INTF block.
In DPU 7.x and later, DSC/DCE enablement registers have been moved from
PINGPONG to INTF.
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
This is a series of changes for DSI to enable command mode support
for DSC v1.2.
This includes:
1) Rounding up `hdisplay / 3` in dsc_timing_setup()
2) Adjusting pclk_rate to account for compression
3) Fixing incorrect uses of slice_count in DSI DSC calculations
4) Setting the DATA_COMPRESS bit
Adjust the pclk rate to divide hdisplay by the compression ratio when DSC
is enabled.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
On Fri, May 19, 2023 at 07:55:47PM +0300, Dmitry Baryshkov wrote:
> On 19/04/2023 18:43, Mark Yacoub wrote:
> > Hi all,
> > This is v10 of the HDCP patches. The patches are authored by Sean Paul.
> > I rebased and addressed the review comments in v6-v10.
> >
> > Main change in v10 is handling the
Use the newly introduced usb_control_msg_send() instead of usb_control_msg()
when selecting the channel.
Signed-off-by: Helge Deller
---
drivers/video/fbdev/udlfb.c | 14 +++---
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/drivers/video/fbdev/udlfb.c
On 2023-05-19 22:37:34, Dmitry Baryshkov wrote:
> >> + ret = cfg_hnd->ops->calc_clk_rate(msm_host);
> >
> > I am not too sure what we are gaining by this.
> >
> > Its not that we are replacing dsi_get_pclk_rate().
> >
> > We are moving the dsi_get_pclk_rate() from
On Wed, May 17, 2023 at 01:02:03PM +0800, Cong Liu wrote:
> Be sure to properly free the allocated memory before exiting
> the live_nop_switch function.
>
> Signed-off-by: Cong Liu
> Suggested-by: Rodrigo Vivi
pushed, thanks for the patch
> ---
>
On Fri, May 19, 2023 at 07:36:56PM +, Prahlad Kilambi wrote:
> > One question is are we able to find a "one size fits all" values.
>
> > However regardless of that, given we already expose frequency controls in
> > sysfs
> > with the same reasoning of allowing system owners explicit control
On Fri, Apr 28, 2023 at 09:14:56AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> In preparation for exposing via sysfs add helpers for managing rps
> thresholds.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/gt/intel_rps.c | 36 +
>
On Fri, Apr 28, 2023 at 09:44:53AM +0100, Tvrtko Ursulin wrote:
>
> On 28/04/2023 09:14, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > User feedback indicates significant performance gains are possible in
> > specific games with non default RPS up/down thresholds.
> >
> > Expose these
On 5/17/2023 2:04 PM, John Harrison wrote:
On 5/2/2023 08:27, Daniele Ceraolo Spurio wrote:
The new binaries that support the 2-step authentication have contain the
have contain?
legacy-style binary, which we can use for loading the HuC via DMA. To
find out where this is located in the
On 19/05/2023 22:36, Abhinav Kumar wrote:
On 5/19/2023 12:33 PM, Dmitry Baryshkov wrote:
On 19/05/2023 21:54, Jessica Zhang wrote:
On 3/28/2023 6:04 AM, Dmitry Baryshkov wrote:
On 26/01/2023 02:07, Abhinav Kumar wrote:
On 1/18/2023 5:00 AM, Dmitry Baryshkov wrote:
Move a call to
> One question is are we able to find a "one size fits all" values.
> However regardless of that, given we already expose frequency controls in
> sysfs
> with the same reasoning of allowing system owners explicit control if so
> wanted,
> I think exposing the thresholds can be equally
On 5/19/2023 12:33 PM, Dmitry Baryshkov wrote:
On 19/05/2023 21:54, Jessica Zhang wrote:
On 3/28/2023 6:04 AM, Dmitry Baryshkov wrote:
On 26/01/2023 02:07, Abhinav Kumar wrote:
On 1/18/2023 5:00 AM, Dmitry Baryshkov wrote:
Move a call to dsi_calc_pclk() out of calc_clk_rate directly
On 19/05/2023 20:04, Konrad Dybcio wrote:
Add SM6350 support to the DPU1 driver to enable display output.
It's worth noting that one entry dpu_qos_lut_entry was trimmed off:
{.fl = 0, .lut = 0x0011223344556677 },
due to the fact that newer SoCs dropped the .fl (fill level)-based
logic and
On 19/05/2023 21:54, Jessica Zhang wrote:
On 3/28/2023 6:04 AM, Dmitry Baryshkov wrote:
On 26/01/2023 02:07, Abhinav Kumar wrote:
On 1/18/2023 5:00 AM, Dmitry Baryshkov wrote:
Move a call to dsi_calc_pclk() out of calc_clk_rate directly towards
msm_dsi_host_get_phy_clk_req(). It is called
On 19.05.2023 21:05, Rob Herring wrote:
>
> On Fri, 19 May 2023 19:04:26 +0200, Konrad Dybcio wrote:
>> Document the SM6375 MDSS.
>>
>> Signed-off-by: Konrad Dybcio
>> ---
>> .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216
>> +
>> 1 file changed, 216
On Fri, 19 May 2023 19:04:26 +0200, Konrad Dybcio wrote:
> Document the SM6375 MDSS.
>
> Signed-off-by: Konrad Dybcio
> ---
> .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216
> +
> 1 file changed, 216 insertions(+)
>
My bot found errors running 'make
On 5/8/2023 2:56 PM, Marijn Suijten wrote:
On 2023-05-05 14:49:08, Jessica Zhang wrote:
On 5/5/2023 2:23 PM, Jessica Zhang wrote:
Adjust the pclk rate to divide hdisplay by the compression ratio when DSC
is enabled.
Changes in v2:
- Adjusted pclk_rate math to divide only the hdisplay value
On 3/28/2023 6:04 AM, Dmitry Baryshkov wrote:
On 26/01/2023 02:07, Abhinav Kumar wrote:
On 1/18/2023 5:00 AM, Dmitry Baryshkov wrote:
Move a call to dsi_calc_pclk() out of calc_clk_rate directly towards
msm_dsi_host_get_phy_clk_req(). It is called for both 6g and v2 hosts.
Also, while we
DPU5 and newer targets enable this unconditionally. Move it from the
SC7280 mask to the SC7180 one.
Fixes: 7e6ee55320f0 ("drm/msm/disp/dpu1: enable DATA_HCTL_EN for sc7280 target")
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Konrad Dybcio
---
Depends on:
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
Before we add the second step of the MTL HuC auth (via GSC), we need to
have the ability to differentiate between them. To do so, the huc
authentication check is duplicated for GuC and GSC auth, with meu
binaries being considered fully
On 5/19/23 17:42, Alan Stern wrote:
On Fri, May 19, 2023 at 12:38:15PM +0200, Helge Deller wrote:
Patch looks good and survived the test.
Will you send a proper patch to the fbdev mailing list, so that I can
include it?
Will do.
Great! Thanks!
While you're working on this driver,
I'm
On some devices the +5V Power pin of the HDMI connector and/or the ESD
protection logic is powered on by a separate regulator. Instead of
declaring this regulator as always-on, make hdmi-connector support the
additional hdmi-pwr supply.
Signed-off-by: Dmitry Baryshkov
---
Follow the dp-connector example and add hdmi-pwr supply to drive the 5V
pin of the HDMI connector (together with some simple glue logic possibly
attached to the connector).
Reviewed-by: Laurent Pinchart
Acked-by: Krzysztof Kozlowski
Signed-off-by: Dmitry Baryshkov
---
In preparation to adding support for the hdmi_pwr supply, rename dp_pwr
structure field to the generic connector_pwr.
Reviewed-by: Laurent Pinchart
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/display-connector.c | 18 +-
1 file changed, 9 insertions(+), 9
On some devices the 5V pin of the HDMI connector and/or the ESD
protection logic is powered on by a separate regulator. The dp-connector
for such usecases provides dp-pwr supply support. Follow this example
and make hdmi-connector support the hdmi-pwr supply.
Changes since v1:
- Changed the pin
Visible glitches have been observed when running graphics applications on
Linux under Xen hypervisor. Those observations have been confirmed with
failures from kms_pwrite_crc Intel GPU test that verifies data coherency
of DRM frame buffer objects using hardware CRC checksums calculated by
display
On Fri, May 19, 2023 at 07:03:52PM +0200, Artur Weber wrote:
> Add bindings for the S6D7AA0 LCD panel controller, including the
> S6D7AA0-LSL080AL02 panel used in the Samsung Galaxy Tab 3 8.0 family
> of tablets, and the S6D7AA0-LSL080AL03 and S6D7AA0-LTL101AT01 panels
> used in the Samsung Galaxy
On 2023-05-19 19:04:21, Konrad Dybcio wrote:
> v3 -> v4:
> - Drop adding new QoS LUT entries
> - Add safe_lut_tbl for both SoCs
I may not have pinged you correctly with this message [1], but can you
add the DSC configuration for both SoCs?
[1]:
Also deprecate the pwm-period DT property, as it is now redundant
(pwms property already contains period value).
Signed-off-by: Artur Weber
---
drivers/video/backlight/lp855x_bl.c | 48 -
1 file changed, 26 insertions(+), 22 deletions(-)
diff --git
Change underscores in ROM node names to dashes, and remove deprecated
pwm-period property.
Signed-off-by: Artur Weber
---
arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git
Notable changes:
- ROM child nodes use dashes instead of underscores; the driver
reads all child nodes regardless of their names, so this doesn't
break ABI.
- pwm-period argument is deprecated, as it effectively duplicates
the period value provided in pwms. The driver continues to accept
Convert TI LP855X backlight controller bindings from TXT to YAML and,
while we're at it, rework some of the code related to PWM handling.
Also correct existing DTS files to avoid introducing new dtb_check
errors.
Signed-off-by: Artur Weber
Changed in v2:
- Added additionalProperties to ROM
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
In the previous patch we extracted the offset of the legacy-style HuC
binary located within the GSC-enabled blob, so now we can use that to
load the HuC via DMA if the fuse is set that way.
Note that we now need to differentiate between
Fannal C3004 is a 2 lane MIPI DSI 480x800 panel which requires initialization
with DSI DCS commands. After some commands delay is required.
In previous discussions for device tree [1] [2] and device driver [3] were
named mipi-dsi-bringup.
[1]
Added fannal to vendor-prefixes and dt bindings for Fannal C3004.
Fannal C3004 is a 480x800 MIPI DSI Panel which requires
DCS initialization sequences with certain delays between certain
commands.
Signed-off-by: Paulo Pavacic
---
v3 changelog:
- renamed yml file
- refactored yml file to
Fannal C3004 is a 480x800 display made by fannal that requires
DCS initialization sequences.
Signed-off-by: Paulo Pavacic
---
v2 changelog:
- renamed from panel-mipi-dsi-bringup
- only one MAINTAINER e-mail
---
MAINTAINERS| 1 +
I test this on my 3A5000 + 7A1000 and 3A5000 + 7A2000 desktop,
and this works well, so:
Tested-by: Liu Peibao
Br,
Peibao
On 5/15/23 11:57 PM, Sui Jingfeng wrote:
> Loongson display controller IP has been integrated in both Loongson north
> bridge chipset(ls7a1000/ls7a2000) and Loongson
On Tue, Apr 11, 2023 at 3:46 PM Dmitry Baryshkov
wrote:
>
> On 12/04/2023 01:43, Marijn Suijten wrote:
> > As I get more and more active in the drm/msm space, yet sometimes miss
> > out on patches (where I was involved in previous discussions), add
> > myself as reviewer to make this involvement
Hi,
On Fri, May 19, 2023 at 1:02 AM Cong Yang
wrote:
>
> The Starry-himax83102-j02 panel is a TDDI IC. From the datasheet[1],
> it seems that the touch can communicate successfully only when the RST
> signal is high. Since i2c_hid_core_probe comes after boe_panel_prepare
> let's set the default
In practice this should never happen. Applied with some minor coding
style fixes.
Alex
On Fri, May 19, 2023 at 11:33 AM Nikita Zhandarovich
wrote:
>
> Function rv740_get_decoded_reference_divider() may return 0 due to
> unpredictable reference divider value calculated in
>
On 19/05/2023 20:03, Dmitry Baryshkov wrote:
The regdma is currently not used by the current driver. We have no way
to practically verify that the regdma is described correctly. Drop it
now.
Signed-off-by: Dmitry Baryshkov
---
Changes since v1:
- Restored dpu_msm8998_cfg.perf, incorrectly
Add the SM6375 DPU compatible to clients compatible list, as it also
needs the workarounds.
Acked-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
From: Konrad Dybcio
Add the SM6350 DPU compatible to clients compatible list, as it also
needs the workarounds.
Signed-off-by: Konrad Dybcio
Acked-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff
Add support for MDSS on SM6375.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/msm_mdss.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index
It got broken at some point, fix it up.
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index
Add support for MDSS on SM6350.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/msm_mdss.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index
Document the SM6375 MDSS.
Signed-off-by: Konrad Dybcio
---
.../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +
1 file changed, 216 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
Add basic SM6375 support to the DPU1 driver to enable display output.
Signed-off-by: Konrad Dybcio
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 153 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |
Add SM6350 support to the DPU1 driver to enable display output.
It's worth noting that one entry dpu_qos_lut_entry was trimmed off:
{.fl = 0, .lut = 0x0011223344556677 },
due to the fact that newer SoCs dropped the .fl (fill level)-based
logic and don't provide real values, resulting in all
Document the SM6350 MDSS.
Signed-off-by: Konrad Dybcio
---
.../bindings/display/msm/qcom,sm6350-mdss.yaml | 214 +
1 file changed, 214 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
Add the DSI host found on SM6375.
Acked-by: Rob Herring
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
SC7180, SM6350 and SM6375 use a rather similar hw setup for DPU, with
the main exception being that the last one requires an additional
throttle clock.
It is not well understood yet, but failing to toggle it on makes the
display hardware stall and not output any frames.
Document SM6350 and
Add the DSI host found on SM6350.
Acked-by: Rob Herring
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
v3 -> v4:
- Drop adding new QoS LUT entries
- Add safe_lut_tbl for both SoCs
Depends on:
-
https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v4-0-27ce1a5ab...@somainline.org/
v3:
https://lore.kernel.org/r/20230411-topic-straitlagoon_mdss-v3-0-9837d6b35...@linaro.org
v2 -> v3:
- Don't
Add myself as maintainer of the Samsung S6D7AA0 panel driver.
Signed-off-by: Artur Weber
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 402e26d0cdbc..7cc2bfa4af6f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6663,6 +6663,12 @@ S:
Initial driver for S6D7AA0-controlled panels. Currently, the following
panels are supported:
- S6D7AA0-LSL080AL02 (Samsung Galaxy Tab 3 8.0)
- S6D7AA0-LSL080AL03 (Samsung Galaxy Tab A 8.0 2015)
- S6D7AA0-LTL101AT01 (Samsung Galaxy Tab A 9.7 2015)
It should be possible to extend this driver to
Add bindings for the S6D7AA0 LCD panel controller, including the
S6D7AA0-LSL080AL02 panel used in the Samsung Galaxy Tab 3 8.0 family
of tablets, and the S6D7AA0-LSL080AL03 and S6D7AA0-LTL101AT01 panels
used in the Samsung Galaxy Tab A 8.0 and 9.7 2015.
Signed-off-by: Artur Weber
---
Changed in
This patchset adds initial support for Samsung S6D7AA0-based panels.
Currently, the following panels are supported:
- S6D7AA0-LSL080AL02 (Samsung Galaxy Tab 3 8.0)
- S6D7AA0-LSL080AL03 (Samsung Galaxy Tab A 8.0 2015)
- S6D7AA0-LTL101AT01 (Samsung Galaxy Tab A 9.7 2015)
Changed in v2:
- Added
The regdma is currently not used by the current driver. We have no way
to practically verify that the regdma is described correctly. Drop it
now.
Signed-off-by: Dmitry Baryshkov
---
Changes since v1:
- Restored dpu_msm8998_cfg.perf, incorrectly removed previously (Marijn)
- Also dropped reg_dma
Applied. Thanks!
On Thu, May 18, 2023 at 9:52 AM Christoph Hellwig wrote:
>
> radeon does not need swiotlb.h, so stop including it.
>
> Signed-off-by: Christoph Hellwig
> ---
> drivers/gpu/drm/radeon/radeon_ttm.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git
Applied. Thanks!
On Thu, May 18, 2023 at 9:52 AM Christoph Hellwig wrote:
>
> amdgpu does not need swiotlb.h, so stop including it.
>
> Signed-off-by: Christoph Hellwig
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git
On 19/04/2023 18:43, Mark Yacoub wrote:
Hi all,
This is v10 of the HDCP patches. The patches are authored by Sean Paul.
I rebased and addressed the review comments in v6-v10.
Main change in v10 is handling the kernel test bot warnings.
Patches 1-4 focus on moving the common HDCP helpers to
On 03/04/2023 19:11, Dmitry Baryshkov wrote:
On Mon, 3 Apr 2023 at 15:01, Vinod Polimera wrote:
On Fri, 31 Mar 2023 at 16:59, Vinod Polimera
wrote:
In certain CPU stress conditions, there can be a delay in scheduling commit
work and it was observed that PSR commit from a different work
Hey Paulo,
On Fri, May 19, 2023 at 04:24:55PM +0200, Paulo Pavacic wrote:
>
> Added fannal to vendor-prefixes and dt bindings for Fannal C3004.
> Fannal C3004 is a 480x800 MIPI DSI Panel which requires
> DCS initialization sequences with certain delays between certain
> commands.
>
>
Some devices might require special handling due to flawed implementations
or other reasons. Implement a quirk framework to handle these situations.
Implement the first quirk in this framework -
MHI_QUIRK_SOC_HW_VERSION_UNRELIABLE
The MHI spec indicates that the MHI device must initialize the
AIC100 does not initialize the SOC_HW_VERSION MHI register as expected.
Some instances of AIC100 are observed to have 0x in this register
which makes the controller think that the link is down and return an error
up to MHI. This results in a failed initialization.
Allow these cards to
With the QAIC driver in -next, I'd like to suggest some MHI changes that
specific to AIC100 devices, but perhaps provide a framework for other
device oddities.
AIC100 devices technically violate the MHI spec in two ways. Sadly, these
issues comes from the device hardware, so host SW needs to work
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