On 2023-05-22 13:30:20, Jessica Zhang wrote:
> Currently, when compression is enabled, hdisplay is reduced via integer
> division. This causes issues for modes where the original hdisplay is
> not a multiple of 3.
>
> To fix this, use DIV_ROUND_UP to divide hdisplay.
>
> Reviewed-by: Marijn Suijt
[Public]
> -Original Message-
> From: Kees Cook
> Sent: Monday, May 22, 2023 4:16 PM
> To: Azeem Shaikh
> Cc: Quan, Evan ; linux-harden...@vger.kernel.org;
> amd-...@lists.freedesktop.org; linux-ker...@vger.kernel.org; Deucher,
> Alexander ; Koenig, Christian
> ; Pan, Xinhui ; David
> Ai
[Public]
> -Original Message-
> From: Kees Cook
> Sent: Monday, May 22, 2023 4:15 PM
> To: Azeem Shaikh
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Pan, Xinhui ; linux-
> harden...@vger.kernel.org; amd-...@lists.freedesktop.org; linux-
> ker...@vger.kernel.org; David Airlie ; Daniel
Yes:
https://lore.kernel.org/dri-devel/20220929184307.258331-1-cont...@emersion.fr/
Add a DPU INTF op to set DATA_COMPRESS register if the
DPU_INTF_DATA_COMPRESS feature is enabled. This bit needs to be set in
order for DSC v1.2 to work.
Note: For now, this op is called for command mode encoders only. Changes to
set DATA_COMPRESS for video mode encoders will be posted along with
Currently, slice_count is being used to calculate word count and
pkt_per_line. Instead, these values should be calculated using slice per
packet, which is not the same as slice_count.
Slice count represents the number of soft slices per interface, and its
value will not always match that of slice
Add DATA_COMPRESS feature flag to DPU INTF block.
In DPU 7.x and later, DSC/DCE enablement registers have been moved from
PINGPONG to INTF.
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_
Adjust the pclk rate to divide hdisplay by the compression ratio when DSC
is enabled.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu
Currently, when compression is enabled, hdisplay is reduced via integer
division. This causes issues for modes where the original hdisplay is
not a multiple of 3.
To fix this, use DIV_ROUND_UP to divide hdisplay.
Reviewed-by: Marijn Suijten
Suggested-by: Marijn Suijten
Fixes: 08802f515c3cf ("dr
This is a series of changes for DSI to enable command mode support
for DSC v1.2.
This includes:
1) Rounding up `hdisplay / 3` in dsc_timing_setup()
2) Adjusting pclk_rate to account for compression
3) Fixing incorrect uses of slice_count in DSI DSC calculations
4) Setting the DATA_COMPRESS bit wh
This fixes a NULL pointer access inside nvkm_acr_oneinit in case necessary
firmware files couldn't be loaded.
Closes: https://gitlab.freedesktop.org/drm/nouveau/-/issues/212
Fixes: 4b569ded09fd ("drm/nouveau/acr/ga102: initial support")
Signed-off-by: Karol Herbst
---
drivers/gpu/drm/nouveau/nvk
On 22/05/2023 22:30, Kuogee Hsieh wrote:
DSC flush bit is the bit 22 of CTL flush register. BIT(22) is expected
to be written to CTL flush register to indicates that DSC is ready for
flush. However 0x22 (BIT(1) and BIT(5)) was written mistakenly at current
DSC_IDX is 22, not 0x22.
implementat
Clearing out report id and timestamp as means to detect unlanded reports
only works if report size is power of 2. That is, only when report size is
a sub-multiple of the OA buffer size can we be certain that reports will
land at the same place each time in the OA buffer (after rewind). If report
si
On 22/05/2023 23:08, Kuogee Hsieh wrote:
The internal_hpd flag was introduced to handle external DP HPD derived
from GPIO pinmuxed into DP controller. HPD plug/unplug interrupts cannot
be enabled until internal_hpd flag is set to true.
At both bootup and resume time, the DP driver will enable ext
On Mon, May 22, 2023 at 03:53:50PM +, Azeem Shaikh wrote:
> strlcpy() reads the entire source buffer first.
> This read may exceed the destination size limit.
> This is both inefficient and can lead to linear read
> overflows if a source string is not NUL-terminated [1].
> In an effort to remov
On Mon, May 22, 2023 at 03:53:31PM +, Azeem Shaikh wrote:
> strlcpy() reads the entire source buffer first.
> This read may exceed the destination size limit.
> This is both inefficient and can lead to linear read
> overflows if a source string is not NUL-terminated [1].
> In an effort to remov
On Mon, May 22, 2023 at 03:53:06PM +, Azeem Shaikh wrote:
> strlcpy() reads the entire source buffer first.
> This read may exceed the destination size limit.
> This is both inefficient and can lead to linear read
> overflows if a source string is not NUL-terminated [1].
> In an effort to remov
On Mon, May 22, 2023 at 03:52:45PM +, Azeem Shaikh wrote:
> strlcpy() reads the entire source buffer first.
> This read may exceed the destination size limit.
> This is both inefficient and can lead to linear read
> overflows if a source string is not NUL-terminated [1].
> In an effort to remov
On Mon, May 22, 2023 at 03:52:28PM +, Azeem Shaikh wrote:
> strlcpy() reads the entire source buffer first.
> This read may exceed the destination size limit.
> This is both inefficient and can lead to linear read
> overflows if a source string is not NUL-terminated [1].
> In an effort to remov
On Mon, May 22, 2023 at 03:52:10PM +, Azeem Shaikh wrote:
> strlcpy() reads the entire source buffer first.
> This read may exceed the destination size limit.
> This is both inefficient and can lead to linear read
> overflows if a source string is not NUL-terminated [1].
> In an effort to remov
On Mon, May 22, 2023 at 03:51:49PM +, Azeem Shaikh wrote:
> strlcpy() reads the entire source buffer first.
> This read may exceed the destination size limit.
> This is both inefficient and can lead to linear read
> overflows if a source string is not NUL-terminated [1].
> In an effort to remov
On Mon, May 22, 2023 at 03:51:24PM +, Azeem Shaikh wrote:
> strlcpy() reads the entire source buffer first.
> This read may exceed the destination size limit.
> This is both inefficient and can lead to linear read
> overflows if a source string is not NUL-terminated [1].
> In an effort to remov
On Mon, May 22, 2023 at 03:50:32PM +, Azeem Shaikh wrote:
> strlcpy() reads the entire source buffer first.
> This read may exceed the destination size limit.
> This is both inefficient and can lead to linear read
> overflows if a source string is not NUL-terminated [1].
> In an effort to remov
The internal_hpd flag was introduced to handle external DP HPD derived
from GPIO pinmuxed into DP controller. HPD plug/unplug interrupts cannot
be enabled until internal_hpd flag is set to true.
At both bootup and resume time, the DP driver will enable external DP
plugin interrupts and handle plugi
We are not using the STAGING inside drm and the uAPI needs to be
in the acceptable form before we get merged upstream.
Link: https://lore.kernel.org/all/2023051029-overspend-sherry-1b85@gregkh/
Cc: Dave Airlie
Cc: Daniel Vetter
Cc: Oded Gabbay
Cc: Francois Dugast
Cc: Luis Strano
Cc: Matthew B
From: Kees Cook
[ Upstream commit 25feda6fbd0cfefcb69308fb20d4d4815a107c5e ]
More arrays (and arguments) for dcpd were set to 16, when it looks like
DP_RECEIVER_CAP_SIZE (15) should be used. Fix the remaining cases, seen
with GCC 13:
../drivers/gpu/drm/nouveau/nvif/outp.c: In function 'nvif_out
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Changes in v3:
-- fixed kernel test rebot report that "__iomem *off" is declared but not
used at dpu_hw_dsc_config_1_2()
-- unrolling thresh loops
Changes in v4:
-- delete DPU_DSC_HW_REV_1_1
-- delete
From: Abhinav Kumar
Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
feature flag information. Each display compression engine (DCE) contains
dual DSC encoders so both share same base address but with its own
different sub block address.
changes in v4:
-- delete DPU_DSC_H
Currently DSC flushing happens during interface configuration at
dpu_hw_ctl_intf_cfg_v1(). Separate DSC flush away from
dpu_hw_ctl_intf_cfg_v1() by adding dpu_hw_ctl_update_pending_flush_dsc_v1()
to handle both per-DSC engine and DSC flush bits at same time to make it
consistent with the location o
DSC flush bit is the bit 22 of CTL flush register. BIT(22) is expected
to be written to CTL flush register to indicates that DSC is ready for
flush. However 0x22 (BIT(1) and BIT(5)) was written mistakenly at current
implementation. Fix this problem by writing BIT(22) to CTL flush register
for DSC t
There are two tiers of pending flush control, main controller and
individual hardware block. Currently only the main controller of
flush mask is reset to 0 but leave out some individual pending flush
mask of particular hardware block keep previous value at
clear_pending_flush(). Reset all individua
This series adds the DPU side changes to support DSC 1.2 encoder. This
was validated with both DSI DSC 1.2 panel and DP DSC 1.2 monitor.
The DSI and DP parts will be pushed later on top of this change.
This seriel is rebase on [1], [2] and catalog fixes from rev-4 of [3].
[1]: https://patchwork.fr
Unset DSC_ACTIVE bit at dpu_hw_ctl_reset_intf_cfg_v1(),
dpu_encoder_unprep_dsc() and dpu_encoder_dsc_pipe_clr() functions
to tear down DSC data path if DSC data path was setup previous.
Changes in V10:
-- pass ctl directly instead of dpu_enc to dsc_pipe_cfg()
-- move both dpu_encoder_unprep_dsc()
DPU < 7.0.0 has DPU_PINGPONG_DSC feature bit set to indicate it requires
both dpu_hw_pp_setup_dsc() and dpu_hw_pp_dsc_{enable,disable}() to be
executed to complete DSC configuration if DSC hardware block is present.
Hence test DPU_PINGPONG_DSC feature bit and assign DSC related functions
to the ops
Disabling the crossbar mux between DSC and PINGPONG currently
requires a bogus enum dpu_pingpong value to be passed when calling
dsc_bind_pingpong_blk() with enable=false, even though the register
value written is independent of the current PINGPONG block. Replace
that `bool enable` parameter with
DPU < 7.0.0 requires the PINGPONG block to be involved during
DSC setting up. Since DPU >= 7.0.0, enabling and starting the DSC
encoder engine was moved to INTF with the help of the flush mechanism.
Add a DPU_PINGPONG_DSC feature bit to restrict the availability of
dpu_hw_pp_setup_dsc() and dpu_hw_
From: Abhinav Kumar
Some platforms have DSC blocks which have not been declared in the catalog.
Complete DSC 1.1 support for all platforms by adding the missing blocks to
MSM8998 and SC8180X.
Changes in v9:
-- add MSM8998 and SC8180x to commit title
Changes in v10:
-- fix grammar at commit text
The fbdev framebuffer is in system memory. Store the address in
the field 'screen_buffer'. Fixes the following sparse warning.
../drivers/gpu/drm/msm/msm_fbdev.c:124:26: warning: incorrect type in
assignment (different address spaces)
../drivers/gpu/drm/msm/msm_fbdev.c:124:26:expected char [n
My understanding is that DRM_MODE_PAGE_FLIP_ASYNC is currently only
supported for the legacy DRM_IOCTL_MODE_PAGE_FLIP ioctl. Comments in
related code suggest that while ASYNC is not currently supported for
DRM_IOCTL_MODE_ATOMIC, there could be support for it at some point in
the future.
Is anyone
Am 21.05.23 um 20:49 schrieb Chia-I Wu:
On Thu, May 18, 2023 at 1:12 PM Alex Deucher wrote:
On Wed, May 17, 2023 at 5:27 PM Chia-I Wu wrote:
On Tue, May 9, 2023 at 11:33 AM Chia-I Wu wrote:
Extend the address and size validations to AMDGPU_VA_OP_UNMAP and
AMDGPU_VA_OP_CLEAR by moving the va
The fbdev framebuffer is I/O memory, so clear it with fb_memset_io().
Fixes the following sparse warning:
../drivers/gpu/drm/gma500/fbdev.c:234:20: warning: incorrect type in argument 1
(different address spaces)
../drivers/gpu/drm/gma500/fbdev.c:234:20:expected void *s
../drivers/gpu/drm/gma
Hi
Am 22.05.23 um 15:20 schrieb Dmitry Baryshkov:
On Mon, 22 May 2023 at 15:22, Thomas Zimmermann wrote:
Implement dedicated fbdev helpers for framebuffer I/O instead
of using DRM's helpers. Fbdev-generic was the only caller of the
DRM helpers, so remove them from the helper module.
v2:
On Mon, May 22, 2023 at 11:25:54AM -0700, Florian Fainelli wrote:
> On 5/22/23 11:17, Conor Dooley wrote:
> > On Fri, May 19, 2023 at 02:19:39PM -0700, Justin Chen wrote:
> > > The ASP 2.0 Ethernet controller uses a brcm unimac.
> > >
> > > Signed-off-by: Florian Fainelli
> > > Signed-off-by:
On 5/20/2023 5:32 PM, Dmitry Baryshkov wrote:
On 20/05/2023 00:17, Jessica Zhang wrote:
Currently, slice_count is being used to calculate word count and
pkt_per_line. In downstream, these values are calculated using slice per
packet, which is not the same as slice_count.
I'd say the referen
On Fri, May 19, 2023 at 02:19:40PM -0700, Justin Chen wrote:
> From: Florian Fainelli
>
> Add a binding document for the Broadcom ASP 2.0 Ethernet controller.
>
> Signed-off-by: Florian Fainelli
> Signed-off-by: Justin Chen
> ---
Same deal here, usual mailer is refusing to reply cos of:
Proble
On Fri, May 19, 2023 at 02:19:39PM -0700, Justin Chen wrote:
> The ASP 2.0 Ethernet controller uses a brcm unimac.
>
> Signed-off-by: Florian Fainelli
> Signed-off-by: Justin Chen
> ---
> Documentation/devicetree/bindings/net/brcm,unimac-mdio.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> d
On 5/20/2023 1:07 AM, Marijn Suijten wrote:
On 2023-05-19 14:17:26, Jessica Zhang wrote:
Currently, when compression is enabled, hdisplay is reduced via integer
division. This causes issues for modes where the original hdisplay is
not a multiple of 3.
To fix this, use DIV_ROUND_UP to divide
On 5/19/2023 2:34 PM, Marijn Suijten wrote:
On 2023-05-19 14:17:28, Jessica Zhang wrote:
Add DATA_COMPRESS feature flag to DPU INTF block.
In DPU 7.x and later, DSC/DCE enablement registers have been moved from
PINGPONG to INTF.
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
Hi Michal,
On 5/22/23 17:36, Michal Koutný wrote:
On Thu, Apr 27, 2023 at 11:08:41AM +0800, Zheng Wang wrote:
static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id
*ent)
@@ -1529,10 +1530,10 @@ static int imsttfb_probe(struct pci_dev *pdev, const
struct pci_device_id *e
tree: git://anongit.freedesktop.org/drm-intel for-linux-next
head: 937859485aefed1d9df72feb6ea74a84ff5cfa46
commit: 937859485aefed1d9df72feb6ea74a84ff5cfa46 [1/1] drm/i915: Support Async
Flip on Linear buffers
config: x86_64-randconfig-a012-20230522
(https://download.01.org/0day-ci/archive
On 5/22/2023 2:09 AM, Neil Armstrong wrote:
On 16/05/2023 22:20, Jessica Zhang wrote:
Add support for the 1080x2340 Visionox R66451 AMOLED DSI panel that
comes with the Qualcomm HDK8350 display expansion pack.
The panel enables display compression (DSC v1.2) by default.
Signed-off-by: Jessi
On Mon, May 22, 2023 at 05:04:09PM +0100, Russell King (Oracle) wrote:
> On Mon, May 22, 2023 at 03:53:50PM +, Azeem Shaikh wrote:
> > strlcpy() reads the entire source buffer first.
> > This read may exceed the destination size limit.
> > This is both inefficient and can lead to linear read
>
On 22.05.2023 03:23, Dmitry Baryshkov wrote:
> On 22/05/2023 00:23, Marijn Suijten wrote:
>> The SOFEF03-M Display-IC paired with an unknown panel in the Sony Xperia
>> 5 II always uses Display Stream Compression 1.1 and features a 60hz and
>> 120hz refresh-rate mode.
>>
>> Co-developed-by: Konr
On 22.05.2023 03:19, Dmitry Baryshkov wrote:
> On 22/05/2023 00:23, Marijn Suijten wrote:
>> This SOFEF01-M Display-IC driver supports two modes with different
>> compatibles to differentiate between slightly different physical sizes
>> (panels) found on the Xperia 5 (6.1") and 10 II (6.0").
>>
On Mon, May 22, 2023 at 03:53:50PM +, Azeem Shaikh wrote:
> strlcpy() reads the entire source buffer first.
> This read may exceed the destination size limit.
> This is both inefficient and can lead to linear read
> overflows if a source string is not NUL-terminated [1].
> In an effort to remov
Hello.
On Thu, Apr 27, 2023 at 11:08:41AM +0800, Zheng Wang wrote:
> static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id
> *ent)
> @@ -1529,10 +1530,10 @@ static int imsttfb_probe(struct pci_dev *pdev, const
> struct pci_device_id *ent)
> if (!par->cmap_regs)
>
https://bugzilla.kernel.org/show_bug.cgi?id=217432
--- Comment #6 from Jonny Mako (jhnmlkv...@gmail.com) ---
This is now fixed in 6.3.3-arch1-1 #1 SMP PREEMPT_DYNAMIC Sun, 21 May 2023
16:15:22 + x86_64 GNU/Linux. Thanks!
--
You may reply to this email to add a comment.
You are receiving thi
> > > To comply with the design that buffer objects shall have immutable
> > > cache setting through out their life cycle, {set, get}_caching ioctl's
> > > are no longer supported from MTL onward. With that change caching
> > > policy can only be set at object creation time. The current code
> > >
On 2023-05-22 04:52:56, Andi Shyti wrote:
> Hi,
>
> On Thu, May 18, 2023 at 10:11:03PM -0700, fei.y...@intel.com wrote:
> > From: Fei Yang
> >
> > To comply with the design that buffer objects shall have immutable
> > cache setting through out their life cycle, {set, get}_caching ioctl's
> > are
Applied. Thanks!
Alex
On Mon, May 22, 2023 at 8:30 AM Tom Rix wrote:
>
> gcc with W=1 reports
> drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c:2138:13: error: variable
> ‘num_xcc’ set but not used [-Werror=unused-but-set-variable]
> 2138 | int num_xcc;
> | ^~~
>
> This
Applied the series. Thanks!
Alex
On Mon, May 22, 2023 at 7:51 AM Arnd Bergmann wrote:
>
> From: Arnd Bergmann
>
> Two newly introduced functions are in the global namespace but have no
> prototypes
> or callers outside of amdgpu_acpi.c, another function is static but only has
> a caller insid
Applied. Thanks!
On Mon, May 22, 2023 at 3:30 AM Harshit Mogalapalli
wrote:
>
> Smatch warns:
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c:579:
> unsigned 'xcc_id' is never less than zero.
>
> gfx_v9_4_3_ih_to_xcc_inst() returns negative numbers as well.
> Fix this by changing type of
Applied. Thanks!
On Mon, May 22, 2023 at 5:02 AM Colin Ian King wrote:
>
> There are a couple of spelling mistakes, one in a dev_info message
> and the other in a dev_debug message. Fix them.
>
> Signed-off-by: Colin Ian King
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
> drivers/gp
On Mon, 22 May 2023, Sui Jingfeng <15330273...@189.cn> wrote:
> Hi,
>
> On 2023/5/22 20:13, Jani Nikula wrote:
>> On Mon, 22 May 2023, Sui Jingfeng <15330273...@189.cn> wrote:
>>> Hi,
>>>
>>> On 2023/5/22 19:29, Jani Nikula wrote:
On Thu, 18 May 2023, Sui Jingfeng <15330273...@189.cn> wrote:
>
On 22/05/2023 17:36, Neil Armstrong wrote:
Hi,
On 22/05/2023 02:42, Dmitry Baryshkov wrote:
There is no point in having a single enum (and a single array) for both
DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
enum and two IRQ address arrays.
Signed-off-by: Dmitry Barys
Hi Daniel et al,
According to [1], there is a conversion guide for atomic.
Unfortunately the document does not have a link to this guide.
Where can I find it?
Thanks in advance!
[1]
https://elixir.bootlin.com/linux/latest/source/Documentation/gpu/todo.rst#L52
Gr{oetje,eeting}s,
On Mon, May 22, 2023 at 12:59:27PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> In preparation for exposing via sysfs add helpers for managing rps
> thresholds.
>
> v2:
> * Force sw and hw re-programming on threshold change.
it makes sense now.
Reviewed-by: Rodrigo Vivi
>
> Sig
On Mon, May 22, 2023 at 12:59:26PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Record the default values as preparation for exposing the sysfs controls.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/gt/intel_gt_types
On Mon, May 22, 2023 at 12:59:25PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Since 36d516be867c ("drm/i915/gt: Switch to manual evaluation of RPS")
> thresholds are invariant so lets move their setting to init time.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Rodrigo Vivi
Reviewed-b
On 2023-05-22 11:05:38, Neil Armstrong wrote:
> On 21/05/2023 12:30, Marijn Suijten wrote:
> > On 2023-05-16 13:20:30, Jessica Zhang wrote:
> >> Document the 1080x2340 Visionox R66451 AMOLED DSI panel bindings
> >>
> >> Signed-off-by: Jessica Zhang
> >> ---
> >> .../bindings/display/panel/vision
On 22/05/2023 02:42, Dmitry Baryshkov wrote:
While reworking interrupts masks, it was easier to keep old
MDP_INTFn_7xxx_INTR and MDP_INTFn_7xxx_TEAR_INTR symbols. Now it is time
to drop them and use unified symbol names.
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/catalog/dp
On 22/05/2023 02:42, Dmitry Baryshkov wrote:
Now as the list of the interrupts is constructed from the catalog
data, drop the mdss_irqs field from catalog.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h| 8
.../gpu/drm/msm/disp/dpu1/catalog/
Hi,
On 22/05/2023 02:42, Dmitry Baryshkov wrote:
There is no point in having a single enum (and a single array) for both
DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
enum and two IRQ address arrays.
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_hw
On 22/05/2023 02:42, Dmitry Baryshkov wrote:
Inline __intr_offset(), there is no point in having a separate oneline
function for setting base block address.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 8 +---
1 file changed, 1 insertion(+), 7 d
On 22/05/2023 02:42, Dmitry Baryshkov wrote:
Using BIT(DPU_INTF_TE) in INTF_SC7180_MASK (and by extension in
INTF_SC7280_MASK) results in this bit (and corrsponding operations)
being enabled for all interfaces, even the ones which do not have TE
block. Move this bit setting to INTF_DSI_TE(), so t
Hi Arseniy,
avkras...@sberdevices.ru wrote on Mon, 15 May 2023 12:49:50 +0300:
> Hello @Miquel!
>
> Sorry, but who could review this patch? :) IIUC this logic is very hw
> specific and we need
> someone who knows it well? I tested this patch on our devices (with already
> known Meson NAND
> co
On 19/05/2023 20:40, Dmitry Baryshkov wrote:
On some devices the +5V Power pin of the HDMI connector and/or the ESD
protection logic is powered on by a separate regulator. Instead of
declaring this regulator as always-on, make hdmi-connector support the
additional hdmi-pwr supply.
Signed-off-by:
Some 64-bit machines require us to call the STI ROM in 64-bit mode, e.g.
with the VisFXe graphic card.
This patch allows drivers to use such 64-bit calling conventions.
Signed-off-by: Helge Deller
---
arch/parisc/include/asm/pdc.h | 4 ++--
arch/parisc/kernel/firmware.c | 21 ++-
Fix the STI console to be able to execute either the 64-bit STI ROM code
or the 32-bit STI ROM code.
This is necessary on 64-bit only machines (e.g. C8000 workstation) which
otherwise won't show the STI text console with HP graphic cards like
Visualize-FX5/FX10/FXe.
Note that when calling 32-bit
Two patches to fix the STI text console on parisc machines.
Helge Deller (2):
sticon/parisc: Allow 64-bit STI calls in PDC firmware abstration
sticon/parisc: Fix STI console on 64-bit only machines
arch/parisc/include/asm/pdc.h | 4 +-
arch/parisc/kernel/firmware.c | 21 +++--
drivers/vid
On 22/05/2023 12:10, Neil Armstrong wrote:
On 18/05/2023 02:19, Dmitry Baryshkov wrote:
On 16/05/2023 23:20, Jessica Zhang wrote:
Add support for the 1080x2340 Visionox R66451 AMOLED DSI panel that
comes with the Qualcomm HDK8350 display expansion pack.
The panel enables display compression (D
On 22/05/2023 14:53, Fabio Estevam wrote:
Hi Neil,
On Sun, May 14, 2023 at 9:29 AM Krzysztof Kozlowski
wrote:
On 14/05/2023 13:46, Fabio Estevam wrote:
From: Fabio Estevam
The Samsung DSIM IP block allows the inversion of the clock and
data lanes.
Add an optional property called 'lane-pol
Hi,
On Sun, 14 May 2023 08:46:24 -0300, Fabio Estevam wrote:
> The Samsung DSIM IP block allows the inversion of the clock and
> data lanes.
>
> Add an optional property called 'lane-polarities' that describes the
> polarities of the MIPI DSI clock and data lanes.
>
> This property is useful for
On 17.05.23 00:22, Fabio Estevam wrote:
> On Thu, May 4, 2023 at 6:12 AM Alexander Stein
> wrote:
>>
>> Am Mittwoch, 3. Mai 2023, 18:33:07 CEST schrieb Frieder Schrempf:
>>> From: Frieder Schrempf
>>>
>>> The datasheet describes the following initialization flow including
>>> minimum delay times
On 5/22/23 16:02, Emil Velikov wrote:
> Hi Dmitry,
>
> Saw v3 fly by, so I had a quick look. Original RB still stands,
> although I noticed a couple of non-blocking nitpicks.
>
> On Sun, 21 May 2023 at 22:00, Dmitry Osipenko
> wrote:
>
>> -static int drm_gem_shmem_get_pages_locked(struct drm_ge
On Mon, 22 May 2023 at 15:22, Thomas Zimmermann wrote:
>
> Implement dedicated fbdev helpers for framebuffer I/O instead
> of using DRM's helpers. Fbdev-generic was the only caller of the
> DRM helpers, so remove them from the helper module.
>
> v2:
> * use FB_SYS_HELPERS_DEFERRED option
>
Hi,
> > There is also a direct and hard coded use in cirrus.c which according to
> > the comment is only necessary during resume. Let's just skip this as
> > for example s390 which doesn't have I/O port support also doesen't
> > support suspend/resume.
>
> I think we should consider making cir
Hi,
On 2023/5/22 18:25, WANG Xuerui wrote:
On 2023/5/22 18:17, Sui Jingfeng wrote:
Hi,
On 2023/5/22 18:05, WANG Xuerui wrote:
On 2023/5/22 17:49, Sui Jingfeng wrote:
Hi,
On 2023/5/22 17:28, WANG Xuerui wrote:
On 2023/5/22 17:25, Sui Jingfeng wrote:
Hi,
On 2023/5/21 20:21, WANG Xuerui wro
On Mon, May 22, 2023, at 14:38, Thomas Zimmermann wrote:
> Am 22.05.23 um 12:50 schrieb Niklas Schnelle:
>> There is also a direct and hard coded use in cirrus.c which according to
>> the comment is only necessary during resume. Let's just skip this as
>> for example s390 which doesn't have I/O p
Hi Dmitry,
Saw v3 fly by, so I had a quick look. Original RB still stands,
although I noticed a couple of non-blocking nitpicks.
On Sun, 21 May 2023 at 22:00, Dmitry Osipenko
wrote:
> -static int drm_gem_shmem_get_pages_locked(struct drm_gem_shmem_object *shmem)
> +static int drm_gem_shmem_get_
On Mon, 22 May 2023 at 11:47, Marijn Suijten
wrote:
>
> On 2023-05-22 10:48:01, Dan Carpenter wrote:
> > The "vsync_hz" variable is used to store negative error codes so it
> > needs to be signed for the error checking to work correctly.
>
> Nicely spotted, but it it looks like we have more to fix
gcc with W=1 reports
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c:760:23: error:
‘mmhub_v1_8_mmea_cgtt_clk_cntl_reg’ defined but not used
[-Werror=unused-const-variable=]
760 | static const uint32_t mmhub_v1_8_mmea_cgtt_clk_cntl_reg[] = {
| ^~
On Sat, May 20, 2023 at 02:07:51AM +0300, Dmitry Baryshkov wrote:
> On 20/05/2023 00:16, Rodrigo Vivi wrote:
> > On Fri, May 19, 2023 at 07:55:47PM +0300, Dmitry Baryshkov wrote:
> > > On 19/04/2023 18:43, Mark Yacoub wrote:
> > > > Hi all,
> > > > This is v10 of the HDCP patches. The patches are a
On Mon, 22 May 2023 at 12:04, Neil Armstrong wrote:
>
> On 22/05/2023 03:16, Dmitry Baryshkov wrote:
> > On 22/05/2023 00:23, Marijn Suijten wrote:
> >> Sony provides an unlabeled LGD + Atmel maXTouch assembly in its Xperia
> >> XZ3 (tama akatsuki) phone, with custom DCS commands to match.
> >>
>
On Mon, 22 May 2023 at 12:08, Neil Armstrong wrote:
>
> On 22/05/2023 03:23, Dmitry Baryshkov wrote:
> > On 22/05/2023 00:23, Marijn Suijten wrote:
> >> The SOFEF03-M Display-IC paired with an unknown panel in the Sony Xperia
> >> 5 II always uses Display Stream Compression 1.1 and features a 60hz
Hi Neil,
On Sun, May 14, 2023 at 9:29 AM Krzysztof Kozlowski
wrote:
>
> On 14/05/2023 13:46, Fabio Estevam wrote:
> > From: Fabio Estevam
> >
> > The Samsung DSIM IP block allows the inversion of the clock and
> > data lanes.
> >
> > Add an optional property called 'lane-polarities' that describ
Hi,
On 2023/5/22 20:13, Jani Nikula wrote:
On Mon, 22 May 2023, Sui Jingfeng <15330273...@189.cn> wrote:
Hi,
On 2023/5/22 19:29, Jani Nikula wrote:
On Thu, 18 May 2023, Sui Jingfeng <15330273...@189.cn> wrote:
On 2023/5/17 18:59, David Laight wrote:
From: 15330273...@189.cn
Sent: 16 May 20
Hi
Am 22.05.23 um 12:50 schrieb Niklas Schnelle:
In a future patch HAS_IOPORT=n will result in inb()/outb() and friends
not being declared. We thus need to add HAS_IOPORT as dependency for
those drivers using them. In the bochs driver there is optional MMIO
support detected at runtime, warn if t
gcc with W=1 reports
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c:2138:13: error: variable
‘num_xcc’ set but not used [-Werror=unused-but-set-variable]
2138 | int num_xcc;
| ^~~
This variable is not used so remove it.
Signed-off-by: Tom Rix
---
drivers/gpu/drm/amd/am
Il 22/05/23 12:00, CK Hu (胡俊光) ha scritto:
Hi, Angelo:
On Thu, 2023-05-18 at 12:48 +0200, AngeloGioacchino Del Regno wrote:
External email : Please do not click links or open attachments until
you have verified the sender or the content.
Move the write to DISP_GAMMA_CFG to enable the Gamma LU
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