On 01/06/2023 00:44, Fabio Estevam wrote:
> From: Fabio Estevam
>
> Use port-base reference for port@1.
>
> This fixes the following schema warning:
>
> imx8mp-dhcom-pdk3.dtb: dsi@32e6: ports:port@1:endpoint: Unevaluated
> properties are not allowed ('data-lanes' was unexpected)
> From sch
Hi Imre,
Raised the ticket and was able to capture the logs for you.
https://gitlab.freedesktop.org/drm/intel/-/issues/8559
Thanks
Rudi
On Wed, 31 May 2023 at 18:47, Imre Deak wrote:
>
> On Tue, May 30, 2023 at 01:49:07PM +, Rudi Heitbaum wrote:
> Hi Rudi,
>
> Could you open a ticket at
>
Le mar. 30 mai 2023 à 09:38, Neil Armstrong
a écrit :
>
> This updates the panel timings to achieve a clean 60Hz refresh rate.
>
> Signed-off-by: Neil Armstrong
> ---
> drivers/gpu/drm/panel/panel-khadas-ts050.c | 16
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --
Le mar. 30 mai 2023 à 09:38, Neil Armstrong
a écrit :
>
> If the case the HDMI controller fails to bind, we try to unbind
> all components before calling drm_dev_put() which makes drm_bridge_detach()
> crash because unbinding the HDMI controller frees the bridge memory.
>
> The solution is the unb
Le mar. 30 mai 2023 à 09:38, Neil Armstrong
a écrit :
>
> The Amlogic G12A/G12B/SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver
> (ver 1.21a), with a custom glue managing the IP resets, clock and data
> inputs similar to the DW-HDMI Glue on other Amlogic SoCs.
>
> This adds support for the Glue
Le mar. 30 mai 2023 à 09:38, Neil Armstrong
a écrit :
>
> This adds supports for the ENCL encoder connected to a MIPI-DSI transceiver
> on the
> Amlogic AXG, G12A, G12B & SM1 SoCs.
>
> Signed-off-by: Neil Armstrong
> Signed-off-by: Neil Armstrong
> ---
> drivers/gpu/drm/meson/meson_registers.h
Le mar. 30 mai 2023 à 09:38, Neil Armstrong
a écrit :
>
> Only DW-HDMI currently needs components since it reuses
> the drm-meson driver context to access HHI registers (sic).
>
> Once this is solved, we can get rid on components.
>
> Until now, limit the components matching to the dw-hdmi compati
Le mar. 30 mai 2023 à 09:38, Neil Armstrong
a écrit :
>
> This adds an encoder bridge designed to drive a MIPI-DSI display
> by using the ENCL encoder through the internal MIPI DSI transceiver
> connected to the output of the ENCL pixel encoder.
>
> Signed-off-by: Neil Armstrong
> Reviewed-by: Ja
devm_kzalloc() can fail and return NULL pointer. Check its return status.
Identified with Coccinelle (kmerr.cocci script).
Fixes: 484e72d3146b ("drm/stm: ltdc: add support of ycbcr pixel formats")
Signed-off-by: Claudiu Beznea
---
Hi,
This has been addressed using kmerr.cocci script proposed fo
Hi,
On Wed, 31 May 2023 19:44:07 -0300, Fabio Estevam wrote:
> Use port-base reference for port@1.
>
> This fixes the following schema warning:
>
> imx8mp-dhcom-pdk3.dtb: dsi@32e6: ports:port@1:endpoint: Unevaluated
> properties are not allowed ('data-lanes' was unexpected)
> From schema:
Hi Inki,
> > > > > > > If it is async, runqueue_node is freed in g2d_runqueue_worker on
> > another
> > > > > > > worker thread. So in extreme cases, if g2d_runqueue_worker runs
> > first, and
> > > > > > > then executes the following if statement, there will be use-
> > after-free.
> > > > > > >
On 31.05.23 20:14, Borislav Petkov wrote:
On Fri, May 19, 2023 at 08:36:34PM +0200, Janusz Krzysztofik wrote:
diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h
index 15ae4d6ba4768..56466afd04307 100644
--- a/arch/x86/include/asm/pgtable.h
+++ b/arch/x86/include/asm/pgt
On Wed, May 31, 2023 at 07:22:49AM -0700, Doug Anderson wrote:
> Hi,
>
> On Wed, May 31, 2023 at 1:00 AM Johan Hovold wrote:
> >
> > A recent commit started taking the GMU lock in the GPU destroy path,
> > which on GPU initialisation failure is called before the GMU and its
> > lock have been ini
Hi
Am 01.06.23 um 02:48 schrieb Jammy Huang:
If we switch display and update cursor together, it could lead to
modeset failed because of concurrent access to IO registers.
Add lock protection in DP's edid access to avoid this problem.
Merged into drm-misc-fixes. Thanks for the patch.
Best re
On 01/06/2023 12:21, neil.armstr...@linaro.org wrote:
From: Dmitry Baryshkov
Add support for the ON Semiconductor NB7VPQ904M Type-C USB SuperSpeed
and DisplayPort ALT Mode Linear Redriver chip found on some devices
with a Type-C port.
The redriver compensates ultra High-Speeed DisplayPort and
On Tue, May 30, 2023 at 05:12:24PM +0200, Thomas Zimmermann wrote:
> Use the regular fbdev helpers for framebuffer I/O instead of DRM's
> helpers. Tegra does not use damage handling, so DRM's fbdev helpers
> are mere wrappers around the fbdev code.
>
> By using fbdev helpers directly within each D
insertions(+), 2 deletions(-)
---
base-commit: d4cee89031c80066ec461bb77b5e13a4f37d5fd2
change-id: 20230601-topic-sm8550-upstream-dp-b713ba275d7c
Best regards,
--
Neil Armstrong
The SM8550 & SM8350 SoC shares the same DP TX IP version, use the
SM8350 compatible as fallback for SM8550.
Signed-off-by: Neil Armstrong
---
Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/dis
Add the Display Port controller subnode to the MDSS node.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 89 +++-
1 file changed, 87 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi
b/arch/arm64/boot/dts/q
On Mon, May 15, 2023 at 03:04:43PM +0200, Michel Dänzer wrote:
On 5/11/23 21:39, Sasha Levin wrote:
From: Wesley Chalmers
[ Upstream commit 474f01015ffdb74e01c2eb3584a2822c64e7b2be ]
[WHY]
Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a
pipe commit can cause underflow.
On 01/06/2023 11:37, Dmitry Baryshkov wrote:
On 01/06/2023 12:21, neil.armstr...@linaro.org wrote:
From: Dmitry Baryshkov
Add support for the ON Semiconductor NB7VPQ904M Type-C USB SuperSpeed
and DisplayPort ALT Mode Linear Redriver chip found on some devices
with a Type-C port.
The redriver
On 1.06.2023 11:52, Neil Armstrong wrote:
> Add the Display Port controller subnode to the MDSS node.
>
> Signed-off-by: Neil Armstrong
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 89
> +++-
> 1 file changed, 87 insertions(+), 2 deletions(-)
>
> diff --git
On 01/06/2023 11:52, Neil Armstrong wrote:
> The SM8550 & SM8350 SoC shares the same DP TX IP version, use the
> SM8350 compatible as fallback for SM8550.
>
> Signed-off-by: Neil Armstrong
> ---
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
Hi,
On 2023/6/1 02:07, Lucas Stach wrote:
Am Mittwoch, dem 31.05.2023 um 00:06 +0800 schrieb Sui Jingfeng:
Because it is also platform-dependent, there are environments where don't
have CLK subsystem support, for example, discreted PCI gpu. So don't rage
quit if there is no CLK subsystem.
For
v2:
- Added review tags
- s/lov_svs/low_svs/
- Applied fixes suggested from Konrad
- Link to v1:
https://lore.kernel.org/r/20230601-topic-sm8550-upstream-dp-v1-0-29efe2689...@linaro.org
---
Neil Armstrong (3):
dt-bindings: display: msm: dp-controller: document SM8550 compatible
arm64
The SM8550 & SM8350 SoC shares the same DP TX IP version, use the
SM8350 compatible as fallback for SM8550.
Acked-by: Krzysztof Kozlowski
Signed-off-by: Neil Armstrong
---
Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Docume
"low" was written "lov", fix this.
Fixes: 99d33ee61cb0 ("arm64: dts: qcom: sm8550: Add missing RPMhPD OPP levels")
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi
Add the Display Port controller subnode to the MDSS node.
Reviewed-by: Konrad Dybcio
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 89 +++-
1 file changed, 87 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.d
On 1.06.2023 12:09, Neil Armstrong wrote:
> "low" was written "lov", fix this.
I "lov" making typos.. Thanks for spotting this!
Reviewed-by: Konrad Dybcio
Konrad
>
> Fixes: 99d33ee61cb0 ("arm64: dts: qcom: sm8550: Add missing RPMhPD OPP
> levels")
> Signed-off-by: Neil Armstrong
> ---
> a
Hi,
On 2023/6/1 01:53, Lucas Stach wrote:
Am Donnerstag, dem 01.06.2023 um 01:29 +0800 schrieb Sui Jingfeng:
Hi,
On 2023/6/1 00:33, Lucas Stach wrote:
Hi Sui Jingfeng,
Am Mittwoch, dem 31.05.2023 um 00:06 +0800 schrieb Sui Jingfeng:
cached system RAM is coherent on loongson CPUs, and the GP
On 6/1/23 08:24, Ying Liu wrote:
On Thu, Jun 1, 2023 at 2:45 AM Lucas Stach wrote:
Force a modeset if the new FB has a different format than the
currently active one. While it might be possible to change between
compatible formats without a full modeset as the format control is
also supposed t
Am 25.05.23 um 17:02 schrieb Thomas Hellström:
Clearing the buffer object bulk move is closely tied to individualizing
the resv, since that is when we effectively detach the bo from a vm.
Clearing the bulk move also requires the bo resv, which we have readily
locked at individualizing time witho
Hi Dave and Daniel,
here's the weekly PR for drm-misc-next. There's support for some new
panels; some improvements to bridge drivers. The code around show_fdinfo
can now be shared among DRM drivers. Fbdev emulation got improved file
I/O code. Plus the usual fixes.
Best regards
Thomas
drm-misc-ne
Hi Laurent,
Thanks for the feedback.
> Subject: Re: [PATCH v9 RESEND 4/5] drm: Add RZ/G2L DU Support
>
> Hi Biju,
>
> Thank you for the patch.
>
> This is a partial review, because the driver is big, and because some
> changes in v10 will (hopefully) simplify the code and make review
> easier.
Changes in v5:
- Removed incorrect comment on default LUT size and bits
- Removed useless check for num_lut_banks
- Added comment about CMDQ implementation on patch 5
- Evaluated passing lut size/bits from AAL, idea discarded as
the implementation would be rather tricky while bringing no
Invert the check for state->gamma_lut and move it at the beginning
of the function to reduce indentation: this prepares the code for
keeping readability on later additions.
This commit brings no functional changes.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Jason-JH.Lin
---
driver
Newer SoCs support a bigger Gamma LUT table: wire up a callback
to retrieve the correct LUT size for each different Gamma IP.
Co-developed-by: Jason-JH.Lin
Signed-off-by: Jason-JH.Lin
[Angelo: Rewritten commit message/description + porting]
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by
Use drm_color_lut_extract() to avoid open-coding the bits reduction
calculations for each color channel and use a struct drm_color_lut
to temporarily store the information instead of an array of u32.
Also, slightly improve the precision of the HW LUT calculation in the
LUT DIFF case by performing
New SoCs, like MT8195, not only may support bigger lookup tables, but
have got a different register layout to support bigger precision:
support specifying the number of `lut_bits` for each SoC and use it
in mtk_gamma_set_common() to perform the right calculation.
Signed-off-by: AngeloGioacchino De
From: "Jason-JH.Lin"
Adjust the parameters in mtk_drm_gamma_set_common()
- add (struct device *dev) to get lut_diff from gamma's driver data
- remove (bool lut_diff) and use false as default value in the function
Signed-off-by: Jason-JH.Lin
Signed-off-by: AngeloGioacchino Del Regno
---
d
Move the write to DISP_GAMMA_CFG to enable the Gamma LUT to after
programming the actual table to avoid potential visual glitches during
table modification.
Note:
GAMMA should get enabled in between vblanks, but this requires many
efforts in order to make this happen, as that requires migrating al
Newer Gamma IP have got multiple LUT banks: support specifying the
size of the LUT banks and handle bank-switching before programming
the LUT in mtk_gamma_set_common() in preparation for adding support
for MT8195 and newer SoCs.
Suggested-by: Jason-JH.Lin
[Angelo: Refactored original commit]
Sign
Make the code more robust and improve readability by using bitfield
macros instead of open coding bit operations.
While at it, also add a definition for LUT_BITS_DEFAULT.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Jason-JH.Lin
---
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 41
Disable relay mode at the end of LUT programming to make sure that the
processed image goes through.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Jason-JH.Lin
---
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediate
Add support for 12-bit gamma lookup tables and introduce the first
user for it: MT8195.
While at it, also reorder the variables in mtk_gamma_set_common()
and rename `lut_base` to `lut0_base` to improve readability.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Jason-JH.Lin
---
drivers
All of the SoCs that don't have dithering control in the gamma IP
have got a GAMMA_LUT_TYPE bit that tells to the IP if the LUT is
"descending" (bit set) or "rising" (bit cleared): make sure to set
it correctly after programming the LUT.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Jas
On Thu, Jun 1, 2023 at 6:33 PM Marek Vasut wrote:
>
> On 6/1/23 08:24, Ying Liu wrote:
> > On Thu, Jun 1, 2023 at 2:45 AM Lucas Stach wrote:
> >>
> >> Force a modeset if the new FB has a different format than the
> >> currently active one. While it might be possible to change between
> >> compati
Hi Laurent,
Thanks for the feedback.
> Subject: Re: [PATCH v9 RESEND 0/5] Add RZ/{G2L,G2LC} and RZ/V2L Display
> Unit support
>
> On Mon, May 29, 2023 at 02:22:06PM +, Biju Das wrote:
> > HI Laurent,
> >
> > Thanks for the feedback.
> >
> > > Subject: Re: [PATCH v9 RESEND 0/5] Add RZ/{G2L,G2
Commit 5d844091f237 ("drm/scdc-helper: Pimp SCDC debugs") changed the scdc
interface to pick up an i2c adapter from a connector instead. However, in
the case of dw-hdmi, the wrong connector was being used to pass i2c adapter
information, since dw-hdmi's embedded connector structure is only populate
On 26.05.2023 14:41, Andi Shyti wrote:
kernel_context() returns an error pointer. Use pointer-error
conversion functions to evaluate its return value, rather than
checking for a '0' return.
Fixes: eb5c10cbbc2f ("drm/i915: Remove I915_USER_PRIORITY_SHIFT")
Reported-by: Dan Carpenter
Signed-off-b
From: Robert Foss
On Tue, 30 May 2023 21:28:04 +0200, Marek Vasut wrote:
> This chip has one reset GPIO input, document it. The reset GPIO
> is optional as it is sometimes not connected on some hardware.
>
>
Applied, thanks!
[1/2] dt-bindings: display: bridge: tc358762: Document reset-gpios
Hi,
On 2023/6/1 02:07, Lucas Stach wrote:
+static int etnaviv_gpu_clk_get(struct etnaviv_gpu *gpu)
+{
+ struct device *dev = gpu->dev;
+
+ if (gpu->no_clk)
+ return 0;
+
+ gpu->clk_reg = devm_clk_get_optional(dev, "reg");
+ DBG("clk_reg: %p", gpu->clk_reg);
Hi Dave & Daniel,
One fix appeared this morning, related to OA API for
non-power-of-two reports.
Full CI results not in yet, BAT is looking good so please check
before pulling the trigger.
Regards, Joonas
***
drm-intel-fixes-2023-06-01:
- Fix for OA reporting to allow detecting non-power-of-t
Hi,
On Thu, 26 Jan 2023 10:39:42 +0100, Neil Armstrong wrote:
> This updates the panel timings to achieve a clean 60Hz refresh rate.
>
>
Thanks, Applied to https://anongit.freedesktop.org/git/drm/drm-misc.git
(drm-misc-next)
[1/1] drm/panel: khadas-ts050: update timings to achieve 60Hz refres
Hi,
On Tue, 30 May 2023 09:38:01 +0200, Neil Armstrong wrote:
> The Amlogic G12A, G12B & SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver
> (ver 1.21a),
> with a custom glue managing the IP resets, clock and data input similar to
> the DW-HDMI
> glue on the same Amlogic SoCs.
>
> This adds su
Am 26.05.23 um 14:37 schrieb Min Li:
Userspace can race to free the gobj(robj converted from), robj should not
be accessed again after drm_gem_object_put, otherwith it will result in
use-after-free.
Signed-off-by: Min Li
---
drivers/gpu/drm/radeon/radeon_gem.c | 2 +-
1 file changed, 1 inser
Hi Tejas,
> > > @@ -1530,8 +1530,8 @@ static int live_busywait_preempt(void *arg)
> > > struct drm_i915_gem_object *obj;
> > > struct i915_vma *vma;
> > > enum intel_engine_id id;
> > > - int err = -ENOMEM;
> > > u32 *map;
> > > + int err;
>
> We could init
> -Original Message-
> From: Intel-gfx On Behalf Of
> Andrzej Hajda
> Sent: Thursday, June 1, 2023 6:14 PM
> To: Andi Shyti ; Intel GFX g...@lists.freedesktop.org>; DRI Devel
> Cc: Chris Wilson ; sta...@vger.kernel.org; Dan
> Carpenter ; Andi Shyti
> Subject: Re: [Intel-gfx] [PATCH] d
Hi Lu,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-misc/drm-misc-next]
[also build test ERROR on next-20230601]
[cannot apply to linus/master v6.4-rc4]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we
On 2023-05-23 09:46:19, Konrad Dybcio wrote:
> Add basic SM6375 support to the DPU1 driver to enable display output.
Nit: The SM6350 commit doesn't use the word "basic" here: what does it
mean? Is this addition not complete (because it seems so)?
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by:
Hi,
On Thu, May 25, 2023 at 2:32 AM Cong Yang
wrote:
>
> Copare V3:Resend without Conor's acks on patches 2 and 4.
>
> Cong Yang (4):
> dt-bindings: display: panel: Add compatible for Starry himax83102-j02
> drm/panel: Support for Starry-himax83102-j02 TDDI MIPI-DSI panel
> dt-bindings: dis
Hi,
On Thu, May 25, 2023 at 2:32 AM Cong Yang
wrote:
>
> The STARRY himax83102-j02 is a 10.51" WUXGA TFT LCD panel,
> which fits in nicely with the existing panel-boe-tv101wum-nl6
> driver. Hence, we add a new compatible with panel specific config.
>
> Signed-off-by: Cong Yang
> Reviewed-by: Dou
Hi,
On Thu, May 25, 2023 at 2:32 AM Cong Yang
wrote:
>
> The Starry-himax83102-j02 is a 10.51" WUXGA TFT panel. which fits in nicely
> with the existing panel-boe-tv101wum-nl6 driver. From the datasheet[1], MIPI
> needs to keep the LP11 state before the lcm_reset pin is pulled high, so
> increase
Hi,
On Thu, May 25, 2023 at 2:32 AM Cong Yang
wrote:
>
> The STARRY ili9882t is a 10.51" WUXGA TFT LCD panel,
> which fits in nicely with the existing panel-boe-tv101wum-nl6
> driver. Hence, we add a new compatible with panel specific config.
>
> Signed-off-by: Cong Yang
> Reviewed-by: Douglas A
Hi,
On Thu, May 25, 2023 at 2:32 AM Cong Yang
wrote:
>
> The Starry-ili9882 is a 10.51" WUXGA TFT panel. which fits in nicely with
> the existing panel-boe-tv101wum-nl6 driver. From the datasheet,MIPI need
> to keep the LP11 state before the lcm_reset pin is pulled high. So add
> lp11_before_rese
On 2023-05-29 15:28, Christophe JAILLET wrote:
> Use struct_size() instead of hand-writing it. It is less verbose, more
> robust and more informative.
>
> Signed-off-by: Christophe JAILLET
Reviewed-by: Marco Pagani
> ---
> drivers/accel/ivpu/ivpu_job.c | 4 +---
> 1 file changed, 1 insertio
In the case of failed suspend flow or cases where the kernel does not go
into full suspend but goes from suspend_prepare back to resume_complete,
we get called for a pm_complete but without runtime_pm guaranteed.
Thus, ensure we take the runtime_pm when calling intel_pxp_init_hw
from within intel_
On Wed, Apr 12, 2023 at 5:52 PM Christian König
wrote:
>
> Hi guys,
>
> took me some tries to get the Intel CI happy with this patch set.
>
> This is the version rebased on drm-misc-next, for a CI run you actually
> need to rebase the last patch to drm-tip. So I'm planning to merge 1-4
> for this
Hi Lu,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on next-20230601]
[cannot apply to linus/master v6.4-rc4]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch
On 5/30/2023 8:02 AM, Thomas Zimmermann wrote:
Use the regular fbdev helpers for framebuffer I/O instead of DRM's
helpers. Msm does not use damage handling, so DRM's fbdev helpers
are mere wrappers around the fbdev code.
By using fbdev helpers directly within each DRM fbdev emulation,
we can
On 5/21/2023 6:32 PM, Su Hui wrote:
Pointer variables of (void*) type do not require type cast.
Signed-off-by: Su Hui
---
Reviewed-by: Abhinav Kumar
On 5/26/2023 4:51 AM, Dan Carpenter wrote:
Static analysis tools complain about the -EINVAL error code being
stored in an unsigned variable. Let's change this to match
the clk_get_rate() function which is type unsigned long and returns
zero on error.
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845
Add the compatible for the MDP5 found on MSM8226.
Acked-by: Conor Dooley
Signed-off-by: Luca Weiss
---
Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml
b/Documentation/d
Add the compatible for the DSI found on MSM8226.
Acked-by: Conor Dooley
Signed-off-by: Luca Weiss
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.y
Add the config for the v1.0.2 DSI found on MSM8226. We can reuse
existing bits from other revisions that are identical for v1.0.2.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Konrad Dybcio
Signed-off-by: Luca Weiss
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++
drivers/gpu/drm/msm/dsi/dsi_cfg.h
MSM8226 uses a modified PLL lock sequence compared to MSM8974, which is
based on the function dsi_pll_enable_seq_m in the msm-3.10 kernel.
Worth noting that the msm-3.10 downstream kernel also will try other
sequences in case this one doesn't work, but during testing it has shown
that the _m seque
Add the required config for the v1.1 MDP5 found on MSM8226.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Luca Weiss
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 82
1 file changed, 82 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
b/driv
The MSM8226 SoC uses a slightly different 28nm dsi phy. Add a new
compatible for it.
And while we're at it, in the dsi-phy-28nm.yaml move the 8960 compatible
to its correct place so its sorted alphabetically.
Acked-by: Conor Dooley
Signed-off-by: Luca Weiss
---
Documentation/devicetree/binding
This series adds the required configs for MDP5 and DSI blocks that are
needed for MDSS on MSM8226. Finally we can add the new nodes into the
dts.
Tested on apq8026-lg-lenok and msm8926-htc-memul.
Signed-off-by: Luca Weiss
---
Changes in v3:
- Adjust mdss labels to new style (Stephan)
- Link to v
Add the nodes that describe the mdss so that display can work on
MSM8226.
Signed-off-by: Luca Weiss
---
arch/arm/boot/dts/qcom-msm8226.dtsi | 127
1 file changed, 127 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi
b/arch/arm/boot/dts/qcom-ms
On 08.05.2023 19:16, Andrzej Hajda wrote:
On 05.05.2023 22:06, Rodrigo Vivi wrote:
On Thu, May 04, 2023 at 06:27:53PM +0200, Andrzej Hajda wrote:
Hi maintainers of net and i915,
On 25.04.2023 00:05, Andrzej Hajda wrote:
This is revived patchset improving ref_tracker library and converting
i
1. Move output drm connector from each ddp_path array to connector array.
2. Add dynamic select available connector flow in crtc create and enable.
Signed-off-by: Nancy Lin
Signed-off-by: Nathan Lu
Signed-off-by: Jason-JH.Lin
---
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 +
drivers/gpu
To support DSI and eDP as main display connector without modifying
mtk-drm driver, we add the dynamic connector selection mechanism.
Change in v4:
1. Change variable naming of connector routes number from conn_route_num to
num_conn_routes.
2. Chnage he encoder_index function return valuew from in
Add DSI as main display output for mt8188 vdosys0.
Signed-off-by: Nathan Lu
Signed-off-by: Jason-JH.Lin
Reviewed-by: Matthias Brugger
---
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +
On Thu, 1 Jun 2023 19:14:50 +0200 Andrzej Hajda wrote:
> Ping on the series, everything reviewed.
> Eric, Dave, Jakub, could you take patches 1-4 via net tree?
Sure thing, would you mind reposting them separately?
Easier for us to apply and it's been over a month since posting,
a fresh run of buil
Rework dpu_encoder initialization code, simplifying calling sequences
and separating common init parts.
Changes since v2:
- Rebased on top of msm-next-lumag branch
Changes since v1:
- Withdrawn two pathes for a later consideration
- Changed dpu_encoder_phys_init() to return void (Abhinav)
- Added
Move common DPU physical encoder initialization code to the new function
dpu_encoder_phys_init().
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 29 +--
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 3 ++
.../drm
There is no reason to split the dpu_encoder interface into separate
_init() and _setup() phases. Merge them into a single function.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 55 +
drivers/gpu/drm/msm/disp/dpu1/dpu_en
The function dpu_encoder_get_wb() returns controller_id if the
corresponding WB is present in the catalog. We can inline this function
and rely on dpu_rm_get_wb() returning NULL for indices for which the
WB is not present on the device.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
Remove intf_idx and wb_idx fields from struct dpu_encoder_phys and
struct dpu_enc_phys_init_params. Set the hw_intf and hw_wb directly and
use them to get the instance index.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 72 ++
There is little sense to get intf index just to call dpu_rm_get_intf()
on it. Move dpu_rm_get_intf() call to dpu_encoder_get_intf() function.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 20
1 file changed, 8 i
There is no need to assign a result to temp varable just to return it
two lines below. Drop the temporary variable.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff
There is no need to assign a result to temp varable just to return it
after a goto. Drop the temporary variable and goto and return the result
directly.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 10 ++
1 file cha
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 571d71e886a5edc89b4ea6d0fe6f445282938320 Add linux-next specific
files for 20230601
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202305230552.wobyqyya-...@intel.com
https
On 31/05/2023 11:32, Liu Ying wrote:
> NXP i.MX93 mediamix blk-ctrl contains one DISPLAY_MUX register which
> configures parallel display format by using the "PARALLEL_DISP_FORMAT"
> field. Add device tree bindings for the display format configuration.
>
> Signed-off-by: Liu Ying
> ---
> v1->v2:
After recent discussions with Mesa folks, it was requested
that we optimize i915's GET_PARAM for the PXP_STATUS without
changing the UAPI spec.
This patch adds this additional optimizations:
- If any PXP initializatoin flow failed, then ensure that
we catch it so that we can change the ret
On Thu, Jun 01, 2023 at 07:03:18PM +0200, Dario Binacchi wrote:
> Add compatible to panel-simple for Rocktech Displays Limited
> RK043FN48H 4.3" 480x272 LCD-TFT panel.
>
> Signed-off-by: Dario Binacchi
> ---
>
> .../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++
> 1 file ch
On Wed, May 31, 2023 at 10:30:09PM +0200, Konrad Dybcio wrote:
>
>
>
> On 31.05.2023 05:09, Bjorn Andersson wrote:
> > From: Bjorn Andersson
> >
> > Introduce support for the Adreno A690, found in Qualcomm SC8280XP.
> >
> > Tested-by: Steev Klimaszewski
> > Reviewed-by: Konrad Dybcio
> > Si
On Mon, May 29, 2023 at 09:38:59AM +0200, Konrad Dybcio wrote:
>
>
>
> On 28.05.2023 19:07, Manivannan Sadhasivam wrote:
> > On Tue, May 23, 2023 at 09:59:53AM +0200, Konrad Dybcio wrote:
> >>
> >>
> >> On 23.05.2023 03:15, Bjorn Andersson wrote:
> >>> From: Bjorn Andersson
> >>>
> >>> Add Adre
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