On 13/06/23 23:47, Conor Dooley wrote:
> On Tue, Jun 13, 2023 at 12:34:23PM +0530, Manikandan Muralidharan wrote:
>> - XLCDC in SAM9X7 has different sets of registers and additional
>> configuration bits when compared to previous HLCDC IP. Read/write
>> operation on the controller registers is now
On 14/06/23 12:19, Claudiu Beznea - M18063 wrote:
> On 13.06.2023 10:04, Manikandan Muralidharan wrote:
>> From: Durai Manickam KR
>>
>> Add compatible string check to differentiate XLCDC and HLCDC code
>> within the atmel-hlcdc driver files.
>>
>> Signed-off-by: Durai Manickam KR
>>
On Thu, Jun 15, 2023 at 01:22:17AM +0200, Sebastian Reichel wrote:
> Hi,
>
> On Tue, Jun 13, 2023 at 08:56:30AM +0200, Miquel Raynal wrote:
> > Hi Michael,
> >
> > michael.rie...@wolfvision.net wrote on Tue, 13 Jun 2023 08:15:26 +0200:
> >
> > > Hi Miquel,
> > >
> > > On 6/9/23 16:59, Miquel
On 14/06/23 12:17, Claudiu Beznea - M18063 wrote:
> Hi, Manikandan,
>
> On 13.06.2023 10:04, Manikandan Muralidharan wrote:
>> From: Durai Manickam KR
>>
>> The register address of the XLCDC IP used in SAM9X7 are different from
>> the previous HLCDC.Defining those address space with valid
On 6/15/2023 5:24 AM, Pablo Ceballos wrote:
This is to eliminate all cases of "*ERROR* LSPCON mode hasn't settled",
followed by link training errors. Intel engineers recommended increasing
this timeout and that does resolve the issue.
On some CometLake-based device designs the Parade PS175
Hi,
On 2023/6/7 20:59, Lucas Stach wrote:
Currently the FE is spinning way too fast when polling for new work in
'way' -> 'away'
the FE idleloop.
'idleloop' -> 'idle loop'
As each poll fetches 16 bytes from memory, a GPU running
at 1GHz with the current setting of 200 wait cycle between
在 2023-06-14星期三的 14:31 -0700，Doug Anderson写道：
> Hi,
>
> On Wed, Jun 14, 2023 at 1:22 AM AngeloGioacchino Del Regno
> wrote:
> >
> > Il 13/06/23 01:32, Douglas Anderson ha scritto:
> > > In order to read the EDID from an eDP panel, you not only need to
> > > power on the bridge chip itself but
From: Dave Airlie
This seems to have existed for ever but is now more apparant after
9bff18d13473a9fdf81d5158248472a9d8ecf2bd (drm/ttm: use per BO cleanup workers)
My analysis:
two threads are running,
one in the irq signalling the fence, in dma_fence_signal_timestamp_locked,
it has done the
Hi Dave, Daniel,
Fixes for 6.4.
The following changes since commit 858fd168a95c5b9669aac8db6c14a9aeab446375:
Linux 6.4-rc6 (2023-06-11 14:35:30 -0700)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-6.4-2023-06-14
for you to
Hi,
On Mon, Jun 12, 2023 at 11:25 AM Dmitry Baryshkov
wrote:
>
> Change adreno_is_a690() prototype to accept the const struct adreno_gpu
> pointer instead of a non-const one. This fixes the following warning:
>
> In file included from drivers/gpu/drm/msm/msm_drv.c:33:
>
Add Cadence HDP-TX HDMI PHY driver for i.MX8MQ.
Cadence HDP-TX PHY could be put in either DP mode or
HDMI mode base on the configuration chosen.
HDMI PHY mode is configurated in the driver.
Signed-off-by: Sandor Yu
---
drivers/phy/freescale/Kconfig | 9 +
Add Cadence HDP-TX DisplayPort PHY driver for i.MX8MQ
Cadence HDP-TX PHY could be put in either DP mode or
HDMI mode base on the configuration chosen.
DisplayPort PHY mode is configurated in the driver.
Signed-off-by: Sandor Yu
---
drivers/phy/freescale/Kconfig | 9 +
Add bindings for Freescale iMX8MQ DP and HDMI PHY.
Signed-off-by: Sandor Yu
---
.../bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml | 53 +++
1 file changed, 53 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml
diff --git
Add a new DRM HDMI bridge driver for Cadence MHDP8501
that used in Freescale i.MX8MQ SoC.
MHDP8501 could support HDMI or DisplayPort standards according
embedded Firmware running in the uCPU.
For iMX8MQ SoC, the HDMI FW was loaded and activated by SOC ROM code.
Bootload binary included HDMI FW
Allow HDMI PHYs to be configured through the generic
functions through a custom structure added to the generic union.
The parameters added here are based on HDMI PHY
implementation practices. The current set of parameters
should cover the potential users.
Signed-off-by: Sandor Yu
---
Add a new DRM DisplayPort bridge driver for Candence MHDP8501
used in i.MX8MQ SOC. MHDP8501 could support HDMI or DisplayPort
standards according embedded Firmware running in the uCPU.
For iMX8MQ SOC, the DisplayPort FW was loaded and activated by SOC
ROM code. Bootload binary included HDMI FW
Add bindings for Cadence MHDP8501 DisplayPort and HDMI driver.
Signed-off-by: Sandor Yu
---
.../display/bridge/cdns,mhdp8501.yaml | 105 ++
1 file changed, 105 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml
diff
MHDP8546 mailbox access functions will be share to other mhdp driver
and Cadence HDP-TX HDMI/DP PHY drivers.
Move those functions to head file include/drm/bridge/cdns-mhdp-mailbox.h
and convert them to macro functions.
Signed-off-by: Sandor Yu
---
.../drm/bridge/cadence/cdns-mhdp8546-core.c |
The patch set initial support for Cadence MHDP8501(HDMI/DP) DRM bridge
drivers and Cadence HDP-TX PHY(HDMI/DP) drivers for Freescale i.MX8MQ.
The patch set compose of DRM bridge drivers and PHY drivers.
Both of them need the followed two patches to pass build.
drm: bridge: Cadence: convert
This is to eliminate all cases of "*ERROR* LSPCON mode hasn't settled",
followed by link training errors. Intel engineers recommended increasing
this timeout and that does resolve the issue.
On some CometLake-based device designs the Parade PS175 takes more than
400ms to settle in PCON mode. 100
On Fri, Jun 09, 2023 at 05:56:33PM +0200, Miquel Raynal wrote:
> The content of of_device_uevent() is currently hardcoded in a driver
> that can be compiled as a module. Nothing prevents of_device_uevent() to
> be exported to modules, most of the other helpers in of/device.c
> actually are. The
Hi,
On Sat, Jun 10, 2023 at 10:45:25PM +0200, Sam Ravnborg wrote:
> Hi Miquel,
>
> On Fri, Jun 09, 2023 at 04:59:51PM +0200, Miquel Raynal wrote:
> > A very basic debugging rule when a device is connected for the first
> > time is to access a read-only register which contains known data in
> >
Hi,
On Tue, Jun 13, 2023 at 08:56:30AM +0200, Miquel Raynal wrote:
> Hi Michael,
>
> michael.rie...@wolfvision.net wrote on Tue, 13 Jun 2023 08:15:26 +0200:
>
> > Hi Miquel,
> >
> > On 6/9/23 16:59, Miquel Raynal wrote:
> > > The spi core warns us about using an of_device_id table without a
Hi, Dave & Daniel:
This includes:
1. Add display binding document for MT6795
Regards,
Chun-Kuang.
The following changes since commit ac9a78681b921877518763ba0e89202254349d1b:
Linux 6.4-rc1 (2023-05-07 13:34:35 -0700)
are available in the Git repository at:
On Mon, Jun 12, 2023 at 11:25 AM Dmitry Baryshkov
wrote:
>
> Change adreno_is_a690() prototype to accept the const struct adreno_gpu
> pointer instead of a non-const one. This fixes the following warning:
>
> In file included from drivers/gpu/drm/msm/msm_drv.c:33:
>
On 2023-06-15 01:44:02, Dmitry Baryshkov wrote:
> It makes no sense to pass NULL parameters to dsi_ctrl_config() in the
> disable case. Split dsi_ctrl_config() into enable and disable parts and
> drop unused params.
>
> Signed-off-by: Dmitry Baryshkov
Indeed, it makes much more sense to split
On 2023-06-15 01:44:01, Dmitry Baryshkov wrote:
> Several source clocks are not used anymore, so stop handling them.
>
> Signed-off-by: Dmitry Baryshkov
Indeed, we were not using these parent clocks for anything.
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 33
On 2023-06-14 14:23:38, Marijn Suijten wrote:
> Tested this on SM8350 which actually has DSI 2.5, and it is also
> corrupted with this series so something else on this series might be
> broken.
Never mind, this was a bad conflict-resolve. Jessica's original
BURST_MODE patch was RMW'ing
On 13/06/2023 02:37, Jessica Zhang wrote:
During a frame transfer in command mode, there could be frequent
LP11 <-> HS transitions when multiple DCS commands are sent mid-frame or
if the DSI controller is running on slow clock and is throttled. To
minimize frame latency due to these transitions,
It makes no sense to pass NULL parameters to dsi_ctrl_config() in the
disable case. Split dsi_ctrl_config() into enable and disable parts and
drop unused params.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 18 +-
1 file changed, 9 insertions(+), 9
Several source clocks are not used anymore, so stop handling them.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 33 --
1 file changed, 33 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
On 6/14/2023 1:41 PM, Harshit Mogalapalli wrote:
Smatch warns:
drivers/gpu/drm/i915/gt/uc/intel_huc.c:388
intel_huc_init() warn: missing error code 'err'
When the allocation of VMAs fail: The value of err is zero at this
point and it is passed to PTR_ERR and also finally
From: Florian Fainelli
74165 is a 16nm process SoC with a 10/100 integrated Ethernet PHY,
utilize the recently defined 16nm EPHY macro to configure that PHY.
Reviewed-by: Simon Horman
Reviewed-by: Andrew Lunn
Signed-off-by: Florian Fainelli
Signed-off-by: Justin Chen
---
Add maintainers entry for ASP 2.0 Ethernet driver.
Reviewed-by: Simon Horman
Signed-off-by: Florian Fainelli
Signed-off-by: Justin Chen
---
v3
- Change from gmail to broadcom emails
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
Add support for eth_mac_stats, rmon_stats, and eth_ctrl_stats.
Signed-off-by: Justin Chen
---
.../net/ethernet/broadcom/asp2/bcmasp_ethtool.c| 77 ++
.../net/ethernet/broadcom/asp2/bcmasp_intf_defs.h | 63 +-
2 files changed, 139 insertions(+), 1
Add support for ethernet driver specific stats.
Signed-off-by: Justin Chen
---
drivers/net/ethernet/broadcom/asp2/bcmasp.c| 1 +
drivers/net/ethernet/broadcom/asp2/bcmasp.h| 21 +++
.../net/ethernet/broadcom/asp2/bcmasp_ethtool.c| 158 +
Add mdio compat string for ASP 2.0 ethernet driver.
Reviewed-by: Simon Horman
Reviewed-by: Andrew Lunn
Signed-off-by: Florian Fainelli
Signed-off-by: Justin Chen
---
drivers/net/mdio/mdio-bcm-unimac.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/mdio/mdio-bcm-unimac.c
Add support for Wake-On-Lan magic packet and magic packet with password.
Signed-off-by: Justin Chen
---
drivers/net/ethernet/broadcom/asp2/bcmasp.c| 148 +
drivers/net/ethernet/broadcom/asp2/bcmasp.h| 18 +++
.../net/ethernet/broadcom/asp2/bcmasp_ethtool.c
Add support for the Broadcom ASP 2.0 Ethernet controller which is first
introduced with 72165. This controller features two distinct Ethernet
ports that can be independently operated.
Reviewed-by: Simon Horman
Signed-off-by: Florian Fainelli
Signed-off-by: Justin Chen
---
v7
- Fixed
Add support for eee mode.
Signed-off-by: Justin Chen
---
drivers/net/ethernet/broadcom/asp2/bcmasp.h| 4 ++
.../net/ethernet/broadcom/asp2/bcmasp_ethtool.c| 61 ++
drivers/net/ethernet/broadcom/asp2/bcmasp_intf.c | 6 +++
3 files changed, 71 insertions(+)
Add support for wake on network filters. The max match is 256 bytes.
Signed-off-by: Justin Chen
---
drivers/net/ethernet/broadcom/asp2/bcmasp.c| 595 +
drivers/net/ethernet/broadcom/asp2/bcmasp.h| 40 ++
.../net/ethernet/broadcom/asp2/bcmasp_ethtool.c|
The ASP 2.0 Ethernet controller uses a brcm unimac.
Reviewed-by: Simon Horman
Acked-by: Conor Dooley
Signed-off-by: Florian Fainelli
Signed-off-by: Justin Chen
---
Documentation/devicetree/bindings/net/brcm,unimac-mdio.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Florian Fainelli
Add a binding document for the Broadcom ASP 2.0 Ethernet
controller.
Reviewed-by: Conor Dooley
Signed-off-by: Florian Fainelli
Signed-off-by: Justin Chen
---
v7
- Added "unevaluatedProperties: False"
v6
- Moved compatible to the top
- Changed
Add support for the Broadcom ASP 2.0 Ethernet controller which is first
introduced with 72165.
Florian Fainelli (2):
dt-bindings: net: Brcm ASP 2.0 Ethernet controller
net: phy: bcm7xxx: Add EPHY entry for 74165
Justin Chen (9):
dt-bindings: net: brcm,unimac-mdio: Add asp-v2.0
net:
On Wed, Jun 14, 2023 at 09:03:34AM -0700, Bjorn Andersson wrote:
> On Mon, 22 May 2023 18:15:19 -0700, Bjorn Andersson wrote:
> > This series introduces support for A690 in the DRM/MSM driver and
> > enables it for the two SC8280XP laptops.
> >
> > Bjorn Andersson (3):
> > drm/msm/adreno: Add
On 2023-06-14 13:39:57, Abhinav Kumar wrote:
> On 6/14/2023 12:54 PM, Abhinav Kumar wrote:
> > On 6/14/2023 12:35 PM, Abhinav Kumar wrote:
> >> On 6/14/2023 5:23 AM, Marijn Suijten wrote:
> >>> On 2023-06-14 15:01:59, Dmitry Baryshkov wrote:
> On 14/06/2023 14:42, Marijn Suijten wrote:
>
Hi,
On Wed, Jun 14, 2023 at 1:22 AM AngeloGioacchino Del Regno
wrote:
>
> Il 13/06/23 01:32, Douglas Anderson ha scritto:
> > In order to read the EDID from an eDP panel, you not only need to
> > power on the bridge chip itself but also the panel. In the ps8640
> > driver, this was made to work
On Tue, Jun 13, 2023 at 11:08 PM Stephan Gerhold wrote:
> I'm still quite confused about what exactly is supposed to be in
> (un)prepare and what in enable/disable. I've seen some related
> discussion every now and then but it's still quite inconsistent across
> different panel drivers... Can
On 14/06/2023 23:39, Abhinav Kumar wrote:
On 6/14/2023 12:54 PM, Abhinav Kumar wrote:
On 6/14/2023 12:35 PM, Abhinav Kumar wrote:
On 6/14/2023 5:23 AM, Marijn Suijten wrote:
On 2023-06-14 15:01:59, Dmitry Baryshkov wrote:
On 14/06/2023 14:42, Marijn Suijten wrote:
On 2023-06-13
Smatch warns:
drivers/gpu/drm/i915/gt/uc/intel_huc.c:388
intel_huc_init() warn: missing error code 'err'
When the allocation of VMAs fail: The value of err is zero at this
point and it is passed to PTR_ERR and also finally returning zero which
is success instead of failure.
On 6/14/2023 12:54 PM, Abhinav Kumar wrote:
On 6/14/2023 12:35 PM, Abhinav Kumar wrote:
On 6/14/2023 5:23 AM, Marijn Suijten wrote:
On 2023-06-14 15:01:59, Dmitry Baryshkov wrote:
On 14/06/2023 14:42, Marijn Suijten wrote:
On 2023-06-13 18:57:11, Jessica Zhang wrote:
DPU 5.x+ supports
On Mon, May 29, 2023 at 03:52:37PM +0200, Konrad Dybcio wrote:
>
> A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125
> (trinket) and SM6225 (khaje). Trinket does not support speed binning
> (only a single SKU exists) and we don't yet support khaje upstream.
> Hence, add a fuse
On Mon, May 29, 2023 at 03:52:36PM +0200, Konrad Dybcio wrote:
>
> A619_holi is implemented on at least two SoCs: SM4350 (holi) and SM6375
> (blair). This is what seems to be a first occurrence of this happening,
> but it's easy to overcome by guarding the SoC-specific fuse values with
>
On 6/14/2023 12:35 PM, Abhinav Kumar wrote:
On 6/14/2023 5:23 AM, Marijn Suijten wrote:
On 2023-06-14 15:01:59, Dmitry Baryshkov wrote:
On 14/06/2023 14:42, Marijn Suijten wrote:
On 2023-06-13 18:57:11, Jessica Zhang wrote:
DPU 5.x+ supports a databus widen mode that allows more data to
On Mon, May 29, 2023 at 03:52:35PM +0200, Konrad Dybcio wrote:
>
> Before transitioning to using per-SoC and not per-Adreno speedbin
> fuse values (need another patchset to land elsewhere), a good
> improvement/stopgap solution is to use adreno_is_aXYZ macros in
> place of explicit revision
On Mon, May 29, 2023 at 03:52:34PM +0200, Konrad Dybcio wrote:
>
> The GPU can only be one at a time. Turn a series of ifs into if +
> elseifs to save some CPU cycles.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Konrad Dybcio
Reviewed-by: Akhil P Oommen
-Akhil
> ---
>
On Mon, May 29, 2023 at 03:52:33PM +0200, Konrad Dybcio wrote:
>
> Adreno 619 expects some tunables to be set differently. Make up for it.
>
> Fixes: b7616b5c69e6 ("drm/msm/adreno: Add A619 support")
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Konrad Dybcio
> ---
>
On Mon, May 29, 2023 at 03:52:32PM +0200, Konrad Dybcio wrote:
>
> A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It
> features no GMU, as it's implemented solely on SoCs with SMD_RPM.
> What's more interesting is that it does not feature a VDDGX line
> either, being powered
On 6/14/2023 5:23 AM, Marijn Suijten wrote:
On 2023-06-14 15:01:59, Dmitry Baryshkov wrote:
On 14/06/2023 14:42, Marijn Suijten wrote:
On 2023-06-13 18:57:11, Jessica Zhang wrote:
DPU 5.x+ supports a databus widen mode that allows more data to be sent
per pclk. Enable this feature flag on
Hi Lucas
>
> Currently the clock is enabled in the runtime resume function, but are
> disabled a level further down in the callstack in the suspend function.
> Move the clock disable into the suspend function to make handling
> symmetrical between resume and suspend.
>
> Signed-off-by: Lucas Stach
Hi Lucas
>
> Conceptually events are the right abstraction to handle the GPU
> runtime PM state: as long as any event is pending the GPU can not
> be idle. Events are also properly freed and reallocated when the
> GPU has been reset after a hang.
>
> Signed-off-by: Lucas Stach
> ---
>
Hi Lucas
>
> Clearing the whole bitmap at once is only a minor optimization in
> a path that should be extremely cold. Free the events by calling
> event_free() instead of directly manipulating the completion count
> and event bitmap.
>
> Signed-off-by: Lucas Stach
Reviewed-by: Christian
Hi Lucas
>
> So it can use the event_free function without adding another
> forward declaration. No functional change.
>
> Signed-off-by: Lucas Stach
Reviewed-by: Christian Gmeiner
> ---
> drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 88 +--
> 1 file changed, 44
Hi Lucas
>
> Currently the FE is spinning way too fast when polling for new work in
> the FE idleloop. As each poll fetches 16 bytes from memory, a GPU running
> at 1GHz with the current setting of 200 wait cycle between fetches causes
> 80 MB/s of memory traffic just to check for new work when
Hi
On 2023/6/14 15:45, Lucas Stach wrote:
Hi,
Am Mittwoch, dem 14.06.2023 um 00:42 +0800 schrieb Sui Jingfeng:
Hi, Lucas
I love your patch, perhaps something to improve:
The MLCG stand for "Module Level Clock Gating",
without reading the commit message, I guess there may have people don't
On Wed, Jun 07, 2023 at 02:58:41PM +0200, Lucas Stach wrote:
> Module level clock gating and the pulse eater might interfere with
> the GPU reset, as they both have the potential to stop the clock
> and thus reset propagation to parts of the GPU.
>
> Signed-off-by: Lucas Stach
> ---
> I'm not
From: Pranjal Ramajor Asha Kanojiya
smatch warning:
drivers/accel/qaic/qaic_data.c:620 qaic_free_object() error:
dereferencing freed memory 'obj->import_attach'
obj->import_attach is detached and freed using dma_buf_detach().
But used after free to decrease the dmabuf
The drm_atomic_get_mst_payload_state() function may
return NULL, which may cause null pointer deference,
and most other callsites of drm_atomic_get_mst_payload_state()
do Null check. Add Null check for return value of
drm_atomic_get_mst_payload_state().
Found by our static analysis tool.
The dev_get_platdata() function may return NULL, which may
cause null pointer deference, and most other callsites of
dev_get_platdata() do Null check. Add Null check for return
value of dev_get_platdata().
Found by our static analysis tool.
Signed-off-by: Chenyuan Mi
---
On Tue, 7 Feb 2023 19:40:49 -0800, Bjorn Andersson wrote:
> This series introduces support for A690 in the DRM/MSM driver and
> enables it for the two SC8280XP laptops.
>
> Bjorn Andersson (3):
> drm/msm/adreno: Add Adreno A690 support
> arm64: dts: qcom: sc8280xp: Add GPU related nodes
>
On Wed, 14 Jun 2023 07:22:02 -0700, Bjorn Andersson wrote:
> With the A690 support merged in the drm/msm driver, this series adds the
> DeviceTree pieces to make it go on sc8280xp.
>
> Note that in order for the GPU driver to probe, the last change
> requires (which is now in linux-next):
>
On Mon, 22 May 2023 18:15:19 -0700, Bjorn Andersson wrote:
> This series introduces support for A690 in the DRM/MSM driver and
> enables it for the two SC8280XP laptops.
>
> Bjorn Andersson (3):
> drm/msm/adreno: Add Adreno A690 support
> arm64: dts: qcom: sc8280xp: Add GPU related nodes
>
On 6/14/23 15:22, Tvrtko Ursulin wrote:
On 14/06/2023 13:35, Sumitra Sharma wrote:
Pages allocated with GFP_KERNEL cannot come from Highmem.
That is why there is no need to call kmap() on them.
Are you sure it is GFP_KERNEL backed and not tmpfs? I am not sure
myself so let me copy Matt
Am 2023-06-13 um 22:04 schrieb Jiapeng Chong:
Use memdup_user() rather than duplicating its implementation. This is a
little bit restricted to reduce false positives.
./drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c:2813:13-20: WARNING
opportunity for memdup_user.
Reported-by: Abaci
On Wed, Jun 14, 2023 at 04:40:50PM +0200, Nicolas Ferre wrote:
> On 13/06/2023 at 20:21, Conor Dooley wrote:
> > On Tue, Jun 13, 2023 at 08:17:13PM +0200, Krzysztof Kozlowski wrote:
> > > On 13/06/2023 09:04, Manikandan Muralidharan wrote:
> > > > Add new compatible string for the XLCD controller
Hi Krzysztof,
On Tue, 2023-06-13 at 20:24 +0200, Krzysztof Kozlowski wrote:
> On 13/06/2023 16:47, Sarah Walker wrote:
> > Add the device tree binding documentation for the Series AXE GPU used in
> > TI AM62 SoCs.
> >
>
> I don't see improvements. That's a NAK :(
>
> This is a friendly
On 13/06/2023 at 20:21, Conor Dooley wrote:
On Tue, Jun 13, 2023 at 08:17:13PM +0200, Krzysztof Kozlowski wrote:
On 13/06/2023 09:04, Manikandan Muralidharan wrote:
Add new compatible string for the XLCD controller on SAM9X7 SoC.
Signed-off-by: Manikandan Muralidharan
---
With the A690 support merged in the drm/msm driver, this series adds the
DeviceTree pieces to make it go on sc8280xp.
Note that in order for the GPU driver to probe, the last change
requires (which is now in linux-next):
Hi
Am 14.06.23 um 15:51 schrieb Lee Jones:
On Tue, 13 Jun 2023, Thomas Zimmermann wrote:
Struct bd6107_platform_data refers to a platform device within
the Linux device hierarchy. The test in bd6107_backlight_check_fb()
compares it against the fbdev device in struct fb_info.dev, which
is
Am 14.06.23 um 15:12 schrieb Thomas Zimmermann:
Use /* */ in initializer macro to avoid out-commenting the comma
at the end of the line.
Reported-by: Christian König
Closes:
On Tue, 13 Jun 2023, Thomas Zimmermann wrote:
> Struct bd6107_platform_data refers to a platform device within
> the Linux device hierarchy. The test in bd6107_backlight_check_fb()
> compares it against the fbdev device in struct fb_info.dev, which
> is different. Fix the test by comparing to
On 14/06/2023 13:35, Sumitra Sharma wrote:
Pages allocated with GFP_KERNEL cannot come from Highmem.
That is why there is no need to call kmap() on them.
Are you sure it is GFP_KERNEL backed and not tmpfs? I am not sure myself
so let me copy Matt and Thomas if they happen to know off hand.
Use /* */ in initializer macro to avoid out-commenting the comma
at the end of the line.
Reported-by: Christian König
Closes:
https://lore.kernel.org/dri-devel/20230530150253.22758-1-tzimmerm...@suse.de/T/#m356cda2679c17d7a01f30ce2b5282cd9046ea6d4
Fixes: f1061fa641b8 ("fbdev: Add initializer
On Wed, 14 Jun 2023 14:30:53 +0200
Christian König wrote:
> Am 14.06.23 um 14:23 schrieb Boris Brezillon:
> > Hi Christian,
> >
> > On Thu, 4 May 2023 13:51:47 +0200
> > "Christian König" wrote:
> >
> >> This adds the infrastructure for an execution context for GEM buffers
> >> which is
Am 14.06.23 um 14:23 schrieb Boris Brezillon:
Hi Christian,
On Thu, 4 May 2023 13:51:47 +0200
"Christian König" wrote:
This adds the infrastructure for an execution context for GEM buffers
which is similar to the existing TTMs execbuf util and intended to replace
it in the long term.
Hi Christian,
On Thu, 4 May 2023 13:51:47 +0200
"Christian König" wrote:
> This adds the infrastructure for an execution context for GEM buffers
> which is similar to the existing TTMs execbuf util and intended to replace
> it in the long term.
>
> The basic functionality is that we abstracts
On 2023-06-14 15:01:59, Dmitry Baryshkov wrote:
> On 14/06/2023 14:42, Marijn Suijten wrote:
> > On 2023-06-13 18:57:11, Jessica Zhang wrote:
> >> DPU 5.x+ supports a databus widen mode that allows more data to be sent
> >> per pclk. Enable this feature flag on all relevant chipsets.
> >>
> >>
, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url:
https://github.com/intel-lab-lkp/linux/commits/Jiapeng-Chong/drm-amdkfd-Switch-over-to-memdup_user/20230614-100553
base: next-20230613
patch link:
https://lore.kernel.org/r
On 14/06/2023 14:42, Marijn Suijten wrote:
On 2023-06-13 18:57:11, Jessica Zhang wrote:
DPU 5.x+ supports a databus widen mode that allows more data to be sent
per pclk. Enable this feature flag on all relevant chipsets.
Signed-off-by: Jessica Zhang
---
Hi
Am 14.06.23 um 13:29 schrieb Christian König:
Am 30.05.23 um 17:02 schrieb Thomas Zimmermann:
For framebuffers in I/O and system memory, add macros that set
struct fb_ops to the respective callback functions.
For deferred I/O, add macros that generate callback functions with
damage
On 2023-06-13 18:57:11, Jessica Zhang wrote:
> DPU 5.x+ supports a databus widen mode that allows more data to be sent
> per pclk. Enable this feature flag on all relevant chipsets.
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ++-
>
Hi Laurent,
Thanks for the feedback.
> Subject: Re: [PATCH v5 01/11] i2c: Enhance i2c_new_ancillary_device API
>
> On Wed, Jun 14, 2023 at 08:21:38AM +, Biju Das wrote:
> > Hi Laurent,
> >
> > Thanks for the feedback.
> >
> > > Subject: Re: [PATCH v5 01/11] i2c: Enhance
Am 30.05.23 um 17:02 schrieb Thomas Zimmermann:
For framebuffers in I/O and system memory, add macros that set
struct fb_ops to the respective callback functions.
For deferred I/O, add macros that generate callback functions with
damage handling. Add initializer macros that set struct fb_ops
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH v5 01/11] i2c: Enhance i2c_new_ancillary_device API
>
> Hi Biju,
>
> On Wed, Jun 14, 2023 at 10:21 AM Biju Das
> wrote:
> > > Subject: Re: [PATCH v5 01/11] i2c: Enhance i2c_new_ancillary_device
> > > API On Tue, Jun 13, 2023 at
Hi,
On 2023/6/13 11:01, Sui Jingfeng wrote:
From: Sui Jingfeng
Deal only with the VGA devcie(pdev->class == 0x0300), so replace the
pci_get_subsys() function with pci_get_class(). Filter the non-PCI display
device(pdev->class != 0x0300) out. There no need to process the non-display
PCI
On 2023-06-14 12:39:13, Marijn Suijten wrote:
> > > > - /* add register dump support */
> > > > - dpu_debugfs_create_regset32("src_blk", 0400,
> > > > - debugfs_root,
> > > > - sblk->src_blk.base + cfg->base,
> > > > -
Hi
Am 14.06.23 um 10:26 schrieb Sui Jingfeng:
Hi,
On 2023/6/14 13:34, Thomas Zimmermann wrote:
Hi
Am 14.06.23 um 04:06 schrieb Sui Jingfeng:
On 2023/6/14 01:27, Sui Jingfeng wrote:
Wow, so many drivers get nuked!
On 2023/6/13 22:51, Thomas Zimmermann wrote:
All drivers initialize this
On 2023-05-21 21:16:39, Marijn Suijten wrote:
> On 2023-05-21 20:12:00, Marijn Suijten wrote:
> > On 2023-05-21 20:21:46, Dmitry Baryshkov wrote:
> > > Drop SSPP-specifig debugfs register dumps in favour of using
> > > debugfs/dri/0/kms or devcoredump.
> > >
> > > Signed-off-by: Dmitry Baryshkov
On Tue, Jun 13, 2023 at 07:16:06PM +0100, Conor Dooley wrote:
> On Tue, Jun 13, 2023 at 12:34:22PM +0530, Manikandan Muralidharan wrote:
> > + /* Other SoC's that supports HLCDC IP */
>
> Should this be "Other SoCs that do not support HLCDC IP"?
Clearly a reading comprehension fail
On Tue, Jun 13, 2023 at 07:18:25PM +0100, Conor Dooley wrote:
> On Tue, Jun 13, 2023 at 12:34:18PM +0530, Manikandan Muralidharan wrote:
> > Add new compatible string for the XLCD controller on SAM9X7 SoC.
>
> You should probably indicate here why this is not compatible with the
> existing SoCs
1 - 100 of 146 matches
Mail list logo
