On 26.09.2023 16:24, Nirmoy Das wrote:
PIPE_CONTROL_FLUSH_L3 is not needed for aux invalidation
so don't set that.
Fixes: 78a6ccd65fa3 ("drm/i915/gt: Ensure memory quiesced before invalidation")
Cc: Jonathan Cavitt
Cc: Andi Shyti
Cc: # v5.8+
Cc: Andrzej Hajda
Cc: Tvrtko Ursulin
Cc: Matt
Am 26.09.23 um 15:09 schrieb Harry Wentland:
On 2023-09-26 01:56, Cong Liu wrote:
This patch fixes a null pointer dereference in the error message that is
printed when the Display Core (DC) fails to initialize. The original
message includes the DC version number, which is undefined if the DC
On 22-09-2023 19:17, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Use the newly added drm_print_memory_stats helper to show memory
> utilisation of our objects in drm/driver specific fdinfo output.
>
> To collect the stats we walk the per memory regions object lists
> and accumulate
On 26-09-2023 21:12, Tvrtko Ursulin wrote:
>
> On 26/09/2023 16:29, Iddamsetty, Aravind wrote:
>> On 22-09-2023 19:16, Tvrtko Ursulin wrote:
>>> From: Tvrtko Ursulin
>>>
>>> At the moment memory region names are a bit too varied and too
>>> inconsistent to be used for ABI purposes, like for
Due to a bug in GuC firmware, Mesa can't enable by default the usage of
compute engines in DG2 and newer.
A new GuC firmware fixed the issue but until now there was no way
for Mesa to know if KMD was running with the fixed GuC version or not,
so this uAPI is required.
It may be expanded in
Fixes all regressions we saw, I also run some extra vulkan and GL
workloads, no regressions observed.
Tested-by: Tapani Pälli
On 26.9.2023 17.24, Nirmoy Das wrote:
PIPE_CONTROL_FLUSH_L3 is not needed for aux invalidation
so don't set that.
Fixes: 78a6ccd65fa3 ("drm/i915/gt: Ensure memory
On Tue, 26 Sept 2023 at 20:52, Danilo Krummrich wrote:
>
> Commit f72c2db47080 ("drm/gpuvm: rename struct drm_gpuva_manager to
> struct drm_gpuvm") did also change the corresponding filenames which are
> referenced from the documentation, but were not adjusted accordingly.
> Hence, fix up those
Hi,
On 2023-09-19 01:01, Matthew Brost wrote:
> In XE, the new Intel GPU driver, a choice has made to have a 1 to 1
> mapping between a drm_gpu_scheduler and drm_sched_entity. At first this
> seems a bit odd but let us explain the reasoning below.
>
> 1. In XE the submission order from multiple
On Sat, 2023-09-23 at 19:34 +0200, Krzysztof Kozlowski wrote:
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> On 22/09/2023 09:21, Moudy Ho wrote:
> > Add the fundamental hardware configuration of component TDSHP,
>
On 2023-09-26 01:56, Cong Liu wrote:
This patch fixes a null pointer dereference in the error message that is
printed when the Display Core (DC) fails to initialize. The original
message includes the DC version number, which is undefined if the DC is
not initialized.
Fixes: 9788d087caff
Hi,
On 2023-09-26 20:13, Danilo Krummrich wrote:
> On 9/26/23 22:43, Luben Tuikov wrote:
>> Hi,
>>
>> On 2023-09-24 18:43, Danilo Krummrich wrote:
>>> Currently, job flow control is implemented simply by limiting the amount
>>> of jobs in flight. Therefore, a scheduler is initialized with a
>>>
Report the maximum number of IBs that can be pushed with a single
DRM_IOCTL_NOUVEAU_EXEC through DRM_IOCTL_NOUVEAU_GETPARAM.
While the maximum number of IBs per ring might vary between chipsets,
the kernel will make sure that userspace can only push a fraction of the
maximum number of IBs per
Use channel class definitions instead of magic numbers.
Signed-off-by: Danilo Krummrich
---
drivers/gpu/drm/nouveau/nouveau_chan.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c
b/drivers/gpu/drm/nouveau/nouveau_chan.c
index
Use actual struct nvif_mclass instead of identical anonymous struct.
Signed-off-by: Danilo Krummrich
---
drivers/gpu/drm/nouveau/nouveau_chan.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c
On 2023-09-19 01:01, Matthew Brost wrote:
> Add scheduler submit ready, stop, and start helpers to hide the
> implementation details of the scheduler from the drivers.
>
> Signed-off-by: Matthew Brost
> ---
> .../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 2 +-
>
Hi,
On 9/27/23 01:48, Luben Tuikov wrote:
Hi,
Please also CC me to the whole set, as opposed to just one patch of the set.
And so in the future.
There is no series. I created a series in the first place, but finally decided
to
send this one and a few driver patches separately. However, I
On 9/26/23 22:43, Luben Tuikov wrote:
Hi,
On 2023-09-24 18:43, Danilo Krummrich wrote:
Currently, job flow control is implemented simply by limiting the amount
of jobs in flight. Therefore, a scheduler is initialized with a
submission limit that corresponds to a certain amount of jobs.
Hi,
Please also CC me to the whole set, as opposed to just one patch of the set.
And so in the future.
Thanks!
--
Regards,
Luben
On 2023-09-26 16:43, Luben Tuikov wrote:
> Hi,
>
> On 2023-09-24 18:43, Danilo Krummrich wrote:
>> Currently, job flow control is implemented simply by limiting the
On Tue, Sep 26, 2023 at 11:58:02PM +0200, Nirmoy Das wrote:
> On MTL GEN12_RING_FAULT_REG is not replicated so don't
> do mcr based operation for this register.
>
> v2: use MEDIA_VER() instead of GRAPHICS_VER()(Matt).
>
> Signed-off-by: Nirmoy Das
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c
On MTL GEN12_RING_FAULT_REG is not replicated so don't
do mcr based operation for this register.
v2: use MEDIA_VER() instead of GRAPHICS_VER()(Matt).
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_gt.c | 13 -
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
Hi,
On Mon, Sep 18, 2023 at 9:19 AM Doug Anderson wrote:
>
> Hi,
>
> On Mon, Jul 3, 2023 at 6:21 AM Linus Walleij wrote:
> >
> > This is two patches fixing things I would normally complain about
> > in reviews, but alas I missed this one, so I go in and fix it up
> > myself.
> >
> > Discovering
Hi,
On 2023-09-24 18:43, Danilo Krummrich wrote:
> Currently, job flow control is implemented simply by limiting the amount
> of jobs in flight. Therefore, a scheduler is initialized with a
> submission limit that corresponds to a certain amount of jobs.
"certain"? How about this instead:
" ...
On 26/09/2023 05:20, Jason-JH Lin (林睿祥) wrote:
mdq_pkt_finialize_loop() at [PATCH 8/15].
>>>
>>> mtk-cmdq-helper.c and mtk-cmdq-mailbox.c are not in the
>>> same maintainer's tree, so I separate this to another patch from
>> [PATCH
>>> 8/15].
>>
>> Why? Anyway it has to go through same tree. You
On 26.09.2023 01:26, Richard Acayan wrote:
> The Snapdragon 670 uses similar clocks (with one frequency added) to the
> Snapdragon 845 but reports DPU revision 4.1. Add support for this DPU
> with configuration from the Pixel 3a downstream kernel.
>
> Since revision 4.0 is SDM845, reuse some
On 26.09.2023 21:10, Danila Tikhonov wrote:
>
> I think you mean by name downstream dt - sdmmagpie-gpu.dtsi
>
> You can see the forked version of the mainline here:
> https://github.com/sm7150-mainline/linux/blob/next/arch/arm64/boot/dts/qcom/sm7150.dtsi
>
> All fdt that we got here, if it is
Hi Nirmoy,
...
> > PIPE_CONTROL_FLUSH_L3 is not needed for aux invalidation
> > so don't set that.
> >
> > Fixes: 78a6ccd65fa3 ("drm/i915/gt: Ensure memory quiesced before
> > invalidation")
> > Cc: Jonathan Cavitt
> > Cc: Andi Shyti
> > Cc: # v5.8+
> > Cc: Andrzej Hajda
> > Cc: Tvrtko
Hi Matt,
On 9/26/2023 4:38 PM, Matt Roper wrote:
On Tue, Sep 26, 2023 at 04:18:42PM +0200, Nirmoy Das wrote:
On MTL GEN12_RING_FAULT_REG is not replicated so don't
do mcr based operation for this register.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_gt.c | 14
I think you mean by name downstream dt - sdmmagpie-gpu.dtsi
You can see the forked version of the mainline here:
https://github.com/sm7150-mainline/linux/blob/next/arch/arm64/boot/dts/qcom/sm7150.dtsi
All fdt that we got here, if it is useful for you:
SM7150 has 5 power levels which correspond to 5 speed-bin values: 0,
128, 146, 167, 172. Speed-bin value is calulated as FMAX/4.8MHz round up
to zero decimal places.
Also a618 on SM7150 uses a615 zapfw. Add a squashed version (.mbn).
Add this as machine = "qcom,sm7150", because speed-bin values
On Fri, Sep 22, 2023 at 8:34 AM Lukasz Majczak wrote:
>
> As drm_dp_get_mst_branch_device_by_guid() is called from
> drm_dp_get_mst_branch_device_by_guid(), mstb parameter has to be checked,
> otherwise NULL dereference may occur in the call to
> the memcpy() and cause following:
>
>
From: Ray Strode
A drm atomic commit can be quite slow on some hardware. It can lead
to a lengthy queue of commands that need to get processed and waited
on before control can go back to user space.
If user space is a real-time thread, that delay can have severe
consequences, leading to the
This patch adds support for SM7150 SoC machine.
Changes in v2:
- Use a630_gmu.bin instead of a618_gmu.bin.
- Use squashed version of a615_zap (.mbn).
- Drop .revn.
- Link to v1:
https://lore.kernel.org/all/20230913191957.26537-1-dan...@jiaxyga.com/
Danila Tikhonov (1):
drm/msm/adreno: Add
How do I bump this patch submission?
When suspending, add a timeout when calling
intel_gt_pm_wait_for_idle else if we have a lost
G2H event that holds a wakeref (which would be
indicative of a bug elsewhere in the driver),
driver will at least complete the suspend-resume
cycle, (albeit not hitting all the targets for
low power hw
This series is the result of debugging issues root caused to
races between the GuC's destroyed_worker_func being triggered
vs repeating suspend-resume cycles with concurrent delayed
fence signals for engine-freeing.
The reproduction steps require that an app is launched right
before the start of
If we are at the end of suspend or very early in resume
its possible an async fence signal (via rcu_call) is triggered
to free_engines which could lead us to the execution of
the context destruction worker (after a prior worker flush).
Thus, when suspending, insert an rcu_barrier at the start
of
When suspending, flush the context-guc-id
deregistration worker at the final stages of
intel_gt_suspend_late when we finally call gt_sanitize
that eventually leads down to __uc_sanitize so that
the deregistration worker doesn't fire off later as
we reset the GuC microcontroller.
Signed-off-by:
On 26.09.2023 19:42, Danila Tikhonov wrote:
> SM7150 has 5 power levels which correspond to 5 speed-bin values: 0,
> 128, 146, 167, 172. Speed-bin value is calulated as FMAX/4.8MHz round up
> to zero decimal places.
>
> Also a618 on SM7150 uses a615 zapfw. Add a squashed version (.mbn).
>
> Add
On 26.09.2023 20:24, Konrad Dybcio wrote:
> Non-Chrome SC7280-family platforms ship a ZAP shader with the Adreno GPU.
> Describe that and make sure it doesn't interfere with Chrome devices.
>
> Signed-off-by: Konrad Dybcio
> ---
> arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi | 2 ++
>
On 26.09.2023 20:24, Konrad Dybcio wrote:
> The SMMUs on sc7280 are cache-coherent. APPS_SMMU is marked as such,
> mark the GPU one as well.
>
> Signed-off-by: Konrad Dybcio
> ---
Fixes: 96c471970b7b ("arm64: dts: qcom: sc7280: Add gpu support")
Sorry.
Konrad
The SMMUs on sc7280 are cache-coherent. APPS_SMMU is marked as such,
mark the GPU one as well.
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
A643 (A635 speedbin 0xac) tops out at 812 MHz. Fill in the
opp-supported-hw appropriately.
Note that fuseval 0xac is referred to as speedbin 1 downstream, but
that was already in use upstream, so 2 was chosen instead.
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 12
GPU_SMMU SID 1 is meant for Adreno LPAC (Low Priority Async Compute).
On platforms that support it (in firmware), it is necessary to
describe that link, or Adreno register access will hang the board.
Add that and fix up the SMR mask of SID 0, which seems to have been
copypasted from another SoC.
Downstream calls this the "speedbin 1", but that number is already
occupied. Use index two.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
Non-Chrome SC7280-family platforms ship a ZAP shader with the Adreno GPU.
Describe that and make sure it doesn't interfere with Chrome devices.
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi | 2 ++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 10
When opp-supported-hw is present under an OPP node, but no form of
opp_set_supported_hw() has been called, that OPP is ignored by the API
and marked as unsupported.
Before Commit c928a05e4415 ("drm/msm/adreno: Move speedbin mapping to
device table"), an unknown speedbin would result in marking
Some (many?) devices with A635 expect a ZAP shader to be loaded.
Set the file name to allow for that.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
files changed, 24 insertions(+), 8 deletions(-)
---
base-commit: 4ae73bba62a367f2314f6ce69e3085a941983d8b
change-id: 20230926-topic-a643-a7ec9a08a3a1
Best regards,
--
Konrad Dybcio
> -Original Message-
> From: Nikula, Jani
> Sent: 07 September 2023 14:58
> To: dri-devel@lists.freedesktop.org
> Cc: intel-...@lists.freedesktop.org; Nikula, Jani ;
> Golani, Mitulkumar Ajitkumar
> Subject: [PATCH 5/6] drm/edid: add helpers to get/set struct cea_sad
> from/to 3-byte sad
> -Original Message-
> From: Nikula, Jani
> Sent: 07 September 2023 14:58
> To: dri-devel@lists.freedesktop.org
> Cc: intel-...@lists.freedesktop.org; Nikula, Jani ;
> Golani, Mitulkumar Ajitkumar
> Subject: [PATCH 6/6] drm/eld: add helpers to modify the SADs of an ELD
>
> Occasionally
From: Zack Rusin
Some drivers require the mapped tt pages to be decrypted. In an ideal
world this would have been handled by the dma layer, but the TTM page
fault handling would have to be rewritten to able to do that.
A side-effect of the TTM page fault handling is using a dma allocation
per
On Tue, Sep 26, 2023 at 04:24:01PM +0200, Nirmoy Das wrote:
> PIPE_CONTROL_FLUSH_L3 is not needed for aux invalidation
> so don't set that.
>
> Fixes: 78a6ccd65fa3 ("drm/i915/gt: Ensure memory quiesced before
> invalidation")
> Cc: Jonathan Cavitt
> Cc: Andi Shyti
> Cc: # v5.8+
> Cc: Andrzej
On Fri, 22 Sep 2023, Shyam Sundar S K wrote:
> PMF driver sends changing inputs from each subystem to TA for evaluating
> the conditions in the policy binary.
>
> Add initial support of plumbing in the PMF driver for Smart PC to get
> information from other subsystems in the kernel.
>
>
On Fri, 22 Sep 2023, Shyam Sundar S K wrote:
> PMF Policy binary is a encrypted and signed binary that will be part
> of the BIOS. PMF driver via the ACPI interface checks the existence
> of Smart PC bit. If the advertised bit is found, PMF driver walks
> the acpi namespace to find out the policy
On Fri, 22 Sep 2023, Shyam Sundar S K wrote:
> amd_pmf_dbgfs_register() needs to be called before amd_pmf_init_features().
Please answer to why? question too here.
> Hence change the sequence.
>
> Reviewed-by: Mario Limonciello
> Signed-off-by: Shyam Sundar S K
> ---
>
On Fri, 22 Sep 2023, Shyam Sundar S K wrote:
Add () to the function name in the shortlog. "Change signature" is quite
vague, perhaps you could come up something more descriptive.
> Make amd_pmf_set_dram_addr() as non-static so that same function
> can be used across files.
This says nothing
On Fri, 22 Sep 2023, Shyam Sundar S K wrote:
> PMF TA (Trusted Application) loads via the TEE environment into the
> AMD ASP.
>
> PMF-TA supports two commands:
> 1) Init: Initialize the TA with the PMF Smart PC policy binary and
> start the policy engine. A policy is a combination of inputs and
On Fri, 22 Sep 2023, Shyam Sundar S K wrote:
> AMD PMF driver loads the PMF TA (Trusted Application) into the AMD
> ASP's (AMD Security Processor) TEE (Trusted Execution Environment).
>
> PMF Trusted Application is a secured firmware placed under
> /lib/firmware/amdtee gets loaded only when the
> -Original Message-
> From: Nikula, Jani
> Sent: 26 September 2023 13:14
> To: Golani, Mitulkumar Ajitkumar ;
> dri-devel@lists.freedesktop.org
> Cc: intel-...@lists.freedesktop.org
> Subject: RE: [PATCH 4/6] drm/edid: use a temp variable for sads to drop one
> level of dereferences
>
Hi Nirmoy,
On Tue, Sep 26, 2023 at 04:24:01PM +0200, Nirmoy Das wrote:
> PIPE_CONTROL_FLUSH_L3 is not needed for aux invalidation
> so don't set that.
>
> Fixes: 78a6ccd65fa3 ("drm/i915/gt: Ensure memory quiesced before
> invalidation")
> Cc: Jonathan Cavitt
> Cc: Andi Shyti
> Cc: # v5.8+
>
On 9/25/2023 11:26 PM, Stanislaw Gruszka wrote:
Use local variable for debugfs root, just to make further changes
easier.
Signed-off-by: Stanislaw Gruszka
Reviewed-by: Jeffrey Hugo
On 9/26/2023 6:09 AM, Stanislaw Gruszka wrote:
From: Karol Wachowski
Create buffers with cache coherency on the CPU side (write-back) while
disabling snooping on the VPU side. These buffers require an explicit
cache flush after each CPU-side modification.
Configuring pages as write-combined
On 9/25/2023 6:11 AM, Stanislaw Gruszka wrote:
From: Karol Wachowski
Move sequence of masking and unmasking global interrupts from buttress
interrupt handler to generic one that handles both VPUIP and BTRS
interrupts.
Unmasking global interrupts will re-trigger MSI for any pending interrupts.
On 9/25/2023 6:11 AM, Stanislaw Gruszka wrote:
From: Karol Wachowski
Do not enable frequency change interrupt on 40xx as it might
lead to an interrupt storm in current design.
FREQ_CHANGE interrupt is triggered on D0I2 entry which will cause
KMD to check VPU interrupt sources by reading VPUIP
On 9/25/2023 6:11 AM, Stanislaw Gruszka wrote:
From: Karol Wachowski
We need to wait for the CLOCK_RESOURCE_OWN_ACK bit to be set
after configuring the workpoint. This step ensures that the VPU
microcontroller clock is actively toggling and ready for operation.
Previously, we relied solely on
On 9/25/2023 6:11 AM, Stanislaw Gruszka wrote:
From: Jacek Lawrynowicz
Use ivpu_dbg() to print the VPU ready message so it doesn't pollute
the dmesg.
Signed-off-by: Jacek Lawrynowicz
Reviewed-by: Stanislaw Gruszka
Signed-off-by: Stanislaw Gruszka
Reviewed-by: Jeffrey Hugo
On 9/25/2023 6:11 AM, Stanislaw Gruszka wrote:
If we receive signal when waiting for IPC message response in
ivpu_ipc_receive() we return error and continue to operate.
Then the driver can send another IPC messages and re-use occupied
slot of the message still processed by the firmware. This can
On 26/09/2023 16:29, Iddamsetty, Aravind wrote:
On 22-09-2023 19:16, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
At the moment memory region names are a bit too varied and too
inconsistent to be used for ABI purposes, like for upcoming fdinfo
memory stats.
System memory can be either system
On 22-09-2023 19:16, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> At the moment memory region names are a bit too varied and too
> inconsistent to be used for ABI purposes, like for upcoming fdinfo
> memory stats.
>
> System memory can be either system or system-ttm. Local memory has the
On 2023-08-28 20:05, Jessica Zhang wrote:
> Some drivers support hardware that have optimizations for solid fill
> planes. This series aims to expose these capabilities to userspace as
> some compositors have a solid fill flag (ex. SOLID_COLOR in the Android
> hardware composer HAL) that can be
Since commit 00e7e698bff1 ("backlight: pwm_bl: Configure pwm only once
per backlight toggle") calling pwm_backlight_power_off() doesn't disable
the PWM any more. However this is necessary to suspend because PWM
drivers usually refuse to suspend if they are still enabled.
Also adapt shutdown and
Hi Laurent, David, Daniel,
On Tue, Sep 19, 2023 at 5:24 PM Laurent Pinchart
wrote:
> On Tue, Sep 19, 2023 at 04:28:40PM +0200, Geert Uytterhoeven wrote:
> > The following changes since commit 0663e1da5ba8e6459e3555ac12c62741668c0d30:
> >
> > drm/dp_mst: Tune down error message during payload
Hi
Am 26.09.23 um 16:15 schrieb Carlos Eduardo Gallo Filho:
There's duplicated functions on drm that do the same job of calculating
the size of planes from a drm_format_info and the size of its first
plane. So this patchset throw away the more specific version intended
to be used from a given
On Tue, Sep 26, 2023 at 04:18:42PM +0200, Nirmoy Das wrote:
> On MTL GEN12_RING_FAULT_REG is not replicated so don't
> do mcr based operation for this register.
>
> Signed-off-by: Nirmoy Das
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 14 +-
>
On 26/09/2023 11:15, Carlos Eduardo Gallo Filho wrote:
There's duplicated functions on drm that do the same job of calculating
the size of planes from a drm_format_info and the size of its first
plane. So this patchset throw away the more specific version intended
to be used from a given
Hi, all,
On Tue, Sep 26, 2023 at 7:15 PM Linux regression tracking (Thorsten
Leemhuis) wrote:
>
> [CCing the regression list, as it should be in the loop for regressions:
> https://docs.kernel.org/admin-guide/reporting-regressions.html]
>
> Hi, Thorsten here, the Linux kernel's regression
PIPE_CONTROL_FLUSH_L3 is not needed for aux invalidation
so don't set that.
Fixes: 78a6ccd65fa3 ("drm/i915/gt: Ensure memory quiesced before invalidation")
Cc: Jonathan Cavitt
Cc: Andi Shyti
Cc: # v5.8+
Cc: Andrzej Hajda
Cc: Tvrtko Ursulin
Cc: Matt Roper
Cc: Tejas Upadhyay
Cc: Lucas De
On MTL GEN12_RING_FAULT_REG is not replicated so don't
do mcr based operation for this register.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_gt.c | 14 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 11 ++-
3
The functions drm_framebuffer_plane_{width,height} and
fb_plane_{width,height} do exactly the same job of its
equivalents drm_format_info_plane_{width,height} from drm_fourcc.
The only reason to have these functions on drm_framebuffer
would be if they would added a abstraction layer to call it
The drm_format_info_plane_{height,width} functions was implemented using
regular division for the plane size calculation, which cause issues [1][2]
when used on contexts where the dimensions are misaligned with relation
to the subsampling factors. So, replace the regular division by the
There's duplicated functions on drm that do the same job of calculating
the size of planes from a drm_format_info and the size of its first
plane. So this patchset throw away the more specific version intended
to be used from a given framebuffer and make the generic version way
more portable
On Wed, Aug 9, 2023 at 10:53 AM Boris Brezillon
wrote:
>
> Hello,
>
> This is the second version of the kernel driver meant to support new Mali
> GPUs which are delegating the scheduling to a firmware.
[...]
>
> I tried to Cc anyone that was involved in any development of the code
> I picked from
Hi,
On Tue, Sep 26, 2023 at 1:06 AM AngeloGioacchino Del Regno
wrote:
>
> Il 26/09/23 00:00, Douglas Anderson ha scritto:
> > In commit 5f04e7ce392d ("drm/panel-edp: Split eDP panels out of
> > panel-simple") I moved a pile of panels out of panel-simple driver
> > into the newly created
Hi Christian,
On 9/26/2023 6:47 PM, Christian König wrote:
> Am 26.09.23 um 14:56 schrieb Hans de Goede:
>> Hi,
>>
>> On 9/26/23 13:24, Shyam Sundar S K wrote:
>>> Hi Hans,
>>>
>>> On 9/26/2023 4:05 PM, Hans de Goede wrote:
Hi,
On 9/22/23 19:50, Shyam Sundar S K wrote:
> For
Am 26.09.23 um 14:56 schrieb Hans de Goede:
Hi,
On 9/26/23 13:24, Shyam Sundar S K wrote:
Hi Hans,
On 9/26/2023 4:05 PM, Hans de Goede wrote:
Hi,
On 9/22/23 19:50, Shyam Sundar S K wrote:
For the Smart PC Solution to fully work, it has to enact to the actions
coming from TA. Add the
On Mon, Sep 25, 2023 at 02:26:09PM +0200, Flavio Suligoi wrote:
> diff --git a/drivers/video/backlight/mp3309c.c
> b/drivers/video/backlight/mp3309c.c
> new file mode 100644
> index ..923ac7f7b291
> --- /dev/null
> +++ b/drivers/video/backlight/mp3309c.c
> @@ -0,0 +1,398 @@
> ...
>
On 2023-09-26 01:56, Cong Liu wrote:
> This patch fixes a null pointer dereference in the error message that is
> printed when the Display Core (DC) fails to initialize. The original
> message includes the DC version number, which is undefined if the DC is
> not initialized.
>
> Fixes:
On 09/25, Harry Wentland wrote:
>
>
> On 2023-07-21 09:24, Melissa Wen wrote:
> > dc->caps.color.mpc.gamut_remap says there is a post-blending color block
> > for gamut remap matrix for DCN3 HW family and newer versions. However,
> > those drivers still follow DCN10 programming that remap stream
On Mon, Sep 25, 2023 at 02:26:08PM +0200, Flavio Suligoi wrote:
> The Monolithic Power (MPS) MP3309C is a WLED step-up converter, featuring a
> programmable switching frequency to optimize efficiency.
> The brightness can be controlled either by I2C commands (called "analog"
> mode) or by a PWM
On 2023-09-26 08:38, Melissa Wen wrote:
> On 09/25, Harry Wentland wrote:
>>
>>
>> On 2023-09-13 12:43, Melissa Wen wrote:
>>> Logging DCN3 MPC state was following DCN1 implementation that doesn't
>>> consider new DCN3 MPC color blocks. Create new elements according to
>>> DCN3 MPC color caps
On Mon, Sep 25, 2023 at 04:24:25PM -0500, Rob Herring wrote:
> Make it explicit that child nodes have additional properties and the
> child node schema is not complete. The complete schemas are applied
> separately based the compatible strings.
>
> Signed-off-by: Rob Herring
I cross-checked
Hi,
On 9/26/23 13:24, Shyam Sundar S K wrote:
> Hi Hans,
>
> On 9/26/2023 4:05 PM, Hans de Goede wrote:
>> Hi,
>>
>> On 9/22/23 19:50, Shyam Sundar S K wrote:
>>> For the Smart PC Solution to fully work, it has to enact to the actions
>>> coming from TA. Add the initial code path for set
On Mon, Sep 25, 2023 at 04:24:24PM -0500, Rob Herring wrote:
> Just as unevaluatedProperties or additionalProperties are required at
> the top level of schemas, they should (and will) also be required for
> child node schemas. That ensures only documented properties are
> present for any node.
>
On 09/25, Harry Wentland wrote:
>
>
> On 2023-09-13 12:43, Melissa Wen wrote:
> > Hi,
> >
> > This is an update of previous RFC [0] improving the data collection of
> > Gamma Correction and Blend Gamma color blocks.
> >
> > As I mentioned in the last version, I'm updating the color state part
On 09/25, Harry Wentland wrote:
>
>
> On 2023-09-13 12:43, Melissa Wen wrote:
> > Color caps changed between HW versions which caused DCN10 color state
> > sections on DTN log no longer fit DCN3.0 versions. Create a
> > DCN3.0-specific color state logging and hook it to drivers of DCN3.0
> >
Hi,
For coding style and wording part, this version looks fine for me after a brief
skim.
Thanks for the patch. :-)
On 2023/9/26 16:23, Mitul Golani wrote:
This patch series adds support for DSC fractional compressed bpp
for MTL+. The series starts with some fixes, followed by patches that
On 09/25, Harry Wentland wrote:
>
>
> On 2023-09-13 12:43, Melissa Wen wrote:
> > Logging DCN3 MPC state was following DCN1 implementation that doesn't
> > consider new DCN3 MPC color blocks. Create new elements according to
> > DCN3 MPC color caps and a new DCN3-specific function for reading
From: Karol Wachowski
Create buffers with cache coherency on the CPU side (write-back) while
disabling snooping on the VPU side. These buffers require an explicit
cache flush after each CPU-side modification.
Configuring pages as write-combined may introduce significant delays,
potentially
Hi Zack,
kernel test robot noticed the following build errors:
[auto build test ERROR on linus/master]
[also build test ERROR on v6.6-rc3 next-20230926]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented
: 8fff9184d1b5810dca5dd1a02726d4f844af88fc
patch link:
https://lore.kernel.org/r/20230628-topic-a7xx_drmmsm-v5-7-3dc527b472d7%40linaro.org
patch subject: [PATCH v5 07/10] drm/msm/a6xx: Mostly implement A7xx gpu_state
config: sparc-allyesconfig
(https://download.01.org/0day-ci/archive/20230926/202309261932
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