With the recent switch from fbdev-generic to fbdev-dma, the driver now
requires the DRM GEM DMA helpers. This dependency is missing, and will
cause a link failure if fbdev emulation is enabled.
Add the missing dependency.
Fixes: 0992284b4fe4 ("drm/mediatek: Use fbdev-dma")
Signed-off-by: Chen-Yu
On 6/19/24 19:33, Jiri Pirko wrote:
> [You don't often get email from j...@resnulli.us. Learn why this is important
> at https://aka.ms/LearnAboutSenderIdentification ]
>
> Thu, Jun 13, 2024 at 10:21:53AM CEST, oshpigel...@habana.ai wrote:
>> This patch set implements the HabanaLabs network
On 6/19/24 11:12 PM, Jason Gunthorpe wrote:
On Mon, Jun 10, 2024 at 04:55:49PM +0800, Lu Baolu wrote:
The domain_alloc_user operation is currently implemented by allocating a
paging domain using iommu_domain_alloc(). This is because it needs to fully
initialize the domain before return. Add a
On Tue, Jun 18, 2024 at 09:18:15AM +0200, Thomas Hellström wrote:
> Use the LRU walker for eviction. This helps
> removing a lot of code with weird locking
> semantics.
>
> The functionality is slightly changed so that
> when trylocked buffer objects are exhausted, we
> continue to interleave
On Tue, Jun 18, 2024 at 09:18:15AM +0200, Thomas Hellström wrote:
> Use the LRU walker for eviction. This helps
> removing a lot of code with weird locking
> semantics.
>
> The functionality is slightly changed so that
> when trylocked buffer objects are exhausted, we
> continue to interleave
Hi Dave, Sima,
Fixes for 6.10. Two weeks worth.
The following changes since commit 6ba59ff4227927d3a8530fc2973b80e94b54d58f:
Linux 6.10-rc4 (2024-06-16 13:40:16 -0700)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
On 5/22/2024 3:51 AM, Dmitry Baryshkov wrote:
The HDMI driver already has msm_hdmi_hpd_enable() and
msm_hdmi_hpd_disable() functions. Wire them into the
msm_hdmi_bridge_funcs, so that HPD can be enabled and disabled
dynamically rather than always having HPD events generation enabled.
On 5/22/2024 3:51 AM, Dmitry Baryshkov wrote:
The HDMI block needs to be enabled to properly generate HPD events. Make
sure it is not turned off in the disable paths if HPD delivery is enabled.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
dpu_encoder_helper_phys_cleanup() calls the ctl ops without checking if
the ops are assigned causing discrepancy between its callers where the
checks are performed and the API itself which does not.
Two approaches can be taken: either drop the checks even in the caller
OR add the checks even in
Thu, Jun 13, 2024 at 10:21:53AM CEST, oshpigel...@habana.ai wrote:
>This patch set implements the HabanaLabs network drivers for Gaudi2 ASIC
>which is designed for scaling of AI neural networks training.
>The patch set includes the common code which is shared by all Gaudi ASICs
>and the Gaudi2
These drivers don't use the driver_data member of struct i2c_device_id,
so don't explicitly initialize this member.
This prepares putting driver_data in an anonymous union which requires
either no initialization or named designators. But it's also a nice
cleanup on its own.
While add it, also
>+
>+What: /sys/kernel/debug/habanalabs_cn/hbl_cn/nic_disable_decap
>+What: /sys/kernel/debug/habanalabs_cn/hbl_cn/nic_inject_rx_err
>+What: /sys/kernel/debug/habanalabs_cn/hbl_cn/nic_mac_lane_remap
Don't think debugfs is the correct interface for all this
>
>Add common support for AI scaling over the network. Initialize the hbl_cn
>driver via
>auxiliary bus and serve as its adapter for accessing the device.
A 1200 line patch deserves a bit more of info in the commit msg.
Can you please elaborate what network scaling support is being added in
Hello!
Ideas welcome, especially some way to see what graphics is doing.
I'm unsure about the distro you are using but try package intel_gpu_top.
It displays irqs/s and a bunch of other utilization statistics.
Hope this helps.
--
BR,
Gerhard
Hi Jacopo,
Thank you for the patch.
On Wed, Jun 19, 2024 at 12:22:18PM +0200, Jacopo Mondi wrote:
> Add support for R-Car R8A779H0 V4M which has similar characteristics
> as the already supported R-Car V4H R8A779G0, but with a single output
> channel.
>
> Signed-off-by: Jacopo Mondi
>
> ---
>
Hi Jacopo,
Thank you for the patch.
On Wed, Jun 19, 2024 at 12:22:16PM +0200, Jacopo Mondi wrote:
> From: Phong Hoang
>
> Add a check to the register access function when attaching a bridge
> device.
>
> Signed-off-by: Phong Hoang
> Signed-off-by: Jacopo Mondi
Reviewed-by: Laurent Pinchart
Hi Jacopo,
Thank you for the patch.
CC'ing Tomi.
On Wed, Jun 19, 2024 at 12:22:15PM +0200, Jacopo Mondi wrote:
> From: Takeshi Kihara
>
> Version 0.51 of the Renesas R-Car Gen4 TRM reports bit 16 of the
> CLOCKSET1 register of the DSI transmitter module to be a reserved
> field.
>
> Fix this
On 6/13/2024 11:29 AM, Marijn Suijten wrote:
On 2024-06-13 20:05:11, Dmitry Baryshkov wrote:
Rename dpu_hw_setup_vsync_source functions to make the names match the
implementation: on DPU 5.x the TOP only contains timer setup, while 3.x
and 4.x used MDP_VSYNC_SEL register to select TE source.
On 6/13/2024 11:14 AM, Marijn Suijten wrote:
On 2024-06-13 20:05:10, Dmitry Baryshkov wrote:
Make the DPU driver use the TE source specified in the DT. If none is
specified, the driver defaults to the first GPIO (mdp_vsync0).
mdp_vsync_p?
Signed-off-by: Dmitry Baryshkov
---
On 6/13/2024 10:05 AM, Dmitry Baryshkov wrote:
Make the DPU driver use the TE source specified in the DT. If none is
specified, the driver defaults to the first GPIO (mdp_vsync0).
as marijn noted,
mdp_vsync0 ---> mdp_vsyncp
Signed-off-by: Dmitry Baryshkov
With that addressed,
On Wed, Jun 19, 2024 at 07:53:23PM +0300, Ville Syrjälä wrote:
> On Wed, Jun 19, 2024 at 02:38:16PM +0300, Ville Syrjälä wrote:
> > On Wed, Jun 12, 2024 at 11:47:03PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > intel_surf_alignment() in particular has devolved into
> > > a
On 6/13/2024 10:05 AM, Dmitry Baryshkov wrote:
Command mode panels provide TE signal back to the DSI host to signal
that the frame display has completed and update of the image will not
cause tearing. Usually it is connected to the first GPIO with the
mdp_vsync function, which is the default.
On 5/22/2024 3:51 AM, Dmitry Baryshkov wrote:
Supporting simultaneous check of native HPD and the external GPIO proved
to be less stable than just native HPD. Drop the hpd-gpios support,
leaving just the native HPD support. In case the native HPD doesn't work
the user is urged to switch to
Timeouts on the AUX bus are to be expected in certain normal operating
conditions. There is no need to raise an error log or re-initialize the
whole AUX state machine. Simply acknowledge the AUX_ERR interrupt and
let upper layers know about the timeout.
Signed-off-by: Lucas Stach
Reviewed-by:
All AUX error responses raise the AUX_ERR interrupt, so there is no
need to read the AUX status register in normal operation. Only read
the status when an error occurred and we can expect a different
status than OK.
Signed-off-by: Lucas Stach
Reviewed-by: Robert Foss
Tested-by: Heiko Stuebner
The PLL will be reconfigured later, which may cause it to go out of lock
anyway, so there is no point in waiting for the PLL to lock here. Instead
we can continue execution of the link setup, which will properly set the
PLL parameters and will wait for the PLL to lock at the appropriate times.
Move the wait loop into its own function, so it doesn't need to be
replicated in multiple locations. Also move the PLL lock checks between
setting the link bandwidth, which may cause the PLL to unlock, and the
MACRO_RST which needs the PLL to be locked.
Signed-off-by: Lucas Stach
Reviewed-by:
Attached is the revert commit that works for me. Tested with Radeon
6800 and Radeon 7900XTX.
Marek
Marek
On Wed, Jun 19, 2024 at 9:50 AM Thomas Zimmermann wrote:
>
> Hi
>
> Am 13.06.24 um 07:59 schrieb Marek Olšák:
> > Hi Thomas,
> >
> > Commit 9eac534db0013aff9b9124985dab114600df9081 as per
On 6/13/24 10:02, Ben Skeggs wrote:
Signed-off-by: Ben Skeggs
...
+
+MODULE_LICENSE("GPL and additional rights");
+module_init(nvkm_init);
+module_exit(nvkm_exit);
missing MODULE_DESCRIPTION() which will cause a warning with make W=1
Make sure the controller is in a basic working state after runtime
resume. Keep the analog function enable in the mode set path as this
enables parts of the PHY that are only required to be powered when
there is a data stream being sent out.
Signed-off-by: Lucas Stach
Reviewed-by: Robert Foss
This isn't used, but gives the impression of the power on and power off
platform calls being non-symmetrical. Remove the unused callback and
rename the power_on_start to simply power_on.
Signed-off-by: Lucas Stach
Reviewed-by: Robert Foss
Tested-by: Heiko Stuebner (rk3288-veyron and
Platform and PHY power isn't only required when the actual display data
stream is active, but may be required earlier to support AUX channel
transactions. Move them into the runtime PM calls, so they are properly
managed whenever various other parts of the driver need them to be active.
There is no reason to enable the controller clock in driver probe, as
there is no HW initialization done in this function. Instead rely on
either runtime PM to handle the controller clock or statically enable
it in the driver bind routine, after which real hardware access is
required to work.
Now that the clock is handled dynamically through
analogix_dp_resume/suspend and it isn't statically enabled in the
driver probe routine, there is no need for the remove function anymore.
Signed-off-by: Lucas Stach
Reviewed-by: Robert Foss
Tested-by: Heiko Stuebner (rk3288-veyron and
The clock is already managed by runtime PM, which is properly invoked
from the analogix_dp_set_bridge function, so there is no need for an
additional reference.
Signed-off-by: Lucas Stach
Reviewed-by: Robert Foss
Tested-by: Heiko Stuebner (rk3288-veyron and rk3399-gru)
---
Hook up the runtime PM suspend/resume paths to make the rockchip
glue behave more like the exynos one. The same suspend/resume
functions are used for system sleep via the runtime PM force
suspend/resume.
Signed-off-by: Lucas Stach
Reviewed-by: Robert Foss
Reviewed-by: Heiko Stuebner
Tested-by:
This check is way too late in the DP enable flow. The PLL must be
locked much earlier, before any link training can happen. If the
PLL is unlocked at that point in time there is something seriously
wrong in the enable flow.
Signed-off-by: Lucas Stach
Reviewed-by: Robert Foss
Tested-by: Heiko
AUX transactions require the controller to be in working state and
take a runtime PM reference. To avoid potential races beween the
first transactions on the bus and runtime PM being set up, move the
AUX registration behind the runtime PM setup.
Signed-off-by: Lucas Stach
Reviewed-by: Robert
Setting the link bandwidth may change the PLL parameters, which will cause
the PLL to go out of lock, so make sure to apply the MACRO_RST, which
according to the comment is required to be pulsed after the PLL is locked.
Signed-off-by: Lucas Stach
Reviewed-by: Robert Foss
Tested-by: Heiko
On 5/22/2024 3:51 AM, Dmitry Baryshkov wrote:
Expand the HDMI_CFG() macro in HDMI config description. It has no added
value other than hiding some boilerplate declarations.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 16
On 5/22/2024 3:51 AM, Dmitry Baryshkov wrote:
As these clocks are now used in the runtime PM callbacks, they have no
connection to 'HPD'. Rename corresponding fields to follow clocks
purpose, to power up the HDMI controller.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
On 5/22/2024 3:51 AM, Dmitry Baryshkov wrote:
It is completely not obvious, but the so-called 'hpd' clocks and
regulators are required for the HDMI host to function properly. Merge
pwr and hpd regulators. Use regulators, clocks and pinctrl to implement
proper runtime PM callbacks.
From: Hsiao Chien Sung
Support "Pre-multiplied" alpha blending mode on in OVL.
Before this patch, only the "coverage" mode is supported.
Signed-off-by: Hsiao Chien Sung
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 32 +---
1 file changed, 25 insertions(+), 7
From: Hsiao Chien Sung
Support "None" alpha blending mode on MediaTek's chips.
Signed-off-by: Hsiao Chien Sung
---
drivers/gpu/drm/mediatek/mtk_ethdr.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c
From: Hsiao Chien Sung
Support "Pre-multiplied" and "None" blend mode on MediaTek's chips by
adding correct blend mode property when the planes init.
Before this patch, only the "Coverage" mode (default) is supported.
For more information, there are three pixel blend modes in DRM driver:
From: Hsiao Chien Sung
Support "Pre-multiplied" alpha blending mode in Mixer.
Before this patch, only the coverage mode is supported.
Signed-off-by: Hsiao Chien Sung
---
drivers/gpu/drm/mediatek/mtk_ethdr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
Support "Pre-multiplied" and "None" blend mode on MediaTek's chips by
adding correct blend mode property when the planes init.
Before this patch, only the "Coverage" mode (default) is supported.
Signed-off-by: Hsiao Chien Sung
---
Hsiao Chien Sung (5):
drm/mediatek: Support "None" blending
From: Hsiao Chien Sung
Support "None" alpha blending mode on MediaTek's chips.
Reviewed-by: CK Hu
Signed-off-by: Hsiao Chien Sung
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
On 6/18/2024 8:26 PM, Dmitry Baryshkov wrote:
On Wed, 19 Jun 2024 at 01:56, Abhinav Kumar wrote:
On 6/13/2024 4:20 PM, Abhinav Kumar wrote:
On 6/13/2024 3:36 PM, Dmitry Baryshkov wrote:
The dpu_crtc_atomic_check() already calls the function
_dpu_crtc_check_and_setup_lm_bounds(). There is
Hi Dave & Sima -
The main i915 pull request for v6.11. A bit more commits than usual.
Should've started sending periodic PR's earlier to keep it more
manageable. My bad.
Highlights are BMG display, panel replay enabling, and link training
failure fallback for DP MST.
A big chunk of the commit
On Wed, Jun 19, 2024 at 12:27 PM Christian König
wrote:
>
> Am 18.06.24 um 16:12 schrieb Demi Marie Obenour:
> > On Tue, Jun 18, 2024 at 08:33:38AM +0200, Christian König wrote:
> > > Am 18.06.24 um 02:57 schrieb Demi Marie Obenour:
> > >> On Mon, Jun 17, 2024 at 10:46:13PM +0200, Marek
On Wed, Jun 19, 2024 at 12:16:47PM +0300, Sergey Shtylyov wrote:
> On 6/19/24 10:54 AM, Jiapeng Chong wrote:
>
> > The function are defined in the rcar_cmm.c file, but not called
>
>s/are/is/.
>
> > elsewhere, so delete the unused function.
>
>Anywhere, maybe?
I'll fix those.
On Wed, Jun 19, 2024 at 02:38:16PM +0300, Ville Syrjälä wrote:
> On Wed, Jun 12, 2024 at 11:47:03PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > intel_surf_alignment() in particular has devolved into
> > a complete mess. Redesign the code so that we can handle
> > alignment
The caching mode for buffer objects with VRAM as a possible
placement was forced to write-combined, regardless of placement.
However, write-combined system memory is expensive to allocate and
even though it is pooled, the pool is expensive to shrink, since
it involves global CPU TLB flushes.
From: Hsiao Chien Sung
Always add DRM_MODE_ROTATE_0 to rotation property to meet
IGT's (Intel GPU Tools) requirement.
Reviewed-by: CK Hu
Reviewed-by: AngeloGioacchino Del Regno
Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
Signed-off-by: Hsiao Chien Sung
---
From: Hsiao Chien Sung
CONST_BLD must be enabled for XRGB formats although the alpha channel
can be ignored, or OVL will still read the value from memory.
This error only affects CRC generation.
Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
Reviewed-by: CK Hu
From: Hsiao Chien Sung
Set DRM mode configs limitation according to the hardware capabilities
and pass the IGT checks as below:
- The test "graphics.IgtKms.kms_plane" requires a frame buffer with
width of 4512 pixels (> 4096).
- The test "graphics.IgtKms.kms_cursor_crc" checks if the cursor
From: Hsiao Chien Sung
Support RGBA and RGBX formats in OVL on MT8195.
Reviewed-by: CK Hu
Reviewed-by: AngeloGioacchino Del Regno
Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
Signed-off-by: Hsiao Chien Sung
---
From: Hsiao Chien Sung
9-bit alpha (max=0x100) is designed for special HDR related
calculation, which should be disabled by default.
Change the alpha value from 0x100 to 0xff in 8-bit form.
Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
Reviewed-by:
From: Hsiao Chien Sung
Define new color formats to hide the bit operation in the MACROs to make
the switch statement more concise.
Change the MACROs to align the naming rule in DRM.
Reviewed-by: CK Hu
Reviewed-by: AngeloGioacchino Del Regno
Signed-off-by: Hsiao Chien Sung
---
From: Hsiao Chien Sung
Add OVL compatible name for MT8195.
Without this commit, DRM won't work after modifying the device tree.
Reviewed-by: CK Hu
Reviewed-by: AngeloGioacchino Del Regno
Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
Signed-off-by: Hsiao Chien
From: Hsiao Chien Sung
Support more 10bit formats in OVL.
Reviewed-by: CK Hu
Reviewed-by: AngeloGioacchino Del Regno
Signed-off-by: Hsiao Chien Sung
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 32 +---
1 file changed, 29 insertions(+), 3 deletions(-)
diff
From: Hsiao Chien Sung
Set the plane alpha according to DRM plane property.
Reviewed-by: CK Hu
Reviewed-by: AngeloGioacchino Del Regno
Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
Signed-off-by: Hsiao Chien Sung
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c |
Signed-off-by: Hsiao Chien Sung
---
Changes in v3:
- Modify the commit message
- Add a patch to fix destination alpha error in OVL
- Link to v2:
https://lore.kernel.org/all/20240619-mediatek-drm-next-v2-0-abf68f46f...@mediatek.com
---
Changes in v2:
- Seperate the changes that belong to another
From: Hsiao Chien Sung
Set the plane alpha according to DRM plane property.
Reviewed-by: CK Hu
Reviewed-by: AngeloGioacchino Del Regno
Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
Signed-off-by: Hsiao Chien Sung
---
drivers/gpu/drm/mediatek/mtk_ethdr.c | 6
From: Hsiao Chien Sung
The formula of Coverage alpha blending is:
dst.a = dst.a * (0xff - src.a * SCA / 0xff) / 0xff
+ src.a * SCA / 0xff
dst.a: destination alpha
src.a: pixel alpha
SCA : plane alpha
When SCA = 0xff, the formula becomes:
dst.a = dst.a * (0xff - src.a) + src.a
This
From: Hsiao Chien Sung
We found that IGT (Intel GPU Tool) will try to commit layers with
zero width or height and lead to undefined behaviors in hardware.
Disable the layers in such a situation.
Fixes: 453c3364632a ("drm/mediatek: Add ovl_adaptor support for MT8195")
Fixes: d886c0009bd0
From: Hsiao Chien Sung
Fix an issue that plane coordinate was not saved when
calling async update.
Fixes: 920fffcc8912 ("drm/mediatek: update cursors by using async atomic
update")
Reviewed-by: CK Hu
Reviewed-by: AngeloGioacchino Del Regno
Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver
From: Hsiao Chien Sung
Although the alpha channel in XRGB formats can be ignored, ALPHA_CON
must be configured accordingly when using XRGB formats or it will still
affects CRC generation.
Fixes: d886c0009bd0 ("drm/mediatek: Add ETHDR support for MT8195")
Reviewed-by: CK Hu
Reviewed-by:
On Mon, Jun 17, 2024 at 04:13:41PM +0100, Robin Murphy wrote:
> On 23/05/2024 6:52 pm, Rob Clark wrote:
> > From: Rob Clark
> >
> > Add an io-pgtable method to walk the pgtable returning the raw PTEs that
> > would be traversed for a given iova access.
>
> Have to say I'm a little torn here -
On Wed, Jun 19, 2024 at 07:16:20AM +, Omer Shpigelman wrote:
> On 6/18/24 17:19, Andrew Lunn wrote:
> +static u32 hbl_en_get_mtu(struct hbl_aux_dev *aux_dev, u32 port_idx)
> +{
> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev, port_idx);
> + struct net_device
On Tue, Jun 4, 2024 at 10:02 AM Christian König
wrote:
>
> Am 04.06.24 um 12:18 schrieb Huang Rui:
> > On Tue, Jun 04, 2024 at 04:49:34PM +0800, Zhu, Lingshan wrote:
> >> ttm page fault handler ttm_bo_vm_fault_reserved() maps
> >> TTM_BO_VM_NUM_PREFAULT more pages beforehand
> >> due to the
On 17/06/2024 19:14, Jeffrey Hugo wrote:
> On 6/15/2024 5:35 AM, Konrad Dybcio wrote:
>> On 14.06.2024 12:33 PM, Dmitry Baryshkov wrote:
>>> On Fri, Jun 14, 2024 at 01:55:46AM GMT, Konrad Dybcio wrote:
>>
>> [...]
>>
GCC_HDMI_CLKREF_CLK is a child of xo, so you can drop the latter.
On Wed, 19 Jun 2024 at 03:44, Pavel Machek wrote:
>
> Ok, so machine is ready to be thrown out of window, again. Trying to
> play 29C3 video should not make machine completely unusable ... as in
> keyboard looses keystrokes in terminal.
Well, that at least sounds like you can bisect it with a
On Wed, Jun 19, 2024 at 06:49:06PM +0300, Dzmitry Sankouski wrote:
> вт, 18 июн. 2024 г. в 17:08, Mark Brown :
> > On Tue, Jun 18, 2024 at 04:59:52PM +0300, Dzmitry Sankouski wrote:
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * s2dos05.c - Regulator driver for the Samsung
вт, 18 июн. 2024 г. в 17:08, Mark Brown :
>
> On Tue, Jun 18, 2024 at 04:59:52PM +0300, Dzmitry Sankouski wrote:
>
> > index ..3c58a1bd2262
> > --- /dev/null
> > +++ b/drivers/regulator/s2dos05-regulator.c
> > @@ -0,0 +1,362 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + *
> > Does this device require IPv4? What about users and infrastructures that
> > use IPv6 only?
> > IPv4 is legacy at this point.
>
> Gaudi2 supports IPv4 only.
Really? I guess really old stuff, SLIP from 1988 does not support
IPv6, but i don't remember seeing anything from this century which
All the handling for the properties was present, but they
were never attached to the connector to allow userspace
to change them.
Add them to the connector.
Signed-off-by: Dave Stevenson
Reviewed-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_vec.c | 2 ++
1 file changed, 2 insertions(+)
diff
The VEC supports not producing colour bursts for monochrome output.
It also has an option for disabling the chroma input to remove
chroma from the signal.
Now that there is a DRM_MODE_TV_MODE_MONOCHROME defined, plumb
this in.
Signed-off-by: Dave Stevenson
---
drivers/gpu/drm/vc4/vc4_vec.c |
Adds test for the cmdline parser, connector property, and
drm_analog_tv_mode to ensure the behaviour of the new value is
correct.
Signed-off-by: Dave Stevenson
---
.../gpu/drm/tests/drm_cmdline_parser_test.c | 20 ++--
drivers/gpu/drm/tests/drm_connector_test.c| 1 +
Changes since v1:
- (Patch adding DRM_MODE_TV_MODE_MONOCHROME has already been merged)
- Added kunit tests as requested by Maxime
- Fixed error in vc4_vec_connector_get_property which was returning the value
rather than setting *val.
- The legacy driver property has to be updated with the new
On Wed, 19 Jun 2024 07:16:20 + Omer Shpigelman wrote:
> >> Are you referring to get_module_eeprom_by_page()? if so, then it is not
> >> supported by our FW, we read the entire data on device load.
> >> However, I can hide that behind the new API and return only the
> >> requested page if
On Mon, Jun 10, 2024 at 04:55:55PM +0800, Lu Baolu wrote:
> The iommu_domain_alloc() interface is no longer used in the tree anymore.
> Remove it to avoid dead code.
>
> There is increasing demand for supporting multiple IOMMU drivers, and this
> is the last bus-based thing standing in the way of
On Mon, Jun 10, 2024 at 04:55:54PM +0800, Lu Baolu wrote:
> The iommu_present() interface is no longer used in the tree anymore.
> Remove it to avoid dead code.
>
> Signed-off-by: Lu Baolu
> ---
> include/linux/iommu.h | 6 --
> drivers/iommu/iommu.c | 25 -
> 2
On Mon, Jun 10, 2024 at 04:55:52PM +0800, Lu Baolu wrote:
> Commit <421be3ee36a4> ("drm/rockchip: Refactor IOMMU initialisation") has
> refactored rockchip_drm_init_iommu() to pass a device that the domain is
> allocated for. Replace iommu_domain_alloc() with
> iommu_paging_domain_alloc() to
On Mon, Jun 10, 2024 at 04:55:51PM +0800, Lu Baolu wrote:
> Since arm_iommu_create_mapping() now accepts the device, let's replace
> iommu_domain_alloc() with iommu_paging_domain_alloc() to retire the former.
>
> Signed-off-by: Lu Baolu
> ---
> arch/arm/mm/dma-mapping.c | 6 --
> 1 file
On Mon, Jun 10, 2024 at 04:55:49PM +0800, Lu Baolu wrote:
> The domain_alloc_user operation is currently implemented by allocating a
> paging domain using iommu_domain_alloc(). This is because it needs to fully
> initialize the domain before return. Add a helper to do this to avoid using
>
On Wed, Jun 19, 2024 at 09:31:33AM +0200, Thomas Hellström wrote:
> Hi, Matthew.
>
> Thanks for reviewing.
>
> On Tue, 2024-06-18 at 22:11 +, Matthew Brost wrote:
> > On Tue, Jun 18, 2024 at 09:18:13AM +0200, Thomas Hellström wrote:
> >
> > Replying to correct version...
> >
> > > Provide
Il 19/06/24 16:46, amerg...@baylibre.com ha scritto:
From: Nicolas Belin
Add the support of MT6357 PMIC audio codec.
Signed-off-by: Nicolas Belin
Signed-off-by: Alexandre Mergnat
Reviewed-by: AngeloGioacchino Del Regno
Il 19/06/24 16:46, Alexandre Mergnat ha scritto:
Add the sound node which is linked to the MT8365 SoC AFE and
the MT6357 audio codec.
Update the file header.
Signed-off-by: Alexandre Mergnat
Reviewed-by: AngeloGioacchino Del Regno
From: Nicolas Belin
Add a specific soundcard for mt8365-evk. It supports audio jack
in/out, dmics, the amic and lineout.
Signed-off-by: Nicolas Belin
Reviewed-by: AngeloGioacchino Del Regno
Signed-off-by: Alexandre Mergnat
---
sound/soc/mediatek/mt8365/mt8365-mt6357.c | 345
Enable the MediaTek MT8365-EVK sound support.
The audio feature is handled by the MT8365 SoC and
the MT6357 PMIC codec audio.
Reviewed-by: AngeloGioacchino Del Regno
Signed-off-by: Alexandre Mergnat
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Nicolas Belin
Add the support of MT6357 PMIC audio codec.
Signed-off-by: Nicolas Belin
Signed-off-by: Alexandre Mergnat
---
sound/soc/codecs/Kconfig |7 +
sound/soc/codecs/Makefile |2 +
sound/soc/codecs/mt6357.c | 1898 +
Add the sound node which is linked to the MT8365 SoC AFE and
the MT6357 audio codec.
Update the file header.
Signed-off-by: Alexandre Mergnat
---
arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 89 +
1 file changed, 89 insertions(+)
diff --git
Add audio front end support of MT8365 SoC.
Update the file header.
Reviewed-by: AngeloGioacchino Del Regno
Signed-off-by: Alexandre Mergnat
---
arch/arm64/boot/dts/mediatek/mt8365.dtsi | 43 ++--
1 file changed, 41 insertions(+), 2 deletions(-)
diff --git
Add a driver for the Audio Front End (AFE) PCM to provide Audio
Uplink (UL) and Downlink (DL) paths.
Use the ALSA SoC Dynamic Audio Power Management to add widget and
kcontrol supports.
Reviewed-by: AngeloGioacchino Del Regno
Signed-off-by: Alexandre Mergnat
---
- Add specific config to enable:
- MT8365 sound support
- MT6357 audio codec support
- Add the mt8365 directory and all drivers under it.
Reviewed-by: AngeloGioacchino Del Regno
Signed-off-by: Alexandre Mergnat
---
sound/soc/mediatek/Kconfig | 20
Add Digital Micro Device Audio Interface support for MT8365 SoC.
Reviewed-by: AngeloGioacchino Del Regno
Signed-off-by: Alexandre Mergnat
---
sound/soc/mediatek/mt8365/mt8365-dai-dmic.c | 340
1 file changed, 340 insertions(+)
diff --git
Add Pulse Code Modulation Device Audio Interface support for MT8365 SoC.
Reviewed-by: AngeloGioacchino Del Regno
Signed-off-by: Alexandre Mergnat
---
sound/soc/mediatek/mt8365/mt8365-dai-pcm.c | 293 +
1 file changed, 293 insertions(+)
diff --git
1 - 100 of 233 matches
Mail list logo
