le/vgacon.c
@@ -1222,4 +1222,5 @@ void vgacon_register_screen(struct screen_info *si)
vga_si = si;
}
+MODULE_DESCRIPTION("VGA based console driver");
MODULE_LICENSE("GPL");
---
base-commit: 6ba59ff4227927d3a8530fc2973b80e94b54d58f
change-id: 20240621-md-i386-drivers-video-console-ae292c09bb67
orks_cleanup(void)
module_init(agp_serverworks_init);
module_exit(agp_serverworks_cleanup);
+MODULE_DESCRIPTION("Serverworks AGPGART routines");
MODULE_LICENSE("GPL and additional rights");
---
base-commit: 6ba59ff4227927d3a8530fc2973b80e94b54d58f
change-id: 20240621-md-i386-drivers-char-agp-d7221005d737
On 6/21/2024 4:35 PM, Abhinav Kumar wrote:
On 5/19/2024 1:38 AM, Dmitry Baryshkov wrote:
On Fri, May 17, 2024 at 04:37:56PM -0700, Abhinav Kumar wrote:
In preparation to register a iommu fault handler for display
related modules, register a fault handler for the backing
mmu object of msm_k
On 5/20/2024 9:12 PM, Stephen Boyd wrote:
Quoting Abhinav Kumar (2024-05-17 16:37:56)
diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c
index af6a6fcb1173..62c8e6163e81 100644
--- a/drivers/gpu/drm/msm/msm_kms.c
+++ b/drivers/gpu/drm/msm/msm_kms.c
@@ -200,6 +200,28 @@
From: John Harrison
The context switch out workaround requires an extra piece on top.
Also, it applies to more platforms.
Signed-off-by: John Harrison
John Harrison (3):
drm/i915/arl: Enable Wa_14019159160 for ARL
drm/i915/guc: Extend w/a 14019159160
drm/i915/dg2: Enable Wa_14019159160
From: John Harrison
There is a new part to an existing workaround, so enable that piece as
well.
v2: Extend even further.
v3: Drop DG2 as there are CI failures still to resolve. Also re-order
the parameters to a function to reduce excessive line wrapping.
Signed-off-by: John Harrison
---
driv
From: John Harrison
The context switch hold out workaround also applies to DG2.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 3 ++-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/dr
From: John Harrison
The context switch out workaround also applies to ARL.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/
From: John Harrison
The context switch out workaround requires an extra piece on top.
Also, it applies to more platforms.
Signed-off-by: John Harrison
John Harrison (2):
drm/i915/arl: Enable Wa_14019159160 for ARL
drm/i915/guc: Extend w/a 14019159160
drivers/gpu/drm/i915/gt/uc/abi/guc_k
From: John Harrison
There is a new part to an existing workaround, so enable that piece as
well.
v2: Extend even further.
v3: Drop DG2 as there are CI failures still to resolve. Also re-order
the parameters to a function to reduce excessive line wrapping.
Signed-off-by: John Harrison
---
driv
From: John Harrison
The context switch out workaround also applies to ARL.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/
Hi Dzmitry,
kernel test robot noticed the following build errors:
[auto build test ERROR on 6906a84c482f098d31486df8dc98cead21cce2d0]
url:
https://github.com/intel-lab-lkp/linux/commits/Dzmitry-Sankouski/power-supply-add-undervoltage-health-status-property/20240618-222456
base: 6906a84c482
On 5/19/2024 1:38 AM, Dmitry Baryshkov wrote:
On Fri, May 17, 2024 at 04:37:56PM -0700, Abhinav Kumar wrote:
In preparation to register a iommu fault handler for display
related modules, register a fault handler for the backing
mmu object of msm_kms.
Currently, the fault handler only capture
On 5/19/2024 1:31 AM, Dmitry Baryshkov wrote:
On Fri, May 17, 2024 at 04:37:56PM -0700, Abhinav Kumar wrote:
In preparation to register a iommu fault handler for display
related modules, register a fault handler for the backing
mmu object of msm_kms.
Currently, the fault handler only capture
On Thu, Jun 20, 2024 at 03:48:02PM GMT, Chen Ni wrote:
> Add check for the return value of mipi_dsi_dcs_enter_sleep_mode() and
> return the error if it fails in order to catch the error.
>
> Signed-off-by: Chen Ni
> ---
> drivers/gpu/drm/panel/panel-xinpeng-xpp055c272.c | 2 +-
> 1 file changed,
On Thu, Jun 20, 2024 at 03:47:20PM GMT, Chen Ni wrote:
> Add check for the return value of mipi_dsi_dcs_enter_sleep_mode() and
> return the error if it fails in order to catch the error.
>
> Signed-off-by: Chen Ni
> ---
> drivers/gpu/drm/panel/panel-leadtek-ltk050h3146w.c | 2 +-
> 1 file change
The pull request you sent on Sat, 22 Jun 2024 06:41:13 +1000:
> https://gitlab.freedesktop.org/drm/kernel.git tags/drm-fixes-2024-06-22
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/d6c941570680d4d11e5c7480c3bcbeff8d3860f9
Thank you!
--
Deet-doot-dot, I am a bot.
h
On Sat, Jun 8, 2024 at 8:44 AM Kiarash Hajian
wrote:
>
> The driver's memory regions are currently just ioremap()ed, but not
> reserved through a request. That's not a bug, but having the request is
> a little more robust.
>
> Implement the region-request through the corresponding managed
> devres
Hi,
On Fri, Jun 21, 2024 at 1:45 PM Douglas Anderson wrote:
>
> At shutdown if you've got a _properly_ coded DRM modeset driver then
> you'll get these two warnings at shutdown time:
>
> Skipping disable of already disabled panel
> Skipping unprepare of already unprepared panel
>
> These warn
At shutdown if you've got a _properly_ coded DRM modeset driver then
you'll get these two warnings at shutdown time:
Skipping disable of already disabled panel
Skipping unprepare of already unprepared panel
These warnings are ugly and sound concerning, but they're actually a
sign of a properl
Hey Linus,
Still pretty quiet, two weeks worth of amdgpu fixes, with one i915 and
one xe. I didn't get the drm-misc-fixes tree PR this week, but there
was only one fix queued and I think it can way another week, so seems
pretty normal.
Dave.
drm-fixes-2024-06-22:
drm fixes for 6.10-rc5
xe:
- Fi
Hi Dzmitry,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 6906a84c482f098d31486df8dc98cead21cce2d0]
url:
https://github.com/intel-lab-lkp/linux/commits/Dzmitry-Sankouski/power-supply-add-undervoltage-health-status-property/20240618-222456
base: 6906a84
On 6/18/2024 1:15 AM, Hironori KIKUCHI wrote:
The ST7701 supports not only MIPI DSI, but also SPI as an interface
for configuration. To support a panel connected via RGB parallel
interface, add support for SPI using MIPI DBI helpers.
Signed-off-by: Hironori KIKUCHI
---
drivers/gpu/drm/pane
On Mon, Jun 17, 2024 at 9:36 AM Pavel Begunkov wrote:
>
> On 6/13/24 02:35, Mina Almasry wrote:
> >
> > The pages awaiting freeing are stored in the newly added
> > sk->sk_user_frags, and each page passed to userspace is get_page()'d.
> > This reference is dropped once the userspace indicates that
When the DP output is routed to a external connector there is no
need for a fixed panel, as the panel may be detected via EDID on
the AUX channel. Allow to continue probing if no panel reference
is present.
Signed-off-by: Lucas Stach
---
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 2 +-
1
Hi,
On Fri, Jun 21, 2024 at 6:17 AM Tejas Vipin wrote:
>
> Use functions introduced in commit 966e397e4f60 ("drm/mipi-dsi:
> Introduce mipi_dsi_*_write_seq_multi()") and commit f79d6d28d8fe
> ("drm/mipi-dsi: wrap more functions for streamline handling") for the
> asus-z00t-tm5p5-n35596 panel.
>
>
A single IRQ might signal the completion of multiple jobs/fences
at once. There is no point in attaching a new timestamp to each
fence that only differs in when exactly the IRQ handler was able
to process this fence.
Get a single timestamp when the IRQ handler has determined that
there are complet
Since 45ecaea73883 ("drm/sched: Partial revert of 'drm/sched: Keep
s_fence->parent pointer'") still active jobs aren't put back in the
pending list on drm_sched_start(), as they don't have a active
parent fence anymore, so if the GPU is still working and the timeout
is extended, all currently activ
Hi Sui,
On Sun, Apr 28, 2024 at 04:36:50AM +0800, Sui Jingfeng wrote:
> Because the software node backend of the fwnode API framework lacks an
> implementation for the .device_get_match_data function callback. This
> makes it difficult to use(and/or test) a few drivers that originates
> from DT wo
On Fri, 21 Jun 2024 at 18:52, Daniel Vetter wrote:
>
> On Fri, Jun 21, 2024 at 09:40:09AM -0600, Jeffrey Hugo wrote:
> > On 6/21/2024 5:19 AM, Dmitry Baryshkov wrote:
> > > On Fri, 21 Jun 2024 at 09:19, Bjorn Andersson
> > > wrote:
> > > >
> > > > On Wed, Jun 12, 2024 at 09:28:39PM GMT, Dmitry B
Daniel Vetter writes:
Hello Sima,
Thanks for your comment and explanations.
> On Fri, Jun 21, 2024 at 05:42:53PM +0200, Javier Martinez Canillas wrote:
>> Javier Martinez Canillas writes:
>>
>> > Jocelyn Falempe writes:
>> >
>> > Hello Jocelyn, thanks for your feedback!
>> >
>> >> On 21/06/2
Hi,
On Thu, Jun 20, 2024 at 1:05 AM Zhaoxiong Lv
wrote:
>
> @@ -893,6 +901,12 @@ static int jadard_dsi_probe(struct mipi_dsi_device *dsi)
> drm_panel_init(&jadard->panel, dev, &jadard_funcs,
>DRM_MODE_CONNECTOR_DSI);
>
> + ret = of_drm_get_panel_orientation(d
Hi,
On Thu, Jun 20, 2024 at 1:05 AM Zhaoxiong Lv
wrote:
>
> @@ -31,6 +31,15 @@ struct jadard_panel_desc {
> enum mipi_dsi_pixel_format format;
> const struct jadard_init_cmd *init_cmds;
> u32 num_init_cmds;
> + bool lp11_before_reset;
> + bool reset_before_powe
Hi,
On Thu, Jun 20, 2024 at 1:05 AM Zhaoxiong Lv
wrote:
>
> Currently, the init_code of the jd9365da driver is placed
> in the enable() function and sent, but this seems to take
> a long time. It takes 17ms to send each instruction (an init
> code consists of about 200 instructions), so it takes
On Mon, Jun 17, 2024 at 7:17 AM Pavel Begunkov wrote:
>
> On 6/13/24 02:35, Mina Almasry wrote:
> > Convert netmem to be a union of struct page and struct netmem. Overload
> > the LSB of struct netmem* to indicate that it's a net_iov, otherwise
> > it's a page.
> >
> > Currently these entries in s
On 6/20/2024 12:47 AM, Chen Ni wrote:
Add check for the return value of mipi_dsi_dcs_enter_sleep_mode() and
return the error if it fails in order to catch the error.
Signed-off-by: Chen Ni
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/panel/panel-leadtek-ltk050h3146w.c | 2 +-
1 fil
On 6/20/2024 12:48 AM, Chen Ni wrote:
Add check for the return value of mipi_dsi_dcs_enter_sleep_mode() and
return the error if it fails in order to catch the error.
Signed-off-by: Chen Ni
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/panel/panel-xinpeng-xpp055c272.c | 2 +-
1 file
On Tue, Jun 18, 2024 at 12:48:13PM +0300, Dmitry Baryshkov wrote:
> On Tue, 18 Jun 2024 at 12:33, Daniel Vetter wrote:
> >
> > On Mon, Jun 17, 2024 at 10:52:27PM +0300, Dmitry Baryshkov wrote:
> > > On Mon, Jun 17, 2024 at 11:28:35AM GMT, Abhinav Kumar wrote:
> > > > Hi
> > > >
> > > > On 6/17/202
The etnaviv devcoredump is created in the GPU reset path, which
must make forward progress to avoid stalling memory reclaim on
unsignalled dma fences. The currently used __GFP_NORETRY does not
prohibit sleeping on direct reclaim, breaking the forward progress
guarantee. Switch to GFP_NOWAIT, which
The dma sync operation needs to be done with DMA_BIDIRECTIONAL when
the BO is prepared for both read and write operations.
Fixes: a8c21a5451d8 ("drm/etnaviv: add initial etnaviv DRM driver")
Signed-off-by: Lucas Stach
---
v2: switch conditions to be exact matches
---
drivers/gpu/drm/etnaviv/etna
On Fri, Jun 21, 2024 at 10:29:59AM +0800, Yafang Shao wrote:
> To prevent erros from occurring when the src string is longer than the
> dst string in strcpy(), we should use __get_task_comm() instead. This
> approach also facilitates future extensions to the task comm.
>
> Signed-off-by: Yafang Sh
On Fri, Jun 21, 2024 at 05:42:53PM +0200, Javier Martinez Canillas wrote:
> Javier Martinez Canillas writes:
>
> > Jocelyn Falempe writes:
> >
> > Hello Jocelyn, thanks for your feedback!
> >
> >> On 21/06/2024 00:22, Javier Martinez Canillas wrote:
> >>> Add support for the drm_panic infrastruc
On Tue, Jun 18, 2024 at 07:10:58PM -0700, Abhinav Kumar wrote:
>
>
> On 6/18/2024 2:33 AM, Daniel Vetter wrote:
> > On Mon, Jun 17, 2024 at 10:52:27PM +0300, Dmitry Baryshkov wrote:
> > > On Mon, Jun 17, 2024 at 11:28:35AM GMT, Abhinav Kumar wrote:
> > > > Hi
> > > >
> > > > On 6/17/2024 9:54 AM
Hi Dzmitry,
kernel test robot noticed the following build errors:
[auto build test ERROR on 6906a84c482f098d31486df8dc98cead21cce2d0]
url:
https://github.com/intel-lab-lkp/linux/commits/Dzmitry-Sankouski/power-supply-add-undervoltage-health-status-property/20240618-222456
base: 6906a84c482
On Tue, Jun 18, 2024 at 04:49:32PM -0700, Doug Anderson wrote:
> Hi,
>
> On Mon, Jun 17, 2024 at 7:22 AM Daniel Vetter wrote:
> >
> > > I'm really not convinced that hacking with device links in order to
> > > get the shutdown notification in the right order is correct, though.
> > > The idea is
> I see other vendors have debugfs entries for debug configurations or
> settings, not just for dumping debug info.
Did you see any added in the last few years? This is also something
DaveM pushed back on. We want uniform APIs so that all devices look
alike. Please consider what you are exporting
Hi,
On 21/06/2024 06:29, Arunpravin Paneer Selvam wrote:
- Add a new start parameter in trim function to specify exact
address from where to start the trimming. This would help us
in situations like if drivers would like to do address alignment
for specific requirements.
- Add a new fl
On Tue, Jun 18, 2024 at 04:49:22PM -0700, Doug Anderson wrote:
> Hi,
>
> On Mon, Jun 17, 2024 at 7:17 AM Daniel Vetter wrote:
> >
> > > That all being said, I'm also totally OK with any of the following:
> > >
> > > 1. Dropping my patch and just accepting that we will have warnings
> > > printed
Make the default DP port preemphasis configurable via new DT property
"toshiba,pre-emphasis". This is useful in case the DP link properties
are known and starting link training from preemphasis setting of 0 dB
is not useful. The preemphasis can be set separately for both DP lanes
in range 0=0dB, 1=
Document default DP port preemphasis configurable via new DT property
"toshiba,pre-emphasis". This is useful in case the DP link properties
are known and starting link training from preemphasis setting of 0 dB
is not useful. The preemphasis can be set separately for both DP lanes
in range 0=0dB, 1=
The MIPI_DSI_CLOCK_NON_CONTINUOUS causes visible artifacts in high
resolution modes, disable it. Namely, in DSI->DP mode 1920x1200 24
bpp 59.95 Hz, with DSI bus at maximum 1 Gbps per lane setting, the
image contains jittering empty lines.
Signed-off-by: Marek Vasut
---
Cc: Andrzej Hajda
Cc: Dani
The only information in the datasheet regarding this divider is a note
in SYS_PLLPARAM register documentation which states that when LSCLK is
270 MHz, LSCLK_DIV should be 1. What should LSCLK_DIV be set to when
LSCLK is 162 MHz (for DP 1.62G mode) is unclear, but empirical test
confirms using LSCLK
This line_pixel_subtract is no longer needed now that the bridge can
request and obtain specific pixel clock on input to the bridge, with
clock frequency that matches the Pixel PLL frequency.
The line_pixel_subtract is now always 0, so drop it entirely.
The line_pixel_subtract was not reliable as
This reverts commit 01338bb82fed40a6a234c2b36a92367c8671adf0.
With clock improvements in place, this seems to be no longer
necessary. Set the CLRSIPO to default setting recommended by
manufacturer.
Signed-off-by: Marek Vasut
---
Cc: Andrzej Hajda
Cc: Daniel Vetter
Cc: David Airlie
Cc: Jernej
Use tc_pxl_pll_calc() to find out the exact clock frequency generated by the
Pixel PLL. Use the Pixel PLL frequency as adjusted_mode clock frequency and
pass it down the display pipeline to obtain exactly this frequency on input
into this bridge.
The precise input frequency that matches the Pixel
Split tc_pxl_pll_en() into tc_pxl_pll_calc() which does only Pixel PLL
parameter calculation and tc_pxl_pll_en() which calls tc_pxl_pll_calc()
and then configures the Pixel PLL register.
This is a preparatory patch for further rework, where tc_pxl_pll_calc()
will also be used to find out the exact
On Fri, Jun 21, 2024 at 09:40:09AM -0600, Jeffrey Hugo wrote:
> On 6/21/2024 5:19 AM, Dmitry Baryshkov wrote:
> > On Fri, 21 Jun 2024 at 09:19, Bjorn Andersson wrote:
> > >
> > > On Wed, Jun 12, 2024 at 09:28:39PM GMT, Dmitry Baryshkov wrote:
> > > > On Wed, Jun 12, 2024 at 12:17:28PM +0530, Ekan
Hi Christian,
On 6/21/2024 4:54 PM, Christian König wrote:
Am 20.06.24 um 18:01 schrieb Nirmoy Das:
Currently ttm pool is not honoring TTM_TT_FLAG_ZERO_ALLOC flag and
clearing pages on free. It does help with allocation latency but
clearing
happens even if drm driver doesn't passes the flag.
Javier Martinez Canillas writes:
> Jocelyn Falempe writes:
>
> Hello Jocelyn, thanks for your feedback!
>
>> On 21/06/2024 00:22, Javier Martinez Canillas wrote:
>>> Add support for the drm_panic infrastructure, which allows to display
>>> a user friendly message on the screen when a Linux kerne
On 6/21/2024 5:19 AM, Dmitry Baryshkov wrote:
On Fri, 21 Jun 2024 at 09:19, Bjorn Andersson wrote:
On Wed, Jun 12, 2024 at 09:28:39PM GMT, Dmitry Baryshkov wrote:
On Wed, Jun 12, 2024 at 12:17:28PM +0530, Ekansh Gupta wrote:
Move fastrpc.c from misc/ to misc/fastrpc/. New C files are planned
On 6/21/24 12:32 PM, Alexander Stein wrote:
Hi,
skipping the parts where I would simply write "OK" ...
As FVUEN is cleared at the next VSYNC event I suspect the DSI timings
are (slightly) off, but unfortunately I don't have equipment to check
DSI signal quality/timings.
As long as the LCDIFv
Hi, Alexandre:
於 2024年5月23日 週四 下午8:49寫道：
>
> From: Fabien Parent
>
> Add DRM support for MT8365 SoC.
>
> Signed-off-by: Fabien Parent
> Reviewed-by: AngeloGioacchino Del Regno
>
> Signed-off-by: Alexandre Mergnat
> ---
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8
> 1 file changed,
From: Dom Cobley
Trying to read /sys/kernel/debug/dri/1/hdmi1_regs
when the hdmi is disconnected results in a fatal system hang.
This is due to the pm suspend code disabling the dvp clock.
That is just a gate of the 108MHz clock in DVP_HT_RPI_MISC_CONFIG,
which results in accesses hanging AXI bu
From: Maxime Ripard
With the introduction of the BCM2712 support, we will get yet another
generation of display engine to support.
The binary check of whether it's VC5 or not thus doesn't work anymore,
especially since some parts of the driver will have changed with BCM2711,
and some others with
The gamma block has changed in 2711, therefore writing the lut
in vc4_hvs_lut_load is incorrect.
Whilst the gamma property isn't created for 2711, it is called
from vc4_hvs_init_channel, so abort if attempted.
Fixes: c54619b0bfb3 ("drm/vc4: Add support for the BCM2711 HVS5")
Signed-off-by: Dave S
From: Maxime Ripard
Since the BCM2712 will feature a significantly different HVS, let's move
the hardware initialisation part of our bind function into a separate
function.
That way, it will be easier to extend in the future.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Stevenson
---
dri
The debug function to display the dlists didn't reset next_entry_start
when starting each display, so resulting in not stopping the
list at the correct place.
Fixes: c6dac00340fc ("drm/vc4: hvs: Add debugfs node that dumps the current
display lists")
Signed-off-by: Dave Stevenson
---
drivers/gp
The debugfs function to dump dlists aborted at 256 bytes,
when actually the dlist memory is generally significantly
larger but varies based on SoC.
We already have the correct limit in __vc4_hvs_alloc, so
store it for use in the debugfs dlist function.
Fixes: c6dac00340fc ("drm/vc4: hvs: Add debu
From: Dom Cobley
We regularly get dmesg error reports of:
[ 18.184066] hdmi-audio-codec hdmi-audio-codec.3.auto: ASoC: error at
snd_soc_dai_startup on i2s-hifi: -19
[ 18.184098] MAI: soc_pcm_open() failed (-19)
These are generated for any disconnected hdmi interface when pulseaudio
attempt
From: Maxime Ripard
We access multiple times the vc4_crtc_state->assigned_channel variable
in the vc4_crtc_get_scanout_position() function, so let's store it in a
local variable.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Stevenson
---
drivers/gpu/drm/vc4/vc4_crtc.c | 7 ---
1 file
It has been observed that a YUV422 unity scaled plane isn't displayed.
Enabling vertical scaling on the UV planes solves this. There is
already a similar clause to always enable horizontal scaling on the
UV planes.
Signed-off-by: Dave Stevenson
---
drivers/gpu/drm/vc4/vc4_plane.c | 6 ++
1 f
From: Maxime Ripard
Just like the HVS itself, the COB parameters will be fairly different in
the BCM2712.
Let's move the COB parameters computation and its initialisation to a
separate function that will be easier to extend in the future.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Steven
From: Maxime Ripard
The VC4 HDMI driver has a bunch of accessors to read from a register.
The read accessor was warning when accessing an unknown register, but
the write one was just returning silently.
Let's make sure we warn also when writing to an unknown register.
Signed-off-by: Maxime Ripa
From: Maxime Ripard
The BCM2712 will have a fairly different dlist, that will feature one
Pointer 0 word for each plane.
Let's prepare by changing the ptr0_offset variable that holds the offset
in a dlist of the pointer 0 word to an array.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Steve
From: Tim Gover
Always enable SCALER_CONTROL before attempting other HVS
operations. It's safe to write to some parts of the HVS but
in general it's dangerous to do this because it can cause bus
lockups.
Signed-off-by: Tim Gover
Signed-off-by: Dave Stevenson
---
drivers/gpu/drm/vc4/vc4_hvs.c
From: Maxime Ripard
The HVS register set has been heavily modified in the BCM2712, and we'll
thus need a separate debugfs_reg32 array for it.
The name hvs_regs is thus a bit too generic, so let's rename it to
something more specific.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Stevenson
From: Dom Cobley
ABORT_ON_EMPTY chooses whether the HVS abandons the current frame
when it experiences an underflow, or attempts to continue.
In theory the frame should be black from the point of underflow,
compared to a shift of sebsequent pixels to the left.
Unfortunately it seems to put the
From: Maxime Ripard
With the introduction of the support for BCM2712, the check of whether
we're running on vc5 or not to compute the LBM alignment requirement
doesn't work anymore.
Moreover, the LBM size will need to be computed in words for the
BCM2712, while we've had sizes in bytes so far.
The offset fields in vc4_plane_state are described as being
the offset for each buffer in the bo, however it is used to
store the complete DMA address that is then written into the
register.
The DMA address including the fb ofset can be retrieved
using drm_fb_dma_get_gem_addr, and the offset adjus
From: Maxime Ripard
The BCM2712 HVS has registers to report the size of the various SRAM the
driver uses, and their size actually differ depending on the stepping.
The initialisation of the memory pools happen in the __vc4_hvs_alloc()
function that also allocates the main HVS structure, that wil
From: Maxime Ripard
Since we'll support BCM2712 soon, let's move the logic behind
vc4_hvs_get_fifo_from_output() to a switch to extend it more easily.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Stevenson
---
drivers/gpu/drm/vc4/vc4_hvs.c | 77 +++
1 file
From: Dom Cobley
Now we wait for write responses and have a burst
size of 4, we can set the fifo threshold much higher.
Set it to 28 (of the 32 entry size) to keep fifo
fuller and reduce chance of underflow.
Signed-off-by: Dom Cobley
Signed-off-by: Dave Stevenson
---
drivers/gpu/drm/vc4/vc4_
When factoring out __vc4_hvs_stop_channel, the logic got inverted from
if (condition)
// stop channel
to
if (condition)
goto out
//stop channel
out:
and also changed the exact register writes used to stop the channel.
Correct the logic so that th
From: Maxime Ripard
The V3D IP has been separate since BCM2711, so let's make sure we issue
a WARN if we're running not only on BCM2711, but also anything newer.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Stevenson
---
drivers/gpu/drm/vc4/vc4_bo.c | 28 +++-
From: Maxime Ripard
LBM allocations need a different size depending on the line length,
format, etc.
This can get tricky, and fail. Let's add some more prints to ease the
debugging when it does.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Stevenson
---
drivers/gpu/drm/vc4/vc4_plane.c |
From: Dom Cobley
Support displaying DRM_FORMAT_YUV444 and DRM_FORMAT_YVU444 formats.
Tested with kmstest and kodi. e.g.
kmstest -r 1920x1080@60 -f 400x300-YU24
Note: without the shift of width, only half the chroma is fetched,
resulting in correct left half of image and corrupt colours on right
The HVS can change AXI request mode based on how full the COB
FIFOs are.
Until now the vc4 driver has been relying on the firmware to
have set these to sensible values.
With HVS channel 2 now being used for live video, change the
panic mode for all channels to be explicitly set by the driver,
and
From: Maxime Ripard
DLIST generation can get pretty tricky and there's not a lot of debug in
the driver to help. Let's add a few more to track the generated DLIST
size.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Stevenson
---
drivers/gpu/drm/vc4/vc4_hvs.c | 14 --
1 file cha
From: Maxime Ripard
The vc4_plane_atomic_check() directly returns the result of the final
function it calls.
Using the already defined ret variable to check its content on error,
and a separate return 0 on success, makes it easier to extend.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Ste
When the margins are changed, the dlist needs to be regenerated
with the changed updated dest regions for each of the planes.
Setting the zpos_changed flag is sufficient to trigger that
without doing a full modeset, therefore set it should the
margins be changed.
Signed-off-by: Dave Stevenson
--
From: Maxime Ripard
We need to allocate a few additional structures when checking our
atomic_state, especially related to hardware SRAM that will hold the
plane descriptors (DLIST) and the current line context (LBM) during
composition.
Since those allocation can fail, let's add some error messag
From: Dom Cobley
Apply fractional source co-ordinates into the scaling filters.
Signed-off-by: Dom Cobley
Signed-off-by: Dave Stevenson
---
drivers/gpu/drm/vc4/vc4_plane.c | 87 -
1 file changed, 76 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/v
From: Dom Cobley
Fractional source co-ordinates can be used to setup the scaling
filters, so retain the information.
Signed-off-by: Dom Cobley
Signed-off-by: Dave Stevenson
---
drivers/gpu/drm/vc4/vc4_drv.h | 2 +-
drivers/gpu/drm/vc4/vc4_plane.c | 68 -
2 f
Hi
This set is a number of minor fixes that we've had downstream for a while,
and then lays down the some infrastructure changes to facilitate adding support
of BCM2712. I'm just finalising those patches so they should follow on fairly
soon.
Thanks
Dave
---
v1 -> v2
- Sorted Maxime's email ad
On 21/06/2024 12:59, Hironori KIKUCHI wrote:
> Hello Krzysztof,
>
> Thank you for your reply!
>
> On Tue, Jun 18, 2024 at 6:17 PM Krzysztof Kozlowski wrote:
>>
>> On 18/06/2024 10:15, Hironori KIKUCHI wrote:
>>> The RG28XX panel is a panel specific to the Anbernic RG28XX.
>>> It is 2.8 inches in
Hi, Alexandre:
於 2024年5月23日 週四 下午8:49寫道：
>
> From: Fabien Parent
>
> DPI is part of the display / multimedia block in MediaTek SoCs, and
> always have a power-domain (at least in the upstream device-trees).
> Add the power-domains property to the binding documentation.
I've tired to apply this
On 19/06/2024 16:46, Alexandre Mergnat wrote:
> Add the audio codec sub-device. This sub-device is used to set the
> optional voltage values according to the hardware.
> The properties are:
> - Setup of microphone bias voltage.
> - Setup of the speaker pin pull-down.
>
> Also, add the audio po
On Wed, Jun 19, 2024 at 04:46:48PM +0200, amerg...@baylibre.com wrote:
> From: Nicolas Belin
>
> Add the support of MT6357 PMIC audio codec.
This breaks an x86 allmodconfig build:
/build/stage/linux/sound/soc/codecs/mt6357.c: In function ‘mt_delay_250_event’:
/build/stage/linux/sound/soc/codecs
Hi Raphaël,
Thanks for your patch, it will not merged due to a new clock management.
Philippe,
this patch will be replaced by another which manages all clocks that the
display controller
will need (pixel clock, bus clock reference clock).
Best regards
Le 26/02/2024 à 11:48, Raphael Gall
Am 20.06.24 um 18:01 schrieb Nirmoy Das:
Currently ttm pool is not honoring TTM_TT_FLAG_ZERO_ALLOC flag and
clearing pages on free. It does help with allocation latency but clearing
happens even if drm driver doesn't passes the flag. If clear on free
is needed then a new flag can be added for tha
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