There are two kinds of MediaTek DPI devices in the tree: the ones with a
power domain and those without (or missing). The former are the majority
and are more common in newer DTs. Only three older DTs fall into the
latter category: MT2701, MT7623 and MT8192.
However, the current binding only allow
Hi Jyothi,
kernel test robot noticed the following build errors:
[auto build test ERROR on 55bcd2e0d04c1171d382badef1def1fd04ef66c5]
url:
https://github.com/intel-lab-lkp/linux/commits/Jyothi-Kumar-Seerapu/dt-bindings-dmaengine-qcom-gpi-Add-additional-arg-to-dma-cell-property/20241015-202637
On Tue, 15 Oct 2024 at 09:27, Liu Ying wrote:
>
> On 10/14/2024, Dmitry Baryshkov wrote:
> > On Mon, Oct 14, 2024 at 01:33:44PM +0800, Liu Ying wrote:
> >> On 10/14/2024, Dmitry Baryshkov wrote:
> >>> On Sat, Oct 12, 2024 at 05:14:13PM +0800, Liu Ying wrote:
> On 10/12/2024, Dmitry Baryshkov
On 10/17/2024 8:58 AM, Jacek Lawrynowicz wrote:
From: Karol Wachowski
Secondary preemption buffer is accessible by NPU's DMA and can be
allocated with addresses above 4 GB. Move secondary preemption buffer
allocation from SHAVE range which is much smaller (2GB) to DMA range.
This allows to allo
Although the interlace_allowed and ycbcr_420_allowed flags are a part of
the struct drm_connector rather than struct drm_connector_state, still
include them into state dump in order to ease debugging of the setup
issues.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/drm_atomic.c | 2 ++
1
On Mon, Oct 14, 2024 at 03:19:42PM +0530, Manikandan Muralidharan wrote:
> From: Cyrille Pitchen
>
> On SoCs, like the SAM9X75, which embed the XLCDC ip, the registers that
> configure the unified scaling engine were not filled with proper values.
>
> Indeed, for YCbCr formats, the VXSCFACT bitf
On Tue, 15 Oct 2024 19:05:42 -0400, Alex Lanzano wrote:
> This patch series add support for the monochrome Sharp Memory LCD
> panels. This series is based off of the work done by Mehdi Djait.
>
> References:
> https://lore.kernel.org/dri-devel/71a9dbf4609dbba46026a31f60261830163a0b99.1701267411.gi
Use new drm_bridge_connector_mode_valid() helper if there is a HDMI
bridge in the bridge chain. This removes the need to perform TMDS char
rate check manually in the bridge driver.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_bridge_connector.c | 16 +++-
1 file ch
Use new drm_hdmi_connector_mode_valid() helper instead of a
module-specific copy.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
b/drivers/gpu/drm/
On 10/17/2024 8:58 AM, Jacek Lawrynowicz wrote:
From: Karol Wachowski
Do not allocate preemption buffers when Mid Inference Preemption (MIP)
is disabled through test mode.
Rename IVPU_TEST_MODE_PREEMPTION_DISABLE to IVPU_TEST_MODE_MIP_DISABLE
to better describe that this test mode only disable
Hi Jyothi,
kernel test robot noticed the following build errors:
[auto build test ERROR on 55bcd2e0d04c1171d382badef1def1fd04ef66c5]
url:
https://github.com/intel-lab-lkp/linux/commits/Jyothi-Kumar-Seerapu/dt-bindings-dmaengine-qcom-gpi-Add-additional-arg-to-dma-cell-property/20241015-202637
On 10/17/2024 8:58 AM, Jacek Lawrynowicz wrote:
From: Karol Wachowski
Increase DMA address range to:
* 128 GB on 37xx (due to MMU limitations)
* 256 GB on other generations
Merge User and DMA ranges on 40xx and above as it is possible
to access whole 256 GBs from both FW and DMA.
Increase
On 10/17/2024 8:58 AM, Jacek Lawrynowicz wrote:
From: Maciej Falkowski
Add CONFIG_DRM_ACCEL_IVPU_DEBUG option that:
- Adds -DDEBUG that enables printk regardless of the kernel config
- Enables unsafe module params (that are now disabled by default)
Signed-off-by: Maciej Falkowski
Reviewed
On 10/17/2024 8:58 AM, Jacek Lawrynowicz wrote:
From: Karol Wachowski
Use XArray for dynamic command queue ID allocations instead of fixed
ones. This is required by upcoming changes to UAPI that will allow to
manage command queues by user space instead of having predefined number
of queues in a
On 10/17/2024 8:58 AM, Jacek Lawrynowicz wrote:
From: Karol Wachowski
Remove custom ivpu_id_alloc() wrapper used for ID allocations
and replace it with standard xa_alloc_cyclic() API.
The idea behind ivpu_id_alloc() was to have monotonic IDs, so the driver
is easier to debug because same IDs a
On 10/17/2024 8:58 AM, Jacek Lawrynowicz wrote:
From: Karol Wachowski
Don't leave a context descriptor in case CFGI_ALL flush fails.
Mark it as invalid (by clearing valid bit) so nothing is left in
partially-initialized state.
Signed-off-by: Karol Wachowski
Reviewed-by: Jacek Lawrynowicz
Sig
On 10/17/2024 8:58 AM, Jacek Lawrynowicz wrote:
From: Andrzej Kacprowski
Copy engine was deprecated by the FW and is no longer supported.
Compute engine includes all copy engine functionality and should be used
instead.
This change does not affect user space as the copy engine was never
used o
On 10/17/2024 8:58 AM, Jacek Lawrynowicz wrote:
From: Karol Wachowski
Defer root page table allocation and unify context init/fini functions.
Move allocation of the root page table from the file_priv_open function to
perform a lazy allocation approach during ivpu_bo_pin().
By doing so, we avoi
On 10/17/2024 8:58 AM, Jacek Lawrynowicz wrote:
From: Karol Wachowski
Allow TILE_FUSE register to disable more than 1 tile.
The driver should not prevent such configurations from being functional.
Signed-off-by: Karol Wachowski
Reviewed-by: Jacek Lawrynowicz
Signed-off-by: Jacek Lawrynowicz
On Fri, 2024-09-13 at 09:03 +0200, Jocelyn Falempe wrote:
> Add drm_panic support, for nv50+ cards.
> It's enough to get the panic screen while running Gnome/Wayland on a
> GTX 1650.
> It doesn't support multi-plane or compressed format.
> Support for other formats and older cards will come later.
Follow the interlace_allowed example and calculate drm_connector's
ycbcr_420_allowed flag as AND of all drm_bridge's ycbcr_420_allowed
flags in a chain. This is one of the gaps between several
bridge-specific connector implementations and drm_bridge_connector.
Signed-off-by: Dmitry Baryshkov
---
Set the drm_bridge's ycbcr_420_allowed flag if the YCbCr 420 output is
supported by the hardware.
Cc: Alexander Stein
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
b
Instead of forcing the ycbcr_420_allowed flag to be set on the created
drm_connector, set it on the drm_bridge instance and allow
drm_bridge_connecgtor to propagate it to the drm_connector.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_display.c | 4 ++--
drivers/gpu/drm/msm/dp/
As both aux bridges are merely passthrough bridges, mark them as
supporting interlaced and YCbCr 420 data. Other bridges in the chain
still might limit interlaced and YCbCr 420 data support on the
corresponding connector.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/aux-bridge.c
Allow YCbCr 420 output for HDMI and DisplayPort connectors. Other
bridges in the chain still might limit YCbCr 420 support on the
corresponding connector.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/display-connector.c | 4
1 file changed, 4 insertions(+)
diff --git a/driver
sertions(+), 13 deletions(-)
---
base-commit: 7f796de9da37b78e05edde94ebc7e3f9ee53b3b4
change-id: 20241018-bridge-yuv420-aab94d4575de
Best regards,
--
Dmitry Baryshkov
Non-contiguous mapping of BO in VRAM doesn't work, use ttm_bo_access
instead.
Fixes: 0eb2a18a8fad ("drm/xe: Implement VM snapshot support for BO's and
userptr")
Suggested-by: Matthew Auld
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/xe/xe_vm.c | 17 ++---
1 file changed, 6 inse
Non-contiguous VRAM cannot easily be mapped in TTM nor can non-visible
VRAM easily be accessed. Add xe_ttm_access_memory which hooks into
ttm_bo_access to access such memory.
Reported-by: Christoph Manszewski
Suggested-by: Thomas Hellström
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/xe/xe
On Wed, Oct 16, 2024 at 02:03:02PM +0200, Peter Zijlstra wrote:
On Mon, Oct 14, 2024 at 09:25:19PM +0200, Peter Zijlstra wrote:
Let me ponder that a little bit.
So I did the thing on top of the get/put thing that would allow you to
get rid of the ->closed thing, and before I was finished I al
On 10/11/2024 5:12 PM, Lizhi Hou wrote:
Add GET_INFO ioctl to retrieve hardware information, including
AIE, clock, hardware context etc.
Co-developed-by: Min Ma
Signed-off-by: Min Ma
Signed-off-by: Lizhi Hou
Reviewed-by: Jeffrey Hugo
Non-contiguous VRAM cannot easily be mapped in TTM nor can non-visible
VRAM easily be accessed. Add ttm_bo_access, which is similar to
ttm_bo_vm_access, to access such memory.
Reported-by: Christoph Manszewski
Suggested-by: Thomas Hellström
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/ttm/
On 10/18/24 14:01, Jeffrey Hugo wrote:
On 10/11/2024 5:12 PM, Lizhi Hou wrote:
When there is a hardware error, the NPU firmware notifies the host
through
a mailbox message. The message includes details of the error, such as
the
tile and column indexes where the error occurred.
The driver st
Non-contiguous mapping of BO in VRAM doesn't work, use ttm_bo_access
instead.
v2:
- Fix error handling
Fixes: 0eb2a18a8fad ("drm/xe: Implement VM snapshot support for BO's and
userptr")
Suggested-by: Matthew Auld
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/xe/xe_vm.c | 18 +++---
Mapping a non-contiguous VRAM BO doesn't work, start to fix this.
A follow up series should cleanup any remaining mapping of
non-contiguous VRAM BOs, add non-visible access support to
xe_ttm_access_memory, and warn / error on mapping a BO which cannot be
mapped.
v2:
- Include missing local chang
Mapping a non-contiguous VRAM BO doesn't work, start to fix this.
A follow up series should cleanup any remaining mapping of
non-contiguous VRAM BOs, add non-visible access support to
xe_ttm_access_memory, and warn / error on mapping a BO which cannot be
mapped.
Matthew Brost (3):
drm/ttm: Add
Non-contiguous VRAM cannot easily be mapped in TTM nor can non-visible
VRAM easily be accessed. Add xe_ttm_access_memory which hooks into
ttm_bo_access to access such memory.
Reported-by: Christoph Manszewski
Suggested-by: Thomas Hellström
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/xe/xe
Non-contiguous VRAM cannot easily be mapped in TTM nor can non-visible
VRAM easily be accessed. Add ttm_bo_access, which is similar to
ttm_bo_vm_access, to access such memory.
Reported-by: Christoph Manszewski
Suggested-by: Thomas Hellström
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/ttm/
The MSM HDMI driver supports interlaced modes. Set the corresponding
flag to allow interlaced modes on the corresponding connectors.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge
On Fri, Oct 18, 2024 at 1:56 PM André Almeida wrote:
>
> Em 18/10/2024 12:31, Alex Deucher escreveu:
> > On Fri, Oct 18, 2024 at 11:23 AM Rodrigo Vivi
> > wrote:
> >>
> >> On Thu, Oct 17, 2024 at 04:16:09PM -0300, André Almeida wrote:
> >>> Hi Raag,
> >>>
> >>> Em 30/09/2024 04:38, Raag Jadav es
A userspace may create a userspace managed surface but not destroy it,
add hw_destroy function for userspace surfaces so that vmwgfx records the
destroy command and submits it when the userspace context is destroyed.
Signed-off-by: Maaz Mombasawala
---
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h |
Older HW versions of the svga device will only support older versions of
DefineGBSurface command.
Allow userspace to submit v3 and v2 of the DefineGBSurface command for
userspace managed surfaces. The first version of the command is not
supported since it is only used for pre-dx hardware.
Signed-o
The kernel currently exposes both mobs and surfaces to userspace through
ioctls. We would like to move to a model where kernel would only expose
mobs and have userspace manage surfaces. This would simplify kernel paths
for surfaces since these userspace managed surfaces will not support prime
trans
On 10/11/2024 5:12 PM, Lizhi Hou wrote:
When there is a hardware error, the NPU firmware notifies the host through
a mailbox message. The message includes details of the error, such as the
tile and column indexes where the error occurred.
The driver starts a thread to handle the NPU error messag
This series introduces basic support for userspace managed surfaces. The
lifetime and id's of these surfaces is managed by userspace submitted
commands instead of relying on the kernel to manage them.
v2: Add flag for userspace to check userspace surface support.
Maaz Mombasawala (3):
drm/vmwgf
On 10/11/2024 5:12 PM, Lizhi Hou wrote:
AMD AI Engine forms the core of AMD NPU and can be used for accelerating
machine learning applications.
Add the driver to support AI Engine integrated to AMD CPU.
Only very basic functionalities are added.
- module and PCI device initialization
- fir
During GuC reset prepare, interrupt disabled before hardware reset.
Add disable ct to prevent unnecessary message processing.
Signed-off-by: Zhanjun Dong
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 3 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 ++
2 files changed, 5 in
During GuC reset prepare, interrupt disabled before hardware reset.
Add disable ct to prevent unnecessary message processing.
Signed-off-by: Zhanjun Dong
Zhanjun Dong (1):
drm/i915/guc: Disable ct during GuC reset
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 3 +++
drivers/gpu/drm/i91
On 10/11/2024 5:12 PM, Lizhi Hou wrote:
Implement PCI power management suspend and resume callbacks.
Co-developed-by: Narendra Gutta
Signed-off-by: Narendra Gutta
Co-developed-by: Xiaoming Ren
Signed-off-by: Xiaoming Ren
Co-developed-by: Min Ma
Signed-off-by: Min Ma
Signed-off-by: Lizhi Hou
Re
On 10/11/2024 5:12 PM, Lizhi Hou wrote:
There different types of BOs are supported:
- shmem
A user application uses shmem BOs as input/output for its workload running
on NPU.
- device memory heap
The fixed size buffer dedicated to the device.
- device buffer
The buffer object allocated from de
On 10/11/2024 5:12 PM, Lizhi Hou wrote:
The hardware can be shared among multiple user applications. The
hardware resources are allocated/freed based on the request from
user application via driver IOCTLs.
DRM_IOCTL_AMDXDNA_CREATE_HWCTX
Allocate tile columns and create a hardware context structu
On 10/17/2024 8:49 AM, Jacek Lawrynowicz wrote:
From: Andrzej Kacprowski
The NOC firewall interrupt means that the HW prevented
unauthorized access to a protected resource, so there
is no need to trigger device reset in such case.
To facilitate security testing add firewall_irq_counter
debugfs
145b5dfcb421f4deebaf
change-id: 20241018-fix-drm-deferred-01c9996c17a6
Best regards,
--
Dmitry Baryshkov
Drop manual check of the TMDS char rate in the mode_valid callback. This
check is now being performed by the core.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/lontium-lt9611.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/bridge/lontium-lt9
This message reports a mismatch between new_crtc_state->enable and
has_connectors, which should be either both true or both false. However it
does not mention which one is true and which is false, which can be useful
for debugging. Add the value of both avriables to the log message.
Signed-off-by:
Replace .mode_valid() callback with .hdmi_tmds_char_rate_valid(). It is
more generic and is used in other mode validation paths. The rate
validation for .mode_valid() will be performed by the
drm_bridge_connector code.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi-q
On 10/11/2024 5:12 PM, Lizhi Hou wrote:
The hardware mailboxes are used by the driver to submit requests to
firmware and receive the completion notices from hardware.
Initially, a management mailbox channel is up and running. The driver may
request firmware to create/destroy more channels dynami
Use new drm_hdmi_connector_mode_valid() helper instead of a
module-specific copy.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 62b82b
Add drm_hdmi_connector_mode_valid(), generic helper for HDMI connectors.
It can be either used directly or as a part of the .mode_valid callback.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_hdmi_helper.c | 25 +
include/drm/display/drm_hdmi_helper.h
/display/drm_hdmi_helper.h | 4
7 files changed, 52 insertions(+), 25 deletions(-)
---
base-commit: af44b5b5776cc6ac1891393a37b1424509f07b35
change-id: 20241018-hdmi-mode-valid-aaec4428501c
Best regards,
--
Dmitry Baryshkov
On 10/11/2024 5:12 PM, Lizhi Hou wrote:
AMD NPU (Neural Processing Unit) is a multi-user AI inference accelerator
integrated into AMD client APU. NPU enables efficient execution of Machine
Learning applications like CNN, LLM, etc. NPU is based on AMD XDNA
Architecture. NPU is managed by amdxdna d
On 10/13/24 09:58, Simon Ser wrote:
On Thursday, October 3rd, 2024 at 22:01, Harry Wentland
wrote:
From: Alex Hung
It is to be used to enable HDR by allowing userpace to create and pass
3D LUTs to kernel and hardware.
1. new drm_colorop_type: DRM_COLOROP_3D_LUT.
2. 3D LUT modes define h
On 10/11/2024 3:57 AM, Simon Horman wrote:
Recently I noticed that both gcc-14 and clang-18 report that passing
a non-string literal as the format argument of alloc_workqueue()
is potentially insecure.
E.g. clang-18 says:
.../qaic_drv.c:61:23: warning: format string is not a string literal
(po
On 10/11/2024 3:57 AM, Simon Horman wrote:
Recently I noticed that both gcc-14 and clang-18 report that passing
a non-string literal as the format argument of alloc_workqueue()
is potentially insecure.
E.g. clang-18 says:
.../qaic_drv.c:61:23: warning: format string is not a string literal
(po
On Wed, Oct 16, 2024 at 10:51:02AM +0200, Peter Zijlstra wrote:
On Tue, Oct 08, 2024 at 01:34:57PM -0500, Lucas De Marchi wrote:
+static int parse_device(const char __user *ubuf, size_t size, u32 *instance)
+{
+ char buf[16];
+ ssize_t len;
+
+ if (size > sizeof(buf) - 1)
+
Hi,
On 18.10.24 10:56, Christian König wrote:
Am 18.10.24 um 07:46 schrieb Friedrich Vock:
When dma_fence_unwrap_merge is called on fence chains where the fences
aren't ordered by context, the merging logic breaks down and we end up
inserting fences twice. Doing this repeatedly leads to the num
On 9/21/2024 1:17 AM, Dmitry Baryshkov wrote:
Move existing register definitions to mdss.xml and use generated defines
for registers access instead of hand-coding everything in the source
file.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 35
The pull request you sent on Fri, 18 Oct 2024 15:53:18 +1000:
> https://gitlab.freedesktop.org/drm/kernel.git tags/drm-fixes-2024-10-18
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/5d97dde4d5f751858390b557729a1a12210024c1
Thank you!
--
Deet-doot-dot, I am a bot.
h
On 9/21/2024 1:17 AM, Dmitry Baryshkov wrote:
In preparation of adding more registers, move MDSS-related headers to
the separate top-level file.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/registers/display/mdp5.xml | 16 -
Em 18/10/2024 12:31, Alex Deucher escreveu:
On Fri, Oct 18, 2024 at 11:23 AM Rodrigo Vivi wrote:
On Thu, Oct 17, 2024 at 04:16:09PM -0300, André Almeida wrote:
Hi Raag,
Em 30/09/2024 04:38, Raag Jadav escreveu:
Introduce device wedged event, which will notify userspace of wedged
(hanged/unu
On Tue, Oct 15, 2024 at 07:29:57AM +, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> The driver now uses the legacy bridge helper code but can be configured
> to get built without it:
>
> ERROR: modpost: "devm_imx_drm_legacy_bridge"
> [drivers/gpu/drm/imx/ipuv3/parallel-display.ko] undefine
Of the page table implementations (AMD v1/2, VT-D SS, ARM32, DART)
arm_lpae is unique in how it handles partial unmap of large IOPTEs.
All other drivers will unmap the large IOPTE and return it's length. For
example if a 2M IOPTE is present and the first 4K is requested to be
unmapped then unmap
On 2024-10-15 13:01, Simon Ser wrote:
> On Tuesday, October 15th, 2024 at 12:47, Michel Dänzer
> wrote:
>
>> On 2024-10-13 15:34, Simon Ser wrote:
>>
>>> This is a flag to opt-out of the automagic buffer migration to
>>> system memory when importing a DMA-BUF.
>>>
>>> In multi-GPU scenarii, a Wa
On Wed, Oct 16, 2024 at 1:47 PM Harry Wentland wrote:
>
>
>
> On 2024-09-16 14:23, Thomas Weißschuh wrote:
> > Hi Harry, Leo and other amdgpu maintainers,
> >
> > On 2024-08-24 20:33:53+, Thomas Weißschuh wrote:
> >> The value of "min_input_signal" returned from ATIF on a Framework AMD 13
> >>
On Fri, Oct 18, 2024 at 03:49:34PM +0300, Abel Vesa wrote:
> The assignment of the of_node to the aux bridge needs to mark the
> of_node as reused as well, otherwise resource providers like pinctrl will
> report a gpio as already requested by a different device when both pinconf
> and gpios propert
On Fri, Oct 18, 2024 at 10:08:06AM +0100, Matthew Auld wrote:
> On 18/10/2024 00:39, Matthew Brost wrote:
> > Non-contiguous VRAM cannot be mapped in Xe nor can non-visible VRAM
> > easily be accessed. Add ttm_bo_access, which is similar to
> > ttm_bo_vm_access, to access such memory.
>
> Is the p
On Fri, Oct 18, 2024 at 04:01:17PM +, Arnd Bergmann wrote:
> On Fri, Oct 18, 2024, at 15:42, Dmitry Baryshkov wrote:
> > On Fri, Oct 18, 2024 at 03:08:45PM +, Arnd Bergmann wrote:
> >> From: Arnd Bergmann
> >>
> >> The imx display drivers use the new bridge connector helpers but don't
> >
On Fri, Oct 18, 2024, at 15:42, Dmitry Baryshkov wrote:
> On Fri, Oct 18, 2024 at 03:08:45PM +, Arnd Bergmann wrote:
>> From: Arnd Bergmann
>>
>> The imx display drivers use the new bridge connector helpers but don't
>> explicitly select CONFIG_DRM_DISPLAY_HELPER, leading to a link failure
>>
On Tue, Oct 15, 2024 at 07:29:58AM +, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> Every module should have a description, without this we get a
> build time warning.
>
> Fixes: cc3e8a216d6b ("drm/imx: add internal bridge handling display-timings
> DT node")
> Signed-off-by: Arnd Bergmann
On Fri, Oct 18, 2024 at 03:10:10PM +, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> Dividing a 64-bit integer prevents building this for 32-bit targets:
>
> ERROR: modpost: "__aeabi_uldivmod" [drivers/gpu/drm/rockchip/rockchipdrm.ko]
> undefined!
>
> As this function is not performance cr
On Fri, Oct 18, 2024 at 03:08:45PM +, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> The imx display drivers use the new bridge connector helpers but don't
> explicitly select CONFIG_DRM_DISPLAY_HELPER, leading to a link failure
> in rare configurations:
>
> ld.lld-20: error: undefined symbo
Hi Sumit,
On Thu, Oct 17, 2024 at 1:00 PM Sumit Garg wrote:
>
> Hi Jens,
>
> On Tue, 15 Oct 2024 at 15:47, Jens Wiklander
> wrote:
> >
> > Add support in the OP-TEE backend driver for restricted memory
> > allocation. The support is limited to only the SMC ABI and for secure
> > video buffers.
From: Brendan King
This adds a linked list of VM contexts which is needed for the next patch
to be able to correctly track VM contexts for destruction on file close.
It is only safe for VM contexts to be removed from the list and destroyed
when not in interrupt context.
Signed-off-by: Brendan K
From: Brendan King
When remaining resources are being cleaned up on driver close,
outstanding VM mappings may result in resources being leaked, due
to an object reference loop, as shown below, with each object (or
set of objects) referencing the object below it:
PVR GEM Object
GPU schedu
When remaining resources are being cleaned up on driver close,
outstanding VM mappings may result in resources being leaked, due
to an object reference loop, as shown below, with each object (or
set of objects) referencing the object below it:
PVR GEM Object
GPU scheduler "finished" fence
On Fri, Oct 18, 2024 at 05:26:51PM +0200, Luca Ceresoli wrote:
> Remove unintended extra word.
>
> Signed-off-by: Luca Ceresoli
> ---
> include/drm/drm_mode_object.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On 18/10/2024 14:33, Yunxiang Li wrote:
The old behavior reports the resident memory usage for this key and the
documentation say so as well. However this was accidentally changed to
include buffers that was evicted.
Fixes: a2529f67e2ed ("drm/amdgpu: Use drm_print_memory_stats helper from
fdi
On Thu, Oct 17, 2024 at 12:46 PM Sumit Garg wrote:
>
> Hi Jens,
>
> On Tue, 15 Oct 2024 at 15:47, Jens Wiklander
> wrote:
> >
> > Hi,
> >
> > This patch set allocates the restricted DMA-bufs via the TEE subsystem.
> > This a complete rewrite compared to the previous patch set [1], and other
> >
On Fri, Oct 18, 2024 at 11:23 AM Rodrigo Vivi wrote:
>
> On Thu, Oct 17, 2024 at 04:16:09PM -0300, André Almeida wrote:
> > Hi Raag,
> >
> > Em 30/09/2024 04:38, Raag Jadav escreveu:
> > > Introduce device wedged event, which will notify userspace of wedged
> > > (hanged/unusable) state of the DRM
/drm_atomic_helper.c | 5 +++--
include/drm/drm_mode_object.h | 2 +-
2 files changed, 4 insertions(+), 3 deletions(-)
---
base-commit: 75aa74d52f43e75d0beb20572f98529071b700e5
change-id: 20241018-drm-small-improvements-1d104cc10280
Best regards,
--
Luca Ceresoli
Remove unintended extra word.
Signed-off-by: Luca Ceresoli
---
include/drm/drm_mode_object.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/drm_mode_object.h b/include/drm/drm_mode_object.h
index 08d7a7f0188f..c68edbd126d0 100644
--- a/include/drm/drm_mode_object
On 10/18/24 17:12, Arnd Bergmann wrote:
From: Arnd Bergmann
The fb_io_mmap() function is used in the file operations but
not enabled in all configurations unless FB_IOMEM_FOPS gets
selected:
ld.lld-20: error: undefined symbol: fb_io_mmap
referenced by wm8505fb.c
drivers/video/f
On Thu, Oct 17, 2024 at 04:16:09PM -0300, André Almeida wrote:
> Hi Raag,
>
> Em 30/09/2024 04:38, Raag Jadav escreveu:
> > Introduce device wedged event, which will notify userspace of wedged
> > (hanged/unusable) state of the DRM device through a uevent. This is
> > useful especially in cases wh
From: Arnd Bergmann
The fb_io_mmap() function is used in the file operations but
not enabled in all configurations unless FB_IOMEM_FOPS gets
selected:
ld.lld-20: error: undefined symbol: fb_io_mmap
>>> referenced by wm8505fb.c
>>> drivers/video/fbdev/wm8505fb.o:(wm8505fb_ops) in ar
From: Arnd Bergmann
Clang-19 and above sometimes end up with multiple copies of the large
a6xx_hfi_msg_bw_table structure on the stack. The problem is that
a6xx_hfi_send_bw_table() calls a number of device specific functions to
fill the structure, but these create another copy of the structure on
From: Arnd Bergmann
Dividing a 64-bit integer prevents building this for 32-bit targets:
ERROR: modpost: "__aeabi_uldivmod" [drivers/gpu/drm/rockchip/rockchipdrm.ko]
undefined!
As this function is not performance criticial, just Use the div_u64() helper.
Fixes: 128a9bf8ace2 ("drm/rockchip: Ad
From: Arnd Bergmann
The imx display drivers use the new bridge connector helpers but don't
explicitly select CONFIG_DRM_DISPLAY_HELPER, leading to a link failure
in rare configurations:
ld.lld-20: error: undefined symbol: drm_bridge_connector_init
>>> referenced by imx-ldb.c
>>> dr
On Fri, Oct 18, 2024 at 05:25:22PM +0300, Laurent Pinchart wrote:
> Hi Greg,
>
> On Fri, Oct 18, 2024 at 04:09:26PM +0200, Greg KH wrote:
> > On Fri, Oct 18, 2024 at 03:36:48PM +0200, Geert Uytterhoeven wrote:
> > > On Fri, Oct 18, 2024 at 3:10 PM Laurent Pinchart wrote:
> > > > On Fri, Oct 18, 20
On Fri, Oct 18, 2024 at 03:36:48PM +0200, Geert Uytterhoeven wrote:
> Hi Laurent,
>
> CC GregKH
>
> On Fri, Oct 18, 2024 at 3:10 PM Laurent Pinchart
> wrote:
> > On Fri, Oct 18, 2024 at 09:45:52AM +0200, Geert Uytterhoeven wrote:
> > > Each bridge instance creates up to four auxiliary devices wi
Hi Greg,
On Fri, Oct 18, 2024 at 04:09:26PM +0200, Greg KH wrote:
> On Fri, Oct 18, 2024 at 03:36:48PM +0200, Geert Uytterhoeven wrote:
> > On Fri, Oct 18, 2024 at 3:10 PM Laurent Pinchart wrote:
> > > On Fri, Oct 18, 2024 at 09:45:52AM +0200, Geert Uytterhoeven wrote:
> > > > Each bridge instance
On 10/18/24 13:02, Dmitry Baryshkov wrote:
On Fri, Oct 18, 2024 at 12:18:11PM +0100, Lukasz Luba wrote:
There is a need to check the returned value of the registration function.
Why?
The question can be:
why this driver doesn't check errors from frameworks during the
registration?
Is it
1 - 100 of 161 matches
Mail list logo
