On 17-02-2025 22:56, Simona Vetter wrote:
On Mon, Feb 17, 2025 at 12:08:08PM +0200, Pekka Paalanen wrote:
Hi Arun,
this whole series seems to be missing all the UAPI docs for the DRM
ReST files, e.g. drm-kms.rst. The UAPI header doc comments are not a
replacement for them, I would assume both
On 17-02-2025 15:38, Pekka Paalanen wrote:
Hi Arun,
this whole series seems to be missing all the UAPI docs for the DRM
ReST files, e.g. drm-kms.rst. The UAPI header doc comments are not a
replacement for them, I would assume both are a requirement.
Without the ReST docs it is really difficult
This patch series adds support for the MediaTek MT8196 SoC in the CMDQ
driver and related subsystems. The changes include adding compatible
names and iommus property, updating driver data to accommodate hardware
changes, and modifying the usage of CMDQ APIs to support non-subsys ID
hardware.
---
C
To support hardware without subsys IDs on new SoCs, add a programming
flow that checks whether the subsys ID is valid. If the subsys ID is
invalid, the flow will call 2 alternative CMDQ APIs:
cmdq_pkt_assign() and cmdq_pkt_write_s_mask_value() to achieve the
same functionality.
Signed-off-by: Jaso
Add the compatible name and iommus property for MT8196.
In MT8196, all command buffers allocated and used by the GCE device
work with IOMMU.
Signed-off-by: Jason-JH Lin
---
.../devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml | 4
1 file changed, 4 insertions(+)
diff --git
a/Doc
Add GCE header define for GCE Thread priority and GCE event IDs
that used in the MT8196 dtsi.
Signed-off-by: Jason-JH Lin
---
arch/arm64/boot/dts/mediatek/mt8196-gce.h | 612 ++
1 file changed, 612 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8196-gce.h
d
To support hardware without subsys IDs on new SoCs, add a programming
flow that checks whether the subsys ID is valid. If the subsys ID is
invalid, the flow will call 2 alternative CMDQ APIs:
cmdq_pkt_assign() and cmdq_pkt_write_s_value() to achieve the same
functionality.
Signed-off-by: Jason-JH
When GCE executes instructions, the corresponding hardware register
can be found through the subsys ID. For hardware that does not support
subsys ID, its subsys ID will be set to invalid value and its physical
address needs to be used to generate GCE instructions.
This commit adds a pa_base parsin
Since GCE has been moved to mminfra in MT8196, all transactions from
mminfra to DRAM will have their addresses adjusted by subtracting a
mminfra offset.
This information should be handled inside the CMDQ driver, allowing
CMDQ users to call CMDQ APIs as usual.
Therefore, CMDQ driver needs to use th
MT8196 has 3 new hardware configuration compared with the previous SoC,
which correspond to the 3 new driver data:
1. mminfra_offset: For GCE data plane control
Since GCE has been moved into mminfra, GCE needs to append the
mminfra offset to the DRAM address when accessing the DRAM.
2. gce_
To support hardware without subsys IDs on new SoCs, add a programming
flow that checks whether the subsys ID is valid. If the subsys ID is
invalid, the flow will call 2 alternative CMDQ APIs:
cmdq_pkt_assign() and cmdq_pkt_write_s_value() to achieve the same
functionality.
Signed-off-by: Jason-JH
On Mon, Jan 06, 2025 at 05:06:35PM +0100, Ahmad Fatoum wrote:
> Ahmad Fatoum (5):
> arm64: dts: imx8mp-skov: correct PMIC board limits
> arm64: dts: imx8mp-skov: operate CPU at 850 mV by default
> arm64: dts: imx8mp-skov: use I2C5 for DDC
> dt-bindings: display/lvds-codec: a
On Tue, Jan 07, 2025 at 10:49:41AM +0100, Alexander Stein wrote:
> fsl,imx-iomuxc-gpr.yaml only contains the mux-controller but the actual
> video-mux is not part of it. So move it below root node.
> Fixes the dtbs_check warning:
> arch/arm/boot/dts/nxp/imx/imx7s-mba7.dtb: iomuxc-gpr@3034: 'csi
On Mon, Feb 17, 2025 at 10:27:56PM +0200, Tomi Valkeinen wrote:
> Hi,
>
> On 17/02/2025 22:15, Dmitry Baryshkov wrote:
> > On Wed, Feb 12, 2025 at 04:56:10PM +0200, Tomi Valkeinen wrote:
> > > Add XVUY2101010, a 10 bits per component YCbCr format in a 32 bit
> > > container.
> >
> > Is there a mo
Hi,
On Tue, 18 Feb 2025 01:33:34 +0200, Cristian Ciocaltea wrote:
>@Jianfeng: Did you encounter any particular issue with the current approach?
This patch is adding a dependency of hdptxphy1 to vop for all rk3588
boards, but not all rk3588 boards have dual hdmi, armsom sige7 is an
example. At run
> 1. How to avoid unnecessary calls to try_access().
>
> This is why I made Boot0.read() take a &RevocableGuard<'_, Bar0> as argument.
> I
> think we can just call try_access() once and then propage the guard through
> the
> callchain, where necessary.
Nope, you can't do that, RevocableGuard hol
On Tue, 18 Feb 2025 at 00:04, Alexandre Courbot wrote:
>
> Hi everyone,
>
> This short RFC is based on top of Danilo's initial driver stub series
> [1] and has for goal to initiate discussions and hopefully some design
> decisions using the simplest subdevice of the GPU (the timer) as an
> example
On Fri, 14 Feb 2025 16:08:40 +0100, Krzysztof Kozlowski wrote:
> Changes in v3:
> - Define bitfields in patches 1-3, so move there parts from patch #4
> - Use FIELD_GET
> - Keep separate cached->bit_clk_div and pix_clk_div
> - I think this implements entire feedback from Dmitry
> - Link to v2:
>
On Wed, 08 Jan 2025 14:40:48 -0800, Jessica Zhang wrote:
> Drop extra return at the end of dpu_crtc_reassign_planes()
>
>
Applied to msm-fixes, thanks!
[2/2] drm/msm/dpu: Drop extraneous return in dpu_crtc_reassign_planes()
https://gitlab.freedesktop.org/drm/msm/-/commit/5e192eefebaa
B
ot;);
MODULE_FIRMWARE("nvidia/gp10b/pmu/sig.bin");
---
base-commit: 2408a807bfc3f738850ef5ad5e3fd59d66168996
change-id: 20250217-nouveau-gm10b-guard-a438402b5022
Best regards,
--
Aaron Kling
On 2/17/25 4:33 PM, Heiko Stübner wrote:
> Am Montag, 17. Februar 2025, 03:44:37 MEZ schrieb Jianfeng Liu:
>> Hi Cristian,
>>
>> On Sat, 15 Feb 2025 02:55:39 +0200, Cristian Ciocaltea wrote:
>>> The HDMI1 PHY PLL clock source cannot be added directly to vop node in
>>> rk3588-base.dtsi, along with
On Tue, 11 Feb 2025 00:19:32 +0100, Marijn Suijten wrote:
> What used to be the input_10_bits boolean - feeding into the lowest
> bit of DSC_ENC - on MSM downstream turned into an accidental OR with
> the full bits_per_component number when it was ported to the upstream
> kernel.
>
> On typical
On Tue, 11 Feb 2025 19:59:19 -0800, Jessica Zhang wrote:
> Disable pingpong dither in dpu_encoder_helper_phys_cleanup().
>
> This avoids the issue where an encoder unknowingly uses dither after
> reserving a pingpong block that was previously bound to an encoder that
> had enabled dither.
>
>
On Sun, 09 Feb 2025 22:51:54 -0500, Ethan Carter Edwards wrote:
> There is a possibility for an uninitialized *ret* variable to be
> returned in some code paths.
>
> Fix this by initializing *ret* to 0.
>
>
Applied to msm-fixes, thanks!
[1/1] drm/msm/dpu: Fix uninitialized variable
ht
The Visionox RM692E5 is a 6.55" AMOLED panel used in Nothing Phone (1)
(sm7325-nothing-spacewar).
Signed-off-by: Danila Tikhonov
Reviewed-by: Rob Herring (Arm)
---
.../display/panel/visionox,rm692e5.yaml | 77 +++
1 file changed, 77 insertions(+)
create mode 100644
Docum
From: Eugene Lepshy
The DRM DSC helper has various bits_per_component values - not just 8.
But the DSC 1.1 block supports only 8, 10, and 12. Extend the guard
accordingly and add a comment noting this limitation.
Signed-off-by: Eugene Lepshy
Co-developed-by: Danila Tikhonov
Signed-off-by: Dani
From: Eugene Lepshy
Enable the Adreno GPU and configure the Visionox RM692E5 panel.
Signed-off-by: Eugene Lepshy
Co-developed-by: Danila Tikhonov
Signed-off-by: Danila Tikhonov
Reviewed-by: Konrad Dybcio
---
Note:
Depends on
https://lore.kernel.org/linux-arm-msm/20250122-dpu-111-topology-v2
From: Eugene Lepshy
Add the driver for Visionox RM692E5 panel support found in Nothing
Phone (1).
Signed-off-by: Eugene Lepshy
Co-developed-by: Danila Tikhonov
Signed-off-by: Danila Tikhonov
---
drivers/gpu/drm/panel/Kconfig | 10 +
drivers/gpu/drm/panel/Makefile
This patch series adds support for the Visionox RM692E5 panel, which is
used on the Nothing Phone (1) and then adds it to the DTS.
Before integrating the panel into the DTS, we update the DSI code to
allow bits-per-component (bpc) values of 10 and 12, since the Visionox
RM692E5 panel operates at 1
On Thu, 06 Feb 2025 11:46:36 -0800, Abhinav Kumar wrote:
> Widebus allows the DP controller to operate in 2 pixel per clock mode.
> The mode validation logic validates the mode->clock against the max
> DP pixel clock. However the max DP pixel clock limit assumes widebus
> is already enabled. Adju
On Mon, Feb 17, 2025 at 06:26:17PM +0100, Simona Vetter wrote:
> On Mon, Feb 17, 2025 at 12:08:08PM +0200, Pekka Paalanen wrote:
> > Hi Arun,
> >
> > this whole series seems to be missing all the UAPI docs for the DRM
> > ReST files, e.g. drm-kms.rst. The UAPI header doc comments are not a
> > rep
On Tue, 17 Dec 2024 14:35:40 +0200, Dmitry Baryshkov wrote:
> The SM6150 platform doesn't have 3DMux (MERGE_3D) block, so it can not
> split the screen between two LMs. Drop lm_pair fields as they don't make
> sense for this platform.
>
>
Applied to msm-fixes, thanks!
[1/1] drm/msm/dpu: corre
On Sat, 14 Dec 2024 00:14:16 +0200, Dmitry Baryshkov wrote:
> Some time ago we started the process of converting HW blocks to use
> revision-based checks instead of having feature bits (which are easy to
> miss or to set incorrectly). Then the process of such a conversion was
> postponed. (Mostly
On Thu, Feb 13, 2025 at 03:43:20PM +0100, Maxime Ripard wrote:
> After some discussions on the mailing-list for an earlier revision of
> the series, it was suggested to document the evolution of
> drm_atomic_state and its use by drivers to explain some of the confusion
> one might still encounter w
HDMI audio is available on the Rock 5B HDMI TX ports.
Enable it for both ports.
Reviewed-by: Quentin Schulz
Signed-off-by: Detlev Casanova
---
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk358
To support HDMI audio on the rk3588 based devices, the generic HDMI
Codec framework is used in the dw-hdmi-qp DRM bridge driver.
The implementation is mainly based on the downstream driver, ported to the
generic HDMI Codec framework [1] recently merged in the master branch.
The parameters computat
For hdmi0_sound, use the simple-audio-card driver with the hdmi0 QP node
as CODEC and the i2s5 device as CPU.
Similarly for hdmi1_sound, the CODEC is the hdmi1 node and the CPU is
i2s6, but only added in the rk3588-extra.dtsi device tree as the second
TX HDMI port is not available on base versions
From: Sugar Zhang
Register the dw-hdmi-qp bridge driver as an HDMI audio codec.
The register values computation functions (for n) are based on the
downstream driver, as well as the register writing functions.
The driver uses the generic HDMI Codec framework in order to implement
the HDMI audio
On Mon, 17 Feb 2025 at 15:07, Alexandre Courbot wrote:
>
> It is common to build a u64 from its high and low parts obtained from
> two 32-bit registers. Conversely, it is also common to split a u64 into
> two u32s to write them into registers. Add an extension trait for u64
> that implement these
This driver uses the enable-gpios property and it is confusing that the
error message refers to reset-gpios. Use the correct name when the
enable GPIO is not found.
Fixes: e2450d32e5fb5 ("drm/panel: ili9882t: Break out as separate driver")
Signed-off-by: John Keeping
---
drivers/gpu/drm/panel/p
Hi Alex,
On Mon, Feb 17, 2025 at 11:04:45PM +0900, Alexandre Courbot wrote:
> Hi everyone,
>
> This short RFC is based on top of Danilo's initial driver stub series
> [1] and has for goal to initiate discussions and hopefully some design
> decisions using the simplest subdevice of the GPU (the ti
Hi Alex,
> On 17 Feb 2025, at 11:04, Alexandre Courbot wrote:
>
> Signed-off-by: Alexandre Courbot
> ---
> rust/kernel/error.rs | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/rust/kernel/error.rs b/rust/kernel/error.rs
> index
> f6ecf09cb65f4ebe9b88da68b3830ae79aa4f182..8858eb13b3df6
Hi Alex,
> On 17 Feb 2025, at 11:04, Alexandre Courbot wrote:
>
> It is common to build a u64 from its high and low parts obtained from
> two 32-bit registers. Conversely, it is also common to split a u64 into
> two u32s to write them into registers. Add an extension trait for u64
> that implem
Hi,
On 17/02/2025 22:15, Dmitry Baryshkov wrote:
On Wed, Feb 12, 2025 at 04:56:10PM +0200, Tomi Valkeinen wrote:
Add XVUY2101010, a 10 bits per component YCbCr format in a 32 bit
container.
Is there a more common name for this format? Otherwise googling for it
reveals only your series.
In t
On 2/11/25 19:31, Christian König wrote:
> That was purely for the transition from static to dynamic dma-buf
> handling and can be removed again now.
>
> Signed-off-by: Christian König
> ---
> drivers/dma-buf/dma-buf.c | 34 --
> drivers/dma-buf/udmabuf.c
On Wed, Feb 12, 2025 at 04:56:09PM +0200, Tomi Valkeinen wrote:
> Add X403, a 3 plane non-subsampled YCbCr format.
>
> Signed-off-by: Tomi Valkeinen
> ---
> drivers/gpu/drm/drm_fourcc.c | 4
> include/uapi/drm/drm_fourcc.h | 8
> 2 files changed, 12 insertions(+)
>
Same comment:
On Wed, Feb 12, 2025 at 04:56:10PM +0200, Tomi Valkeinen wrote:
> Add XVUY2101010, a 10 bits per component YCbCr format in a 32 bit
> container.
Is there a more common name for this format? Otherwise googling for it
reveals only your series.
>
> Signed-off-by: Tomi Valkeinen
> ---
> drivers/gp
On 2/11/25 19:31, Christian König wrote:
> diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h
> index e7ad819962e3..e230af0d123f 100644
> --- a/include/linux/dma-fence.h
> +++ b/include/linux/dma-fence.h
> @@ -169,8 +169,8 @@ struct dma_fence_ops {
>* implementation know tha
On Wed, Feb 12, 2025 at 04:56:06PM +0200, Tomi Valkeinen wrote:
> Add two new pixel formats:
>
> DRM_FORMAT_XV15 ("XV15")
> DRM_FORMAT_XV20 ("XV20")
>
> The formats are 2 plane 10 bit per component YCbCr, with the XV15 2x2
> subsampled whereas XV20 is 2x1 subsampled.
>
> Signed-off-by: Tomi Valk
On Wed, Feb 12, 2025 at 04:56:07PM +0200, Tomi Valkeinen wrote:
> Add greyscale Y8 format.
>
> Signed-off-by: Tomi Valkeinen
> ---
> drivers/gpu/drm/drm_fourcc.c | 1 +
> include/uapi/drm/drm_fourcc.h | 3 +++
> 2 files changed, 4 insertions(+)
My 2c is that it's useful to have YUV (well, Y-on
On Mon, Feb 17, 2025 at 10:16:01PM +0800, Jun Nie wrote:
> Currently, only 2 pipes are used at most for a plane. A stage structure
> describes the configuration for a mixer pair. So only one stage is needed
> for current usage cases. The quad-pipe case will be added in future and 2
> stages are use
On Mon, Feb 17, 2025 at 10:15:55PM +0800, Jun Nie wrote:
> Current code only supports usage cases with one pair of mixers at
> most. To support quad-pipe usage case, two pairs of mixers need to
> be reserved. The lm_count for all pairs is cleared if a peer
> allocation fails in current implementati
On Mon, Feb 17, 2025 at 10:15:53PM +0800, Jun Nie wrote:
> It is more likely that resource allocation may fail in complex usage
> case, such as quad-pipe case, than existing usage cases.
> A resource type ID is printed on failure in the current implementation,
> but the raw ID number is not explici
On Mon, Feb 17, 2025 at 10:15:50PM +0800, Jun Nie wrote:
> The capability stored in sblk and pipe_hw_caps is checked only for
> SSPP of the first pipe in the pair with current implementation. That
> of the 2nd pipe, r_pipe, is not checked and may violate hardware
> capability. Move requirement chec
On Mon, Feb 17, 2025 at 05:38:08PM +0100, Simona Vetter wrote:
> On Fri, Feb 14, 2025 at 03:29:12PM +0200, Dmitry Baryshkov wrote:
> > On Fri, Feb 14, 2025 at 02:07:18PM +0100, Maxime Ripard wrote:
> > > On Thu, Feb 13, 2025 at 06:35:15PM +0200, Dmitry Baryshkov wrote:
> > > > On Thu, Feb 13, 2025
On 2/11/25 19:31, Christian König wrote:
> The fence_value_str and timeline_value_str callbacks were just an
> unnecessary abstraction in the SW sync implementation.
>
> The only caller of those callbacks already knew that the fence in
> questions is a timeline_fence. So print the values directly
On Mon, Feb 17, 2025 at 05:41:24PM +0100, Simona Vetter wrote:
> On Thu, Feb 13, 2025 at 03:43:50PM +0100, Maxime Ripard wrote:
> > Now that connectors are no longer necessarily created by the bridges
> > drivers themselves but might be created by drm_bridge_connector, it's
> > pretty hard for brid
On Mon, Feb 17, 2025 at 05:41:29PM +0100, Krzysztof Kozlowski wrote:
> Drop comments about SoC before each 'struct dpu_lm_sub_blks' for given
> SoC because it's duplicating the actual name of structure.
Historically there were more SoC-specific data, now we are really
limited to the LM sblk. Maybe
On Mon, Feb 17, 2025 at 05:41:36PM +0100, Krzysztof Kozlowski wrote:
> Implement new features and differences coming in v12.0 of DPU present on
> Qualcomm SM8750 SoC:
> 1. 10-bit color alpha.
> 2. New CTL_PIPE_ACTIVE and CTL_LAYER_ACTIVE registers for pipes and
>layer mixers.
> 2. Several diffe
On Mon, Feb 17, 2025 at 05:41:35PM +0100, Krzysztof Kozlowski wrote:
> The set_active_pipes() callback configures CTL_FETCH_PIPE_ACTIVE and
> newer DPU v12.0 comes with CTL_PIPE_ACTIVE, thus rename it to
> set_active_fetch_pipes() to better match the purpose.
>
> Signed-off-by: Krzysztof Kozlowski
On Mon, Feb 17, 2025 at 05:41:26PM +0100, Krzysztof Kozlowski wrote:
> Add DisplayPort controller for Qualcomm SM8750 SoC which so far looks
> fully compatible with earlier SM8650 variant.
As that became a question for QCS8300, does SM8750 also support exactly
two MST streams?
>
> Signed-off-by:
On Mon, Feb 17, 2025 at 05:41:34PM +0100, Krzysztof Kozlowski wrote:
> Add DPU version v12.0 support for the Qualcomm SM8750 platform.
>
> Signed-off-by: Krzysztof Kozlowski
>
> ---
>
> Changes in v2:
> 1. Add CDM
> ---
> .../drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h| 496
>
Currently CONFIG_PWM is a bool but I intend to change it to tristate. If
CONFIG_PWM=m in the configuration, the cpp symbol CONFIG_PWM isn't
defined and so the PWM code paths in the ti-sn65dsi86 driver are not
used.
The correct way to check for CONFIG_PWM is using IS_REACHABLE which does
the right
On Mon, Feb 17, 2025 at 05:41:33PM +0100, Krzysztof Kozlowski wrote:
> Add support for DSI on Qualcomm SM8750 SoC with notable difference:
>
> DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as
> parents before DSI PHY is configured and the PLLs are prepared with
> initial rate
On Mon, Feb 17, 2025 at 05:41:32PM +0100, Krzysztof Kozlowski wrote:
> Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with an
> incompatible hardware interface change:
>
> ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their
> offsets were just switched. Currently
Il 14/02/25 04:20, CK Hu (胡俊光) ha scritto:
On Tue, 2025-02-11 at 12:33 +0100, AngeloGioacchino Del Regno wrote:
External email : Please do not click links or open attachments until you have
verified the sender or the content.
In preparation for moving the common bits of this driver, merge the
On Tue, Feb 11, 2025 at 05:31:09PM +0100, Christian König wrote:
> That was purely for the transition from static to dynamic dma-buf
> handling and can be removed again now.
>
> Signed-off-by: Christian König
Yay!
Might uncover some fun if people have meanwhile started to rely on this
for perf
On Mon, Feb 17, 2025 at 05:41:31PM +0100, Krzysztof Kozlowski wrote:
> MDSS/MDP v12 comes with new bits in flush registers (e.g.
> MDP_CTL_0_FLUSH) for Layer Mixer 6 and 7.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 ++
> 1 file changed, 6 i
On Mon, Feb 17, 2025 at 05:41:30PM +0100, Krzysztof Kozlowski wrote:
> Add IDs for new blocks present in MDSS/MDP v12 for LM, DSC, PINGPONG and
> MERGE_3D blocks.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 6 ++
> 1 file changed, 6 insertions
From: Kerem Karabay
The Touch Bars found on x86 Macs support two USB configurations: one
where the device presents itself as a HID keyboard and can display
predefined sets of keys, and one where the operating system has full
control over what is displayed.
This commit adds support for the displa
From: Kerem Karabay
Add XRGB emulation helper for devices that only support BGR888.
Signed-off-by: Kerem Karabay
Signed-off-by: Aditya Garg
---
drivers/gpu/drm/drm_format_helper.c | 54 +
.../gpu/drm/tests/drm_format_helper_test.c| 81 +++
include
On Sat 15 Feb 2025 at 07:53, Greg Kroah-Hartman
wrote:
[...]
>>
>> >
>> >> + int id)
>> >> +{
>> >> + struct auxiliary_device *auxdev;
>> >> + int ret;
>> >> +
>> >> + auxdev = kzalloc(sizeof(*auxdev), GFP_KERNEL);
>> >> + if (!auxdev)
>> >> +
Le 17/02/2025 à 17:34, José Expósito a écrit :
Hi Louis,
Thanks for the quick review.
On Mon, Feb 17, 2025 at 04:45:37PM +0100, Louis Chauvet wrote:
Hi José,
Thanks for this new iteration!
Le 17/02/2025 à 11:01, José Expósito a écrit :
Add a list of planes to vkms_config and create as ma
Le 17/02/2025 à 18:49, Uwe Kleine-König a écrit :
Currently CONFIG_PWM is a bool but I intend to change it to tristate. If
CONFIG_PWM=m in the configuration, the cpp symbol CONFIG_PWM isn't
defined and so the PWM code paths in the ti-sn65dsi86 driver are not
used.
The correct way to check for
On Mon, 17 Feb 2025 13:27:25 +0100
Danilo Krummrich wrote:
> > Signed-off-by: Karol Herbst
>
> @Steven, @Masami: Can I get an ACK for taking this through the drm-misc tree?
>
> (Not cutting any context, since you have not been copied on this one.)
Sure,
Acked-by: Steven Rostedt (Google)
On Mon, Feb 17, 2025 at 12:08:08PM +0200, Pekka Paalanen wrote:
> Hi Arun,
>
> this whole series seems to be missing all the UAPI docs for the DRM
> ReST files, e.g. drm-kms.rst. The UAPI header doc comments are not a
> replacement for them, I would assume both are a requirement.
>
> Without the
On 2/11/25 19:31, Christian König wrote:
> As a workaround to smoothly transit from static to dynamic DMA-buf
> handling we cached the sg_table on attach if dynamic handling mismatched
> between exporter and importer.
>
> Since Dmitry and Thomas cleaned that up and also documented the lock
> handl
On 2/17/25 20:11, Dmitry Osipenko wrote:
> On 2/11/25 19:31, Christian König wrote:
>> The fence_value_str and timeline_value_str callbacks were just an
>> unnecessary abstraction in the SW sync implementation.
>>
>> The only caller of those callbacks already knew that the fence in
>> questions is
Rename member aud_sampe_size of struct hdmi_audio_param to
aud_sample_size to fix a typo and enhance readability.
This commit brings no functional changes.
Fixes: 8f83f26891e1 ("drm/mediatek: Add HDMI support")
Reviewed-by: CK Hu
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/m
Add DPU for Qualcomm SM8750 SoC which has several differences, new
blocks and changes in registers, making it incompatible with SM8650.
Signed-off-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Do
On Fri, Feb 14, 2025 at 08:37:56PM +, Jonathan Cavitt wrote:
> Add additional information to drm client so it can report the last 50
> exec queues to have been banned on it, as well as the last pagefault
> seen when said exec queues were banned. Since we cannot reasonably
> associate a pagefau
Drop comments about SoC before each 'struct dpu_lm_sub_blks' for given
SoC because it's duplicating the actual name of structure.
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/d
On Thu, Feb 13, 2025 at 03:43:50PM +0100, Maxime Ripard wrote:
> Now that connectors are no longer necessarily created by the bridges
> drivers themselves but might be created by drm_bridge_connector, it's
> pretty hard for bridge drivers to retrieve pointers to the connector and
> CRTC they are at
Implement the Automated Built-In Self-Test ABIST functionality
provided by the HDMIv2 IP and expose it through the "hdmi_abist"
debugfs file.
Write "1" to this file to activate ABIST, or "0" to deactivate.
The ABIST functionality can be used to validate that the HDMI
Transmitter itself works and
On Fri, Feb 14, 2025 at 08:47:26AM -0700, Jeffrey Hugo wrote:
> On 2/13/2025 7:17 AM, Thomas Zimmermann wrote:
> > Hi
> >
> > Am 12.02.25 um 16:52 schrieb Jeffrey Hugo:
> > > On 2/12/2025 6:27 AM, Jacek Lawrynowicz wrote:
> > > > Hi,
> > > >
> > > > Thanks for your detailed feedback and construct
Add support for the Qualcomm SM8750 platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/msm/msm_mdss.c | 33 +
drivers/gpu/drm/msm/msm_mdss.h | 1 +
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/msm/ms
Add DSI controller for Qualcomm SM8750 SoC which is quite different from
previous (SM8650) generation.
It does not allow the display clock controller clocks like "byte" and
"pixel" to be reparented to DSI PHY PLLs while the DSI PHY PLL is not
configured (not prepared, rate not set). Therefore
ass
Add IDs for new blocks present in MDSS/MDP v12 for LM, DSC, PINGPONG and
MERGE_3D blocks.
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
b/drivers/gpu/drm/ms
MDSS/MDP v12 comes with new bits in flush registers (e.g.
MDP_CTL_0_FLUSH) for Layer Mixer 6 and 7.
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
b/drivers/gp
The set_active_pipes() callback configures CTL_FETCH_PIPE_ACTIVE and
newer DPU v12.0 comes with CTL_PIPE_ACTIVE, thus rename it to
set_active_fetch_pipes() to better match the purpose.
Signed-off-by: Krzysztof Kozlowski
---
Changes in v2:
1. New patch
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc
Implement new features and differences coming in v12.0 of DPU present on
Qualcomm SM8750 SoC:
1. 10-bit color alpha.
2. New CTL_PIPE_ACTIVE and CTL_LAYER_ACTIVE registers for pipes and
layer mixers.
2. Several differences in LM registers (also changed offsets) for LM
crossbar hardware changes
Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with an
incompatible hardware interface change:
ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their
offsets were just switched. Currently these registers are not used in
the driver, so the easiest is to document both
Specific constrain in if:then: blocks for variable lists, like clocks
and clock-names, should have a fixed upper and lower size. Older
dtschema implied minItems, but that's not true since 2024 and missing
minItems means that lower bound is not set.
Signed-off-by: Krzysztof Kozlowski
---
.../dev
Add DPU version v12.0 support for the Qualcomm SM8750 platform.
Signed-off-by: Krzysztof Kozlowski
---
Changes in v2:
1. Add CDM
---
.../drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h| 496 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 29 ++
drivers/gpu/drm/msm/
Add support for DSI on Qualcomm SM8750 SoC with notable difference:
DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as
parents before DSI PHY is configured and the PLLs are prepared with
initial rate is set. Therefore assigned-clock-parents are not working
here and driver is re
Add MDSS/MDP display subsystem for Qualcomm SM8750 SoC, next generation
with two revisions up of the IP block comparing to SM8650.
Signed-off-by: Krzysztof Kozlowski
---
.../bindings/display/msm/qcom,sm8750-mdss.yaml | 460 +
1 file changed, 460 insertions(+)
diff --git
Add DisplayPort controller for Qualcomm SM8750 SoC which so far looks
fully compatible with earlier SM8650 variant.
Signed-off-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/device
Several devices have the same clock inputs, thus they can be in the same
if:then: clause, making everything smaller. No functional impact.
Signed-off-by: Krzysztof Kozlowski
---
.../bindings/display/msm/dsi-controller-main.yaml | 64 ++
1 file changed, 5 insertions(+), 59 d
Add DSI PHY v7.0 for Qualcomm SM8750 SoC which is quite different from
previous (SM8650) generation.
Signed-off-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display
Hi,
Dependency / Rabased on top of:
https://lore.kernel.org/all/20241214-dpu-drop-features-v1-0-988f0662c...@linaro.org/
Changes in v2:
- Implement LM crossbar, 10-bit alpha and active layer changes:
New patch: drm/msm/dpu: Implement new v12.0 DPU differences
- New patch: drm/msm/dpu: Add missi
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