пт, 21 лют. 2025 р. о 22:38 Rob Herring пише:
>
> On Tue, Feb 18, 2025 at 03:26:59PM +0200, Svyatoslav Ryhel wrote:
> > Add bindings for the LM3533 - a complete power source for
> > backlight, keypad, and indicator LEDs in smartphone handsets.
> > The high-voltage inductive boost converter provide
On Sat, Feb 22, 2025 at 10:51:01AM +0800, Yongbang Shi wrote:
> From: Baihan Li
>
> To realize HPD feature, request irq for HPD , add its handler function.
> We use pci_alloc_irq_vectors() to get our msi irq, because we have two
> interrupts now.
>
> Signed-off-by: Baihan Li
> Signed-off-by: Yo
On Sat, Feb 22, 2025 at 10:51:00AM +0800, Yongbang Shi wrote:
> From: Baihan Li
>
> Enable HPD feature and add its isr and event function. Add a drm client
> dev and realized the hotplug callback in it.
What for? There should be no need to add a separate drm client just for
the hotplug.
>
> Si
On Sat, Feb 22, 2025 at 10:50:59AM +0800, Yongbang Shi wrote:
> From: Baihan Li
>
> DP controller can support generating a color bar signal over the
> DisplayPort interface. This can be useful to check for possible DDR
> or GPU problems, as the signal generator resides completely in the DP
> bloc
On Sat, Feb 22, 2025 at 10:50:56AM +0800, Yongbang Shi wrote:
> From: Baihan Li
>
> Add dp serdes cfg in link training process, and related adapting
> and modificating. Change some init values about training,
> because we want completely to negotiation process, so we start with
> the maximum rate
On Sat, Feb 22, 2025 at 10:50:58AM +0800, Yongbang Shi wrote:
> From: Baihan Li
>
> Add registering drm_aux and use it to get connector edid with drm
> functions. Add ddc channel in connector initialization to put drm_aux
> in drm_connector. And also add detect callback to detect connector
> befo
On Sat, Feb 22, 2025 at 10:50:57AM +0800, Yongbang Shi wrote:
> From: Baihan Li
>
> Because the drm_aux of struct hibmc_dp_dev's member is not easy to get in
> hibmc_drm_dp.c, we move the drm_aux to struct hibmc_dp. Then there are some
> adaptations and modifications to make this patch compile.
On Sat, Feb 22, 2025 at 10:50:55AM +0800, Yongbang Shi wrote:
> From: Baihan Li
>
> This dp controller need features of digital-to-analog conversion and
> high-speed transmission in chip by its extern serdes controller. Our
> serdes cfg is relatively simple, just need two register configurations.
On Sat, Feb 22, 2025 at 10:50:54AM +0800, Yongbang Shi wrote:
> From: Baihan Li
>
> Move the macros below their corresponding registers to make
> them more obvious.
>
> Signed-off-by: Baihan Li
> Signed-off-by: Yongbang Shi
> ---
> ChangeLog:
> v2 -> v3:
> - restructuring the header dp_reg.h
From: Baihan Li
Add dp serdes cfg in link training process, and related adapting
and modificating. Change some init values about training,
because we want completely to negotiation process, so we start with
the maximum rate and the electrical characteristic level is 0.
Signed-off-by: Baihan Li
From: Baihan Li
Enable HPD feature and add its isr and event function. Add a drm client
dev and realized the hotplug callback in it.
Signed-off-by: Baihan Li
Signed-off-by: Yongbang Shi
---
ChangeLog:
v2 -> v3:
- remove mdelay(100) hpd function in ISR, suggested by Dmitry Baryshkov.
- remo
From: Baihan Li
This dp controller need features of digital-to-analog conversion and
high-speed transmission in chip by its extern serdes controller. Our
serdes cfg is relatively simple, just need two register configurations.
Don't need too much functions, like: power on/off, initialize, and some
From: Baihan Li
To realize HPD feature, request irq for HPD , add its handler function.
We use pci_alloc_irq_vectors() to get our msi irq, because we have two
interrupts now.
Signed-off-by: Baihan Li
Signed-off-by: Yongbang Shi
---
drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h | 3 +
.../gpu
From: Baihan Li
Move the macros below their corresponding registers to make
them more obvious.
Signed-off-by: Baihan Li
Signed-off-by: Yongbang Shi
---
ChangeLog:
v2 -> v3:
- restructuring the header dp_reg.h, suggested by Dmitry Baryshkov.
---
drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h |
From: Baihan Li
Add registering drm_aux and use it to get connector edid with drm
functions. Add ddc channel in connector initialization to put drm_aux
in drm_connector. And also add detect callback to detect connector
befored call connector_get_modes.
Signed-off-by: Baihan Li
Signed-off-by: Yo
From: Baihan Li
Because the drm_aux of struct hibmc_dp_dev's member is not easy to get in
hibmc_drm_dp.c, we move the drm_aux to struct hibmc_dp. Then there are some
adaptations and modifications to make this patch compile.
Signed-off-by: Baihan Li
Signed-off-by: Yongbang Shi
---
ChangeLog:
v2
From: Baihan Li
DP controller can support generating a color bar signal over the
DisplayPort interface. This can be useful to check for possible DDR
or GPU problems, as the signal generator resides completely in the DP
block. Add debugfs file that controls colorbar generator.
echo: config the co
From: Baihan Li
To support DP HPD, edid printing, and colorbar display features based on
the Hisislcon DP devices.
---
ChangeLog:
v2 -> v3:
- restructuring the header p_reg.h, suggested by Dmitry Baryshkov.
- add commit log about dp serdes, suggested by Dmitry Baryshkov.
- return value in
On Sat, 22 Feb 2025, at 7:57 AM, Jernej Škrabec wrote:
> Hi Ryan,
>
> sorry for very late review, but here we go...
No problem, thanks for the review!
> This patchset actually introduces 3 disticnt features, which should IMO
> be separated
> and thus making reviewing patches easier.
>
> 1. nativ
Applied. Thanks!
On Thu, Feb 20, 2025 at 11:28 AM André Almeida wrote:
>
> When a ring reset happens, the kernel log shows only "amdgpu: Starting
> ring reset", but when it finishes nothing appears in the
> log. Explicitly write in the log that the reset has finished correctly.
>
> Reviewed-by:
The sun4i TCON needs a reference to the D-PHY in order to support LVDS
on Allwinner D1s/T113.
Signed-off-by: Kuba Szczodrzyński
---
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
b/arch/ri
Fixes grammar issues in the VM_BIND locking documentation:
- Corrects adverb "also" positioning in the sentence.
Signed-off-by: Leonardo Felipe Takao Hirata
---
Documentation/gpu/drm-vm-bind-locking.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/gpu/drm-vm-
Add LVDS pins to the PIO since it's now supported on D1s/T113.
Signed-off-by: Kuba Szczodrzyński
---
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
b/arch/riscv/boot/dts/allwinner/su
On Allwinner chips with a combo D-PHY, the TCON LCD0 should fetch it
from device tree, in order to enable LVDS. Since the PHY also needs to
be powered off to disable LVDS, add a function to the quirks.
Signed-off-by: Kuba Szczodrzyński
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 12
dr
The Allwinner D1s/T113 needs to use the combo D-PHY to enable LVDS
output.
Enable LVDS support in the TCON and configure it using the PHY.
Signed-off-by: Kuba Szczodrzyński
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 28
1 file changed, 28 insertions(+)
diff --git a/d
Some Allwinner chips (notably the D1s/T113 and the A100) have a "combo
MIPI DSI D-PHY" which is required when using single-link LVDS0.
In this mode, the DSI peripheral is not used and the PHY is not
configured for DSI. Instead, the COMBO_PHY_REGx registers are set to
enable LVDS operation.
Enable
Some Allwinner chips (notably the D1s/T113 and the A100) have a "combo
MIPI DSI D-PHY" which is required when using single-link LVDS0. The same
PD0..PD9 pins are used for either DSI or LVDS.
Other than having to use the combo D-PHY, LVDS output is configured in
the same way as on older chips.
Thi
On Fri, 21 Feb 2025 00:58:00 +, Andre Przywara wrote:
> The Allwinner H616 SoC has a Mali-G31 MP2 GPU, which is of the Mali
> Bifrost family.
> Add the SoC specific compatible string and pair it with the bifrost
> fallback compatible.
>
> Signed-off-by: Andre Przywara
> ---
> Documentation
On Fri, 21 Feb 2025 00:57:58 +, Andre Przywara wrote:
> The Allwinner H6 and some later SoCs contain some bits in the PRCM (Power
> Reset Clock Management) block that control some power domains.
> Those power domains include the one for the GPU, the PLLs and some
> analogue circuits.
>
> Sig
On Thu, Feb 20, 2025 at 12:41:44PM +0200, Vinod Govindapillai wrote:
> During enabling FBC, for the very first frame, the prepare dirty
> rect routine wouldnt have executed as at that time the plane
> reference in the fbc_state would be NULL. So this could make
> driver program some invalid entries
On Thu, 20 Feb 2025 13:14:43 +0200, Dmitry Baryshkov wrote:
> Add the LCDC / LVDS clock input and the XO used to drive internal LVDS
> PLL to MDP4 controller bindings. The controller also provides LVDS PHY
> PLL, so add optional #clock-cells to the device.
>
> Signed-off-by: Dmitry Baryshkov
>
On Thu, 20 Feb 2025 11:44:54 +0200, Svyatoslav Ryhel wrote:
> From: David Heidelberg
>
> LVDS transmitter used in the Microsoft Surface RT.
>
> Signed-off-by: David Heidelberg
> Signed-off-by: Svyatoslav Ryhel
> ---
> Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml | 1 +
>
On Fri, Feb 21, 2025 at 10:38:02AM +0530, Raag Jadav wrote:
> In a wider effort to improve build speeds, we're attempting to split/cleanup
> core headers.
>
> This series attempts to cleanup io.h with "include what you need" approach.
>
> This depends on earlier modifications available in immutab
On Fri, Feb 21, 2025 at 04:24:21PM +0100, Krzysztof Kozlowski wrote:
> Before blend setup, all existing blend stages are cleared, so shall be
> active fetch pipes.
>
> Fixes: b3652e87c03c ("drm/msm/disp/dpu1: add support to program fetch active
> in ctl path")
> Signed-off-by: Krzysztof Kozlowski
On 2025-02-13 13:21, Leo Li wrote:
>
>
>
> On 2024-12-19 23:33, Alex Hung wrote:
>> This adds support for a 3D LUT.
>>
>> The color pipeline now consists of the following colorops:
>> 1. 1D curve colorop
>> 2. Multiplier
>> 3. 3x4 CTM
>> 4. 1D curve colorop
>> 5. 1D LUT
>> 6. 3D LUT
>> 7. 1D
Hi Dave, Simona,
New stuff for 6.15.
The following changes since commit 1abb2648698bf10783d2236a6b4a7ca5e8021699:
drm/amdgpu: avoid buffer overflow attach in smu_sys_set_pp_table()
(2025-02-12 19:47:15 -0500)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/lin
On Sat, 22 Feb 2025 at 07:15, Linus Torvalds
wrote:
>
> Side note: I think you do something while editing or
> cutting-and-pasting that loses indentation.
>
> I sometimes have to guess at what the intended grouping is.
>
> In this case, notice the "More catalog fixes" entry for the msm driver.
>
>
The pull request you sent on Sat, 22 Feb 2025 06:51:33 +1000:
> https://gitlab.freedesktop.org/drm/kernel.git tags/drm-fixes-2025-02-22
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/3ef7acec975bde28ab9cef92af76be8fc2ce684d
Thank you!
--
Deet-doot-dot, I am a bot.
h
Side note: I think you do something while editing or
cutting-and-pasting that loses indentation.
I sometimes have to guess at what the intended grouping is.
In this case, notice the "More catalog fixes" entry for the msm driver.
I *think* it refers to all the following bullet points up until the
Applied. Thanks!
Alex
On Mon, Feb 17, 2025 at 5:48 AM Colin Ian King wrote:
>
> There is a spelling mistake in max_oustanding_when_urgent_expected,
> fix it.
>
> Signed-off-by: Colin Ian King
> ---
> .../dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c | 6 +++---
> .../dc/dml2/dml21/s
Applied. Thanks!
Alex
On Fri, Feb 21, 2025 at 3:48 PM Alex Hung wrote:
>
> Reviewed-by: Alex Hung
>
> On 2/15/25 14:15, Melissa Wen wrote:
> > When switching to drm_edid, we slightly changed how to get edid by
> > removing the possibility of getting them from dc_link when in aux
> > transactio
> Does this look good now? Made orig a union.
Wait, it's messier. Maybe declare data type of val separately in each case?
>
> char *fourcc_string(char *buf, char *end, const u32 *fourcc, const char *fmt,
> struct printf_spec spec)
> {
> char output[sizeof("0123 little-endian (0x01234567)")];
>
Hi Linus,
Weekly drm fixes pull request, lots of small things all over, msm has
a bunch of things but all very small, xe, i915, a fix for the cgroup
dmem controller.
Thanks,
Dave.
drm-fixes-2025-02-22:
drm fixes for v6.14-rc4
core:
- remove MAINTAINERS entry
cgroup/dmem:
- use correct function
Add support for the Qualcomm SM8750 platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/msm/msm_mdss.c | 33 +
drivers/gpu/drm/msm/msm_mdss.h | 1 +
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/msm/ms
Reviewed-by: Alex Hung
On 2/15/25 14:15, Melissa Wen wrote:
When switching to drm_edid, we slightly changed how to get edid by
removing the possibility of getting them from dc_link when in aux
transaction mode. As MST doesn't initialize the connector with
`drm_connector_init_with_ddc()`, restor
On Tue, 18 Feb 2025 11:59:20 +, Prabhakar wrote:
> From: Lad Prabhakar
>
> Add a compatible string for the Renesas RZ/V2H(P) SoC variants that
> include a Mali-G31 GPU. These variants share the same restrictions on
> interrupts, clocks, and power domains as the RZ/G2L SoC, so extend
> the e
On Fri, Feb 21, 2025 at 07:13:06PM +, Aditya Garg wrote:
> > On Fri, Feb 21, 2025 at 11:37:57AM +, Aditya Garg wrote:
...
> >> +} __packed;
> >
> > Why __packed? Please explain and justify for all the data types that are
> > marked
> > with this attribute.
>
> Just following the origin
On Tue, Feb 18, 2025 at 03:26:59PM +0200, Svyatoslav Ryhel wrote:
> Add bindings for the LM3533 - a complete power source for
> backlight, keypad, and indicator LEDs in smartphone handsets.
> The high-voltage inductive boost converter provides the
> power for two series LED strings display backligh
On Fri, Feb 21, 2025 at 05:21:08PM +, Aditya Garg wrote:
> > On 21 Feb 2025, at 9:21 PM, andriy.shevche...@linux.intel.com wrote:
> > On Fri, Feb 21, 2025 at 11:36:00AM +, Aditya Garg wrote:
...
> >> + for (x = 0; x < pixels; x++) {
> >> + pix = le32_to_cpu(sbuf32[x]);
> >> + /* write red
On Fri, Feb 21, 2025 at 08:06:51PM +, Aditya Garg wrote:
>
> > Does this look good now? Made orig a union.
>
> Wait, it's messier. Maybe declare data type of val separately in each case?
Yes, this sounds better.
--
With Best Regards,
Andy Shevchenko
On Fri, Feb 21, 2025 at 10:18:16PM +0200, andriy.shevche...@linux.intel.com
wrote:
> On Fri, Feb 21, 2025 at 07:37:17PM +, Aditya Garg wrote:
> > > On 21 Feb 2025, at 8:59 PM, andriy.shevche...@linux.intel.com wrote:
> > > On Fri, Feb 21, 2025 at 11:37:13AM +, Aditya Garg wrote:
>
> > > F
On Fri, Feb 21, 2025 at 07:37:17PM +, Aditya Garg wrote:
> > On 21 Feb 2025, at 8:59 PM, andriy.shevche...@linux.intel.com wrote:
> > On Fri, Feb 21, 2025 at 11:37:13AM +, Aditya Garg wrote:
> > First of all, I do not see the cover letter. Is it only an issue on my side?
>
> These are lit
On Mon, Feb 03, 2025 at 12:57:55PM +0200, Abel Vesa wrote:
> Looking at both i915 and nouveau DP drivers, both are setting the first
> LTTPR (if found) in transparent mode first and then in non-transparent
> mode, just like the DP v2.0 specification mentions in section 3.6.6.1.
>
> Being part of t
On Fri, Feb 21, 2025, at 17:50, Andy Shevchenko wrote:
> On Fri, Feb 21, 2025 at 11:15:47AM +0100, Arnd Bergmann wrote:
>> As you already found, removing an old indirect #include that is
>> no longer needed usually leads to some files breaking. The more
>> impactful your change is in terms of build
> On 21 Feb 2025, at 8:59 PM, andriy.shevche...@linux.intel.com wrote:
>
> On Fri, Feb 21, 2025 at 11:37:13AM +, Aditya Garg wrote:
>> From: Hector Martin
>
> First of all, I do not see the cover letter. Is it only an issue on my side?
These are literally 3 patches that are self explanato
There is no need to print out page->index as part of the debug message.
Signed-off-by: Matthew Wilcox (Oracle)
---
drivers/staging/fbtft/fbtft-core.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/staging/fbtft/fbtft-core.c
b/drivers/staging/fbtft/fbtft-core.c
in
> On 21 Feb 2025, at 8:57 PM, andriy.shevche...@linux.intel.com wrote:
>
> On Thu, Feb 20, 2025 at 04:39:23PM +, Aditya Garg wrote:
>> From: Hector Martin
>>
>> %p4cc is designed for DRM/V4L2 FOURCCs with their specific quirks, but
>> it's useful to be able to print generic 4-character cod
Hi
>
> On Fri, Feb 21, 2025 at 11:37:57AM +, Aditya Garg wrote:
>> From: Kerem Karabay
>>
>> The Touch Bars found on x86 Macs support two USB configurations: one
>> where the device presents itself as a HID keyboard and can display
>> predefined sets of keys, and one where the operating sys
On Mon, Feb 17, 2025 at 10:16:04PM +0800, Jun Nie wrote:
> To support high-resolution cases that exceed the width limitation of
> a pair of SSPPs, or scenarios that surpass the maximum MDP clock rate,
> additional pipes are necessary to enable parallel data processing
> within the SSPP width constr
Hi Ryan,
sorry for very late review, but here we go...
Dne nedelja, 16. februar 2025 ob 19:31:59 Srednjeevropski standardni čas je
Ryan Walklin napisal(a):
> Hi All,
>
> v7 of this patch adding support for the Allwinner DE33 display engine, used
> in the H616 family of SoCs. Apologies for the
v12.0 DPU on SM8750 comes with new CTL_PIPE_ACTIVE register for
selective activation of pipes, which replaces earlier
dpu_hw_ctl_setup_blendstage() code path for newer devices.
Signed-off-by: Krzysztof Kozlowski
---
Changes in v3:
1. New patch, split from previous big DPU v12.0.
---
drivers/gp
On 2/14/2025 9:21 AM, Jeffrey Hugo wrote:
If mhi_fw_load_handler() bails out early because the EE is not capable
of loading firmware, we may reference fw_load_type in cleanup which is
uninitialized at this point. The cleanup code checks fw_load_type as a
proxy for knowing if fbc_image was allocat
On Friday, February 21st, 2025 at 19:41, Harry Wentland
wrote:
> > Other people have argued that strings make it easier for user-space to
> > start using a new KMS property without deploying new kernel uAPI headers.
>
> I don't understand this argument. You would either need to define the
> str
On 2025-02-21 11:42, Simon Ser wrote:
> On Friday, February 21st, 2025 at 17:18, Harry Wentland
> wrote:
>
>> I did a brief survey of other enum properties and noticed
>> that this isn't well documented for others, such as the Content
>> Protection connector property, or the COLOR_RANGE and C
Dne petek, 21. februar 2025 ob 01:58:00 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> The Allwinner H616 SoC has a Mali-G31 MP2 GPU, which is of the Mali
> Bifrost family.
> Add the SoC specific compatible string and pair it with the bifrost
> fallback compatible.
>
> Signed-off-
Dne petek, 21. februar 2025 ob 01:58:02 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> All Allwinner H616/H618 SoCs contain a Mali G31 MP2 GPU.
>
> Enable the DT nodes for that GPU, and specify the regulator providing
> power to the VDD_GPU pins of the package. The rest of the DT
Dne petek, 21. februar 2025 ob 01:58:01 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> The Allwinner H616 SoC contains a Mali-G31 MP2 GPU, which is of the Mali
> Bifrost family. There is a power domain specifically for that GPU, which
> needs to be enabled to make use of the it.
>
Hi Andy
> On 21 Feb 2025, at 9:21 PM, andriy.shevche...@linux.intel.com wrote:
>
> On Fri, Feb 21, 2025 at 11:36:00AM +, Aditya Garg wrote:
>> From: Kerem Karabay
>>
>> Add XRGB emulation helper for devices that only support BGR888.
>
> ...
>
>> + for (x = 0; x < pixels; x++) {
>> + p
Dne petek, 21. februar 2025 ob 01:57:59 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> The Allwinner Power Reset Clock Management (RPCM) block contains a few
> bits that control some power domains. The most prominent one is the one
> for the Mali GPU. On the Allwinner H6 this domai
On Wed, Feb 12, 2025 at 12:05:42PM -0800, Lucas De Marchi wrote:
> Now that devres supports component driver cleanup during driver removal
> cleanup, the xe custom support for removal callbacks is not needed
> anymore. Drop it.
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/xe/xe_dev
MDSS/MDP v12 comes with new bits in flush registers (e.g.
MDP_CTL_0_FLUSH) for Layer Mixer 6 and 7.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
On Fri, Feb 21, 2025 at 05:31:29PM +, Matthew Wilcox (Oracle) wrote:
> There is no need to print out page->index as part of the debug message.
>
> Signed-off-by: Matthew Wilcox (Oracle)
LGTM from my side,
Reviewed-by: Lorenzo Stoakes
> ---
> drivers/staging/fbtft/fbtft-core.c | 4 +---
>
On Friday, February 21st, 2025 at 17:18, Harry Wentland
wrote:
> I did a brief survey of other enum properties and noticed
> that this isn't well documented for others, such as the Content
> Protection connector property, or the COLOR_RANGE and COLOR_ENCODING
> plane properties.
Isn't the Conte
On Fri, Feb 21, 2025 at 11:15:47AM +0100, Arnd Bergmann wrote:
> On Fri, Feb 21, 2025, at 06:08, Raag Jadav wrote:
> > In a wider effort to improve build speeds, we're attempting to split/cleanup
> > core headers.
> >
> > This series attempts to cleanup io.h with "include what you need" approach.
>
On 2/19/2025 2:41 PM, Jeff Hugo wrote:
Qualcomm is migrating away from quicinc.com email addresses towards ones
with *.qualcomm.com.
Signed-off-by: Jeff Hugo
Pushed to drm-misc-next
-Jeff
Add initial test to xe query test suite that exercises the reset stats
query. The new test outputs the results of the query.
Signed-off-by: Jonathan Cavitt
---
tests/intel/xe_query.c | 85 ++
1 file changed, 85 insertions(+)
diff --git a/tests/intel/xe_q
On Tue, Feb 18, 2025 at 3:04 AM AngeloGioacchino Del Regno
wrote:
>
> Add compatible for Display Stream Compression (DSC) IP found in
> the display controller of the MT8188 SoC.
>
> This IP is fully compatible with the one found on MT8195.
>
> Signed-off-by: AngeloGioacchino Del Regno
>
> ---
>
On Mon, Feb 17, 2025 at 10:16:02PM +0800, Jun Nie wrote:
> Currently, SSPPs are assigned to a maximum of two pipes. However,
> quad-pipe usage scenarios require four pipes and involve configuring
> two stages. In quad-pipe case, the first two pipes share a set of
> mixer configurations and enable m
On Fri, Feb 21, 2025 at 04:24:29PM +0100, Krzysztof Kozlowski wrote:
> v12.0 DPU on SM8750 comes with new CTL_PIPE_ACTIVE register for
> selective activation of pipes, which replaces earlier
> dpu_hw_ctl_setup_blendstage() code path for newer devices.
>
> Signed-off-by: Krzysztof Kozlowski
>
> -
On Mon, Feb 17, 2025 at 10:16:03PM +0800, Jun Nie wrote:
> The content of every half of screen is sent out via one interface in
> dual-DSI case. The content for every interface is blended by a LM
> pair in quad-pipe case, thus a LM pair should not blend any content
> that cross the half of screen i
On Fri, 21 Feb 2025 at 18:12, Jun Nie wrote:
>
> Dmitry Baryshkov 于2025年2月21日周五 22:21写道：
> >
> > On Fri, Feb 21, 2025 at 04:07:45PM +0800, Jun Nie wrote:
> > > Dmitry Baryshkov 于2025年2月21日周五 00:17写道：
> > > >
> > > > On Thu, Feb 20, 2025 at 11:48:45PM +0800, Jun Nie wrote:
> > > > > Dmitry Barysh
On 2025-02-12 18:44, Leo Li wrote:
>
>
> On 2024-12-19 23:33, Alex Hung wrote:
>> This patch adds colorops for custom 1D LUTs in the SHAPER and
>> BLND HW blocks.
>>
>> With this change the following IGT tests pass:
>> kms_colorop --run plane-XR30-XR30-srgb_inv_eotf_lut
>> kms_colorop --run pl
On Fri, Feb 21, 2025 at 04:24:30PM +0100, Krzysztof Kozlowski wrote:
> v12.0 DPU on SM8750 comes with new LM crossbar that requires each pipe
> rectangle to be programmed separately in blend stage. Implement support
> for this along with a new CTL_LAYER_ACTIVE register and setting the
> blend stag
On Fri, Feb 21, 2025 at 04:24:28PM +0100, Krzysztof Kozlowski wrote:
> v12.0 DPU on SM8750 comes with 10-bit color alpha. Add register
> differences and new implementations of setup_alpha_out,
> setup_border_color and so one for this.
>
> Signed-off-by: Krzysztof Kozlowski
>
> ---
>
> Changes
Add support for DSI on Qualcomm SM8750 SoC with notable difference:
DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as
parents before DSI PHY is configured and the PLLs are prepared with
initial rate is set. Therefore assigned-clock-parents are not working
here and driver is re
Applied. Thanks!
On Wed, Feb 19, 2025 at 4:48 PM wrote:
>
> From: "Dr. David Alan Gilbert"
>
> The nbif_v6_3_1_sriov_funcs instance of amdgpu_nbio_funcs was added in
> commit 894c6d3522d1 ("drm/amdgpu: Add nbif v6_3_1 ip block support")
> but has remained unused.
>
> Alex has confirmed it wasn'
On 2025-02-15 09:40, Simon Ser wrote:
> On Monday, February 10th, 2025 at 23:03, Harry Wentland
> wrote:
>
+ * DOC: overview
+ *
+ * A colorop represents a single color operation. Colorops are chained
+ * via the NEXT property and make up color pipelines. Color pipelines
>
Dmitry Baryshkov 于2025年2月21日周五 22:21写道：
>
> On Fri, Feb 21, 2025 at 04:07:45PM +0800, Jun Nie wrote:
> > Dmitry Baryshkov 于2025年2月21日周五 00:17写道：
> > >
> > > On Thu, Feb 20, 2025 at 11:48:45PM +0800, Jun Nie wrote:
> > > > Dmitry Baryshkov 于2025年2月18日周二 03:57写道：
> > > > >
> > > > > On Mon, Feb 17
On Fri, Feb 21, 2025 at 04:24:20PM +0100, Krzysztof Kozlowski wrote:
> Resetting entire CTL path should also include resetting active fetch
> pipes.
>
> Fixes: e1a950eec256 ("drm/msm/dpu: add reset_intf_cfg operation for
> dpu_hw_ctl")
> Signed-off-by: Krzysztof Kozlowski
>
> ---
Reviewed-by:
On Fri, Feb 21, 2025 at 04:24:19PM +0100, Krzysztof Kozlowski wrote:
> Resetting mixers should also include resetting active fetch pipes.
>
> Fixes: ae4d721ce100 ("drm/msm/dpu: add an API to reset the encoder related hw
> blocks")
> Signed-off-by: Krzysztof Kozlowski
>
Reviewed-by: Dmitry Bary
Drop comments about SoC before each 'struct dpu_lm_sub_blks' for given
SoC because it's duplicating the actual name of structure.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 8
1 file
Extend the reset stats query tests to exercise the ban count value.
Assert that the ban count increases when a pagefault occurs.
Signed-off-by: Jonathan Cavitt
---
tests/intel/xe_query.c | 202 +
1 file changed, 202 insertions(+)
diff --git a/tests/intel/
Add tests that exercise the xe reset stats query. The current tests
simply output the result of the tests and assert that the reset and ban
counters properly increment.
Signed-off-by: Jonathan Cavitt
Jonathan Cavitt (4):
drm-uapi/xe: Declare reset stats query
tests/intel/xe_query: Implement
Align with 20250220203832.130430-1-jonathan.cav...@intel.com
Add initial declarations for the reset stats query, including necessary
structures and IOCTL macros.
Signed-off-by: Jonathan Cavitt
---
include/drm-uapi/xe_drm.h | 50 +++
1 file changed, 50 inserti
Extend the reset stats query tests to exercise the reset count value.
Assert that the reset count increases when an engine reset occurs.
Signed-off-by: Jonathan Cavitt
---
tests/intel/xe_query.c | 52 ++
1 file changed, 52 insertions(+)
diff --git a/tests
On Fri, Feb 21, 2025 at 11:36:00AM +, Aditya Garg wrote:
> From: Kerem Karabay
>
> Add XRGB emulation helper for devices that only support BGR888.
...
> + for (x = 0; x < pixels; x++) {
> + pix = le32_to_cpu(sbuf32[x]);
> + /* write red-green-blue to output i
On Fri, Feb 21, 2025 at 11:37:57AM +, Aditya Garg wrote:
> From: Kerem Karabay
>
> The Touch Bars found on x86 Macs support two USB configurations: one
> where the device presents itself as a HID keyboard and can display
> predefined sets of keys, and one where the operating system has full
>
On Fri, Feb 21, 2025 at 11:37:13AM +, Aditya Garg wrote:
> From: Hector Martin
First of all, I do not see the cover letter. Is it only an issue on my side?
> %p4cc is designed for DRM/V4L2 FOURCCs with their specific quirks, but
> it's useful to be able to print generic 4-character codes for
Before blend setup, all existing blend stages are cleared, so shall be
active fetch pipes.
Fixes: b3652e87c03c ("drm/msm/disp/dpu1: add support to program fetch active in
ctl path")
Signed-off-by: Krzysztof Kozlowski
---
Changes in v3:
1. New patch, split from previous big DPU v12.0.
---
driv
On Thu, Feb 20, 2025 at 04:39:23PM +, Aditya Garg wrote:
> From: Hector Martin
>
> %p4cc is designed for DRM/V4L2 FOURCCs with their specific quirks, but
> it's useful to be able to print generic 4-character codes formatted as
> an integer. Extend it to add format specifiers for printing gene
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