On Fri, Sep 12, 2025 at 07:53:50PM +0800, Xiangxu Yin wrote:
>
> On 9/12/2025 7:47 PM, Dmitry Baryshkov wrote:
> > On Fri, Sep 12, 2025 at 07:39:17PM +0800, Xiangxu Yin wrote:
> >> Add support for SM6150 DisplayPort controller, which shares base offset
> >> and configuration with SC7180. While SM6
On Wed Sep 10, 2025 at 5:01 PM JST, Danilo Krummrich wrote:
> On Wed Sep 10, 2025 at 6:48 AM CEST, Alexandre Courbot wrote:
>> On Tue Sep 9, 2025 at 11:43 PM JST, Danilo Krummrich wrote:
>>> impl Gpu {
>>> pub(crate) fn new<'a>(
>>> dev: &'a Device,
>>> bar: &'a
Hi Dave and Daniel,
Add DSIM bridge drvier support for Exynos7870 SoC.
Please kindly let me know if there is any problem.
Thanks,
Inki Dae
The following changes since commit c08c931060c7e44452e635e115913dd88214848c:
drm/gem/shmem: Extract drm_gem_shmem_release() from drm_gem_shmem_free()
Hi Dave and Daniel,
Add Exynos7870 SoC support to Exynos DSI driver and a bug fixup.
Please kindly let me know if there is any problem.
Ps. This PR depends on the following PR being merged first:
git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos
tags/exynos-drm-misc-next-for-v
The imx-dcss atomic_check implementation uses the deprecated
drm_atomic_get_existing_crtc_state() helper.
This hook is called as part of the global atomic_check, thus before the
states are swapped. The existing state thus points to the new state, and
we can use drm_atomic_get_new_crtc_state() inst
Patch does not introduce any functional change but would help out when
introducing DRM_COLOR_FORMAT enum in a sub-sequent patch.
Auto will implictly fallthrough to RGB as that should be further
driver-defined.
Signed-off-by: Marius Vlad
---
drivers/gpu/drm/display/drm_hdmi_state_helper.c | 3 ++
This series adds basic Panthor tests. In particular, these are being
used to test both Panthor[0] and Tyr[1], i.e.: the new Rust GPU driver
that implements Panthor's uAPI (i.e.: panthor_drm.h). Most of the
initial tests were chosen in order to have something to test Tyr with,
but this series lays t
On Sun Sep 14, 2025 at 7:06 AM JST, Joel Fernandes wrote:
> On Sat, Sep 13, 2025 at 02:29:54PM -0700, John Hubbard wrote:
> [..]
>
>> >
>> > I would suggest taking a look at our website and the links there (like
>> > issue #2) -- what we are doing upstream Rust is documented.
>>
>> ...and my ques
GuC IRQ and tasklet handler receive just single G2H message, and let other
messages to be received from next tasklet. During this chained tasklet
process, if reset process started, communication will be disabled.
Skip warning for this condition.
Fixes: 65dd4ed0f4e1 ("drm/i915/guc: Don't receive al
On 9/8/25 10:27 AM, Akhil P Oommen wrote:
> There are some special registers which are accessible even when GX power
> domain is collapsed during an IFPC sleep. Accessing these registers
> wakes up GPU from power collapse and allow programming these registers
> without additional handshake with GMU
Hi Danilo,
On Sat, Sep 13, 2025 at 09:53:16PM +0200, Danilo Krummrich wrote:
> On Sat Sep 13, 2025 at 7:13 PM CEST, Joel Fernandes wrote:
> > On Sat, Sep 13, 2025 at 03:30:31PM +0200, Danilo Krummrich wrote:
> >> On Sat Sep 13, 2025 at 3:02 AM CEST, Joel Fernandes wrote:
> >> > Any chance we can i
Hello Manikandan,
This patch has been reviewed for a while now. but i didn't get an
update if it's been pulled yet or not .
kindly can you kindly update if it's been pulled or not ?
thanks in advance.
On Mon, Aug 18, 2025 at 12:16 PM wrote:
>
> On 14/08/25 4:09 am, Eslam Khafagy wrote:
> > EXTE
On Sat, Sep 13, 2025 at 02:29:54PM -0700, John Hubbard wrote:
[..]
> >
> > I would suggest taking a look at our website and the links there (like
> > issue #2) -- what we are doing upstream Rust is documented.
>
> ...and my question was asked before reading through issue #2. So your
> and Danilo
On Mon, Sep 08, 2025 at 03:04:20PM +0200, Neil Armstrong wrote:
> The QMP USB3/DP Combo PHY hosts an USB3 phy and a DP PHY on top
> of a combo glue to route either lanes to the 4 shared physical lanes.
>
> The routing of the lanes can be:
> - 2 DP + 2 USB3
> - 4 DP
> - 2 USB3
>
> The layout of th
On 9/13/25 1:37 PM, Miguel Ojeda wrote:
On Sat, Sep 13, 2025 at 7:14 PM Joel Fernandes wrote:
I am not alone in that opinion.
Hmm... I am not sure how to read this.
This should be first-class in a (systems) language, built into
the language itself?
On this particular point, and *only* th
Hi Miguel,
On Sat, Sep 13, 2025 at 10:37:34PM +0200, Miguel Ojeda wrote:
> On Sat, Sep 13, 2025 at 7:14 PM Joel Fernandes wrote:
> >
> > I am not alone in that opinion.
>
> Hmm... I am not sure how to read this.
I don't follow? I am just saying that pinning seems to be a rather odd thing
to do
On Sat, Sep 13, 2025 at 7:14 PM Joel Fernandes wrote:
>
> I am not alone in that opinion.
Hmm... I am not sure how to read this.
> This should be first-class in a (systems) language, built into
> the language itself?
I would suggest taking a look at our website and the links there (like
issue #
Several firmware files loaded from userspace feature a common header
that describes their payload. Add basic support for it so subsequent
patches can leverage it.
Acked-by: Danilo Krummrich
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/firmware.rs | 62 +
On Sat Sep 13, 2025 at 7:13 PM CEST, Joel Fernandes wrote:
> On Sat, Sep 13, 2025 at 03:30:31PM +0200, Danilo Krummrich wrote:
>> On Sat Sep 13, 2025 at 3:02 AM CEST, Joel Fernandes wrote:
>> > Any chance we can initialize the locks later? We don't need locking until
>> > after the boot process is
From: Molly Sophia
Add documentation for "novatek,nt35596s" panel.
Signed-off-by: Molly Sophia
Signed-off-by: Arnaud Ferraris
Acked-by: Krzysztof Kozlowski
---
.../bindings/display/panel/novatek,nt36672a.yaml| 21 ++---
1 file changed, 14 insertions(+), 7 deletions(-)
di
From: Molly Sophia
Novatek NT35596s is a generic DSI IC that drives command and video mode
panels.
Currently add support for the LCD panel from JDI connected with this IC,
as found on Xiaomi Mi Mix 2S phones.
Signed-off-by: Molly Sophia
Signed-off-by: Arnaud Ferraris
Signed-off-by: David Heide
These patches add support for Novatek NT35596S based JDI FHD panels.
This panel is already used by mainlined Xiaomi Mi Mix 2S mobile phone.
Notes:
- I'm taking over this series as the original submitter is no longer
able to work on/test those patches.
Changes in v5:
- Split changes affecting or
From: Molly Sophia
Preparation for the follow-up nt35596s support, where not all sequences
are provided.
Signed-off-by: Molly Sophia
Signed-off-by: Arnaud Ferraris
Signed-off-by: David Heidelberg
---
drivers/gpu/drm/panel/panel-novatek-nt36672a.c | 27 ++
1 file chang
The only device-specific part of panthor's get_dev_status devfreq
callback is getting the clock frequency. All the other logic surrounding
what it does may be useful for other devfreq implementations however.
Expose it in the panthor_devfreq.h header file, and make it call back
into get_cur_freq i
On Sat Sep 13, 2025 at 11:12 PM JST, Alexandre Courbot wrote:
> Sending a final revision to have the `Link:` tags that dim requires, and
> for the record.
>
> This series makes more progress on the GSP boot process for Ampere GPUs.
>
> At the end of the previous series [1], we were left with a WPR
This patch series improves the Solomon SSD130x DRM driver by adopting
existing DRM helpers, improving code clarity, and following kernel
coding standards.
* Patch #1 moves DRM GEM framebuffer CPU access calls to make critical
sections more visible and maintainable.
* Patch #2 replaces WARN_ON wi
On Tue, Sep 09, 2025 at 02:16:12PM -0500, Mario Limonciello (AMD) wrote:
> PCI devices can be configured as wakeup sources from low power states.
> However, when the system is halting or powering off such wakeups are
> not expected and may lead to spurious behavior.
I'm a little unclear on the nom
The msm atomic_check implementation uses the deprecated
drm_atomic_get_existing_crtc_state() helper.
This hook is called as part of the global atomic_check, thus before the
states are swapped. The existing state thus points to the new state, and
we can use drm_atomic_get_new_crtc_state() instead.
The ITE IT6263 based NXP LVDS to HDMI converter can be attached to the
i.MX943 EVK board LVDS port using the mini-SAS connector. Since this is
the default configuration for the EVK, add support for it here.
Signed-off-by: Laurentiu Palcu
Reviewed-by: Frank Li
---
arch/arm64/boot/dts/freescale/i
Convert kselftest docs link to internal cross-reference.
Acked-by: Mario Limonciello (AMD)
Signed-off-by: Bagas Sanjaya
---
Documentation/admin-guide/pm/amd-pstate.rst | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/Documentation/admin-guide/pm/amd-pstate.rst
b/Documentat
On Sat, Sep 13, 2025 at 03:30:31PM +0200, Danilo Krummrich wrote:
> On Sat Sep 13, 2025 at 3:02 AM CEST, Joel Fernandes wrote:
> > Any chance we can initialize the locks later? We don't need locking until
> > after the boot process is completed, and if there's a way we can dynamically
> > "pin", wh
On Wed, 27 Aug, 2025 08:57:58 +0200 "Maxime Ripard" wrote:
> Hi Rahul,
>
> On Wed, Aug 20, 2025 at 04:46:52AM +, Rahul Rameshbabu wrote:
>> On Tue, 19 Aug, 2025 11:06:40 +0200 "Maxime Ripard"
>> wrote:
>> > Hi Rahul,
>> >
>> > On Mon, Aug 18, 2025 at 05:04:15AM +, Rahul Rameshbabu wrote:
Add the necessary code needed to compile panthor tests as well as the
basic infrastructure that will be used by the Panthor tests themselves.
To make sure everything is in order, add a basic test in
panthor_query.c.
Signed-off-by: Daniel Almeida
---
lib/igt_panthor.c | 41 ++
The mentioned function has been renamed since commit 180fc134d712
("drm/scheduler: Rename cleanup functions v2."), so let it refer to
the current one.
Signed-off-by: Luc Ma
---
include/drm/gpu_scheduler.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/gpu_schedul
On Fri, Sep 12, 2025 at 08:17:09AM +0200, Maud Spierings wrote:
> Hi Frank,
> Thanks for the review.
>
> On 9/11/25 17:33, Frank Li wrote:
> > On Thu, Sep 11, 2025 at 09:53:18AM +0200, Maud Spierings via B4 Relay wrote:
> > > From: Maud Spierings
> > >
> > > The Maxim MAX25014 is a 4-channel autom
On 24/07/2025 10:39, AngeloGioacchino Del Regno wrote:
Add a power supply for the Cache Coherent Interconnect node as it
is required to perform CPU DVFS because both are scaling together.
Signed-off-by: AngeloGioacchino Del Regno
Applied, thanks
---
arch/arm64/boot/dts/mediatek/mt8183
Signed-off-by: Zhijian Yan
---
drivers/gpu/drm/panel/panel-edp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panel/panel-edp.c
b/drivers/gpu/drm/panel/panel-edp.c
index 62435e3cd9f4..2c8536c64c19 100644
--- a/drivers/gpu/drm/panel/panel-edp.c
+++ b/drivers/gpu/drm/panel/p
There are a few cases where we need the lowercase name of a given
chipset, notably to resolve firmware files paths for dynamic loading or
to build the module information.
So far, we relied on a static `NAMES` array for the latter, and some
CString hackery for the former.
Replace both with a new `
We want to store the GSP and SEC2 falcon instances inside the `Gpu`
structure, but doing so require these types to implement `Send` for
`pci::Driver` to remain implementable on `NovaCore`, which embeds `Gpu`.
All implementors of `FalconEngine` and `FalconHal` satisfy the
requirements of `Send`, an
Compute more of the required FB layout information to boot the GSP
firmware.
This information is dependent on the firmware itself, so first we need
to import and abstract the required firmware bindings in the `nvfw`
module.
Then, a new FB HAL method is introduced in `fb::hal` that uses these
bind
The Booter signed firmware is an essential part of bringing up the GSP
on Turing and Ampere. It is loaded on the sec2 falcon core and is
responsible for loading and running the RISC-V GSP bootloader into the
GSP core.
Add support for parsing the Booter firmware loaded from userspace, patch
its sig
From: Alistair Popple
Interacting with the GSP currently requires using definitions from C
header files. Rust definitions for the types needed for Nova core will
be generated using the Rust bindgen tool. This patch adds the base
module to allow inclusion of the generated bindings. The generated
b
570.144 is the latest available into linux-firmware as of this commit,
and the one we will use to start development of nova-core. It should
eventually be dropped for a newer version before the driver becomes able
to do anything useful. The newer firmware is expected to iron out some
of the inelegan
The GSP bootloader is a small RISC-V firmware that is loaded by Booter
onto the GSP core and is in charge of loading, validating, and starting
the actual GSP firmware.
It is a regular binary firmware file containing a specific header.
Create a type holding the DMA-mapped firmware as well as useful
The GSP firmware is a binary blob that is verified, loaded, and run by
the GSP bootloader. Its presentation is a bit peculiar as the GSP
bootloader expects to be given a DMA address to a 3-levels page table
mapping the GSP firmware at address 0 of its own address space.
Prepare such a structure co
When all the firmware files are loaded from `Firmware::new`, it makes
sense to have the firmware request code as a closure. However, since we
eventually want each individual firmware constructor to request its own
file (and get rid of `Firmware` altogether), move this code into a
dedicated function
Sending a final revision to have the `Link:` tags that dim requires, and
for the record.
This series makes more progress on the GSP boot process for Ampere GPUs.
At the end of the previous series [1], we were left with a WPR memory
region created by the FRTS firmware, but still far from the GSP r
On Sat Sep 13, 2025 at 3:02 AM CEST, Joel Fernandes wrote:
> Any chance we can initialize the locks later? We don't need locking until
> after the boot process is completed, and if there's a way we can dynamically
> "pin", where we hypothetically pin after the boot process completed, that
> might a
The ssd130x_crtc_mode_valid() function contains a manual implementation
to validate the display mode against the panel's single fixed resolution.
This pattern is common for simple displays, and the DRM core already
provides the drm_crtc_helper_mode_valid_fixed() helper for this exact
use case.
Si
There may be the panel or bridge after &analogix_dp_device.bridge.
Add rockchip_dp_attach() to support the next bridge attachment for
the Rockchip side.
Signed-off-by: Damon Ding
---
.../gpu/drm/rockchip/analogix_dp-rockchip.c | 19 +++
1 file changed, 19 insertions(+)
diff --
To prevent log spam, convert all instances to the DRM-specific
drm_WARN_ON_ONCE() macro. This ensures that a warning is emitted only
the first time the condition is met for a given device instance, which
is the desired behavior within the graphics subsystem.
Signed-off-by: Iker Pedrosa
---
drive
Fix integer overflow vulnerabilities in fbcon_do_set_font() where font
size calculations could overflow when handling user-controlled font
parameters.
The vulnerabilities occur when:
1. CALC_FONTSZ(h, pitch, charcount) performs h * pith * charcount
multiplication with user-controlled values tha
The code contains several instances of chained assignments. The Linux
kernel coding style generally favors clarity and simplicity over terse
syntax. Refactor the code to use a separate line for each assignment.
Signed-off-by: Iker Pedrosa
---
drivers/gpu/drm/solomon/ssd130x.c | 12
The ssd130x_connector_get_modes function contains a manual implementation
to manage modes.
This pattern is common for simple displays, and the DRM core already
provides the drm_connector_helper_get_modes_fixed() helper for this exact
use case.
Signed-off-by: Iker Pedrosa
---
drivers/gpu/drm/sol
Calls to drm_gem_fb_end_cpu*() should be between the calls to
drm_dev*(), and not hidden inside some other function. This way the
critical section code is visible at a glance, keeping it short and
improving maintainability.
Signed-off-by: Iker Pedrosa
---
drivers/gpu/drm/solomon/ssd130x.c | 33 +
El mié, 10 sept 2025 a las 13:35, Krzysztof Kozlowski
() escribió:
>
> On Tue, Sep 09, 2025 at 06:52:44PM +0200, Iker Pedrosa wrote:
> > Add binding for Sitronix ST7920 display.
> >
> > Signed-off-by: Iker Pedrosa
> > ---
> > .../bindings/display/sitronix,st7920.yaml | 52
> > ++
From: Jayesh Choudhary
TIDSS hardware, by itself, does not have variable max pixel clock for
each VP. The maximum pixel clock is determined by the SoC's clocking
architecture.
The limitation that has been modeled until now comes from the SoC's
clocking architecture (PLL can only be programmed to
On Monday, 8 September 2025 13:15:03 Central European Summer Time
AngeloGioacchino Del Regno wrote:
> Il 05/09/25 12:22, Nicolas Frattaroli ha scritto:
> > On the MediaTek MT8196 SoC, the GPU has its power and frequency
> > dynamically controlled by an embedded special-purpose MCU. This MCU is
> >
On Thu, 04 Sep 2025, Liao Yuanhong wrote:
> For ternary operators in the form of "a ? false : true", if 'a' itself
> returns a boolean result, the ternary operator can be omitted. Remove
> redundant ternary operators to clean up the code.
>
> Signed-off-by: Liao Yuanhong
Pushed to drm-intel-next
On Fri, Sep 12, 2025 at 11:38 AM Nicolas Frattaroli
wrote:
>
> The Mali-based GPU on the MediaTek MT8196 SoC uses a separate MCU to
> control the power and frequency of the GPU.
>
> It lets us omit the OPP tables from the device tree, as those can now be
> enumerated at runtime from the MCU.
>
> A
This series introduces two new drivers to accomplish controlling the
frequency and power of the Mali GPU on MediaTek MT8196 SoCs.
The reason why it's not as straightforward as with other SoCs is that
the MT8196 has quite complex glue logic in order to squeeze the maximum
amount of performance poss
On 10.09.25 13:59, Thadeu Lima de Souza Cascardo wrote:
> When the TTM pool tries to allocate new pages, it stats with max order. If
> there are no pages ready in the system, the page allocator will start
> reclaim. If direct reclaim fails, the allocator will reduce the order until
> it gets all th
Add support in the OP-TEE backend driver for dynamic protected memory
allocation using the SMC ABI.
Reviewed-by: Sumit Garg
Signed-off-by: Jens Wiklander
---
drivers/tee/optee/smc_abi.c | 78 +++--
1 file changed, 75 insertions(+), 3 deletions(-)
diff --git a/dr
Move reset configuration to be managed via qmp_phy_cfg instead of
hardcoded lists. This enables per-PHY customization and simplifies
initialization logic for USB-only and USB/DP switchable PHYs.
Signed-off-by: Xiangxu Yin
---
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 56 ++--
The atmel-hlcdc atomic_check implementation uses the deprecated
drm_atomic_get_existing_crtc_state() helper.
This hook is called as part of the global atomic_check, thus before the
states are swapped. The existing state thus points to the new state, and
we can use drm_atomic_get_new_crtc_state() i
Hello Maxime,
On Wed, 20 Aug 2025 13:13:02 +0200
Luca Ceresoli wrote:
> > > + /*
> > > + * sn65dsi83_atomic_disable() should release some resources, but it
> > > + * cannot if we call drm_bridge_unplug() before it can
> > > + * drm_bridge_enter(). If that happens, let's release those
> > > +
Hi Raphael,
Thank you for this patch.
On Thu, Jul 17, 2025 at 09:15:32PM +0200, Raphael Gallais-Pou wrote:
> Return value for DMA allocation was not checked. Check it and return
> error code in case of failing.
>
> Signed-off-by: Raphael Gallais-Pou
> ---
> drivers/gpu/drm/sti/sti_drv.c | 5 +
For Rockchip platforms, the YUV color formats are currently unsupported.
This compatibility check was previously implemented in
&analogix_dp_plat_data.get_modes().
Moving color format check to &drm_connector_helper_funcs.atomic_check()
would get rid of &analogix_dp_plat_data.get_modes() and be mor
On Tue, 09 Sep 2025, S Sebinraj wrote:
> diff --git a/drivers/gpu/drm/xe/xe_gpu_freq_trace.h
> b/drivers/gpu/drm/xe/xe_gpu_freq_trace.h
> new file mode 100644
> index ..f188d529ae60
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_gpu_freq_trace.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-
Use the existing DP helper APIs instead of repeated self-defined
interfaces with the same functions. It can help make codes more
concise.
Damon Ding (4):
drm/bridge: analogix_dp: Apply DP helper API
drm_dp_dpcd_read_link_status()
drm/bridge: analogix_dp: Apply DP helper API
drm_dp_cloc
On Thu, Sep 11, 2025 at 10:55:07PM +0800, Xiangxu Yin wrote:
> Define qmp_usbc_dp_phy_ops struct to support DP mode on USB/DP
> switchable PHYs.
>
> Signed-off-by: Xiangxu Yin
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 192
> ++-
> 1 file changed, 191 inserti
MediaTek uses some glue logic to control frequency and power on some of
their GPUs. This is best exposed as a devfreq driver, as it saves us
from having to hardcode OPPs into the device tree, and can be extended
with additional devfreq-y logic like more clever governors that use the
hardware's GPUE
On Mon, Sep 08, 2025 at 02:32:28PM +0100, Tvrtko Ursulin wrote:
>
> On 08/09/2025 14:15, Luiz Otavio Mello wrote:
> > Move legacy BKL struct_mutex from drm_device to drm_i915_private, which
> > is the last remaining user.
> >
> > Signed-off-by: Luiz Otavio Mello
> > Reviewed-by: Rodrigo Vivi
>
This compatible is used for an SRAM section that's shared between the
MT8196's application processor cores and the embedded GPUEB MCU that
controls the GPU frequency.
Through this SRAM section, things about the GPU frequency controller
like the OPP table can be read.
Acked-by: Rob Herring (Arm)
On 9/12/2025 6:20 PM, Dmitry Baryshkov wrote:
> On Thu, Sep 11, 2025 at 10:55:06PM +0800, Xiangxu Yin wrote:
>> Parse TCSR registers to support DP mode signaling via dp_phy_mode_reg.
>> Move USB PHY-only register configuration from com_init to
>> qmp_usbc_usb_power_on.
> Two sets of changes. Two
We cannot know where the write pointer is, always reset position to
(0,0) before clearing display.
Signed-off-by: Marcus Folkesson
---
drivers/gpu/drm/sitronix/st7571-i2c.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sitronix/st7571-i2c.c
b/drivers/gpu/drm/sitronix/st757
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