add-mutex-to-protect-the-bridge-chain/20250927-000253
patch link:
https://lore.kernel.org/all/20250926-drm-bridge-alloc-encoder-chain-mutex-v1-4-23b62c473...@bootlin.com/
patch subject: [PATCH 4/7] drm/bridge: lock the encoder chain in scoped
for_each loops
in testcase: boot
config: x86_64-ran
On Tue, 30 Sept 2025 at 12:56, Himanshu Dewangan wrote:
>
> From: Nagaraju Siddineni
>
> Introduce a new Kconfig entry VIDEO_EXYNOS_MFC for the Samsung
> Exynos MFC driver that supports firmware version 13 and later.
> Extend the top‑level Samsung platform Kconfig to disable the legacy
> S5P‑MFC
GMU registers are always at a fixed offset from the GPU base address,
a consistency maintained at least within a given architecture generation.
In A8x family, the base address of the GMU has changed, but the offsets
of the gmu registers remain largely the same. To enable reuse of the gmu
code for A
Correct the register offset and enable this workaround for all A7x
and newer GPUs to match downstream. Also, downstream does this w/a after
moving the fence to allow mode. So do the same.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8
1 file changed, 4 inse
letions(-)
---
base-commit: 09c49a960070d0cdf79a593f3cccb830884f4c76
change-id: 20250929-kaana-gpu-support-11d21c8fa1dc
Best regards,
--
Akhil P Oommen
From: Nagaraju Siddineni
Introduce the device‑tree entries for the Samsung Exynos AUTO V920
multimedia‑function controller (MFC). The patch defines:
- Reserved memory regions for firmware and CMA buffers.
- Core0 and Core1 memory mappings.
- The main MFC node with basic properties (compatible, re
Use the new Tryfrom and Into derive macros to replace the boilerplate
code used for conversion between register fields types and the primitive
type they are represented in.
This removes a lot of boilerplate, with the only exception being fields
encoded as booleans which still need manual implement
From: Nagaraju Siddineni
- Enable HEVC, AV1, VP8/9, MPEG‑4 (incl. MVC, VC‑1 RCV) .
- Extend DPB/buffer structures for AV1 and high‑resolution/multiframe
streams.
- Add codec‑specific QoS weight parameters (10‑bit, 4:2:2, B‑frames)
and update DT bandwidth entries.
- Enhance format tables with
From: Nagaraju Siddineni
- Register H.264 format and V4L2/VB2 headers.
- Initialize encoder context, queues, and defaults.
- Add buffer‑control handling (layers, ROI, frame‑rate, drop,
profile/level) and parse DT properties.
- Register encoder ioctl ops, set up QoS table, and extend debugfs.
S
On Mon, Sep 29, 2025 at 01:10:17PM +0300, Imre Deak wrote:
> On Mon, Sep 29, 2025 at 12:00:03PM +0300, Dmitry Baryshkov wrote:
> > On Mon, Sep 29, 2025 at 09:36:44AM +0300, Imre Deak wrote:
> > > Add helpers to query the DP DSC sink device's per-slice throughput as
> > > well as a DSC branch device
From: Nagaraju Siddineni
- Integrat H.264 encoding.
- Allocate encoder‑specific context buffers and ROI memory.
- Add detection macro and broadened codec‑type validation for
QoS utilities.
- Introduce encoder‑aware QoS tables and refined weight calculations
(B‑frames, reference count).
- Upda
From: Nagaraju Siddineni
- Add for MPEG‑4, H.263, VP8/VP9, HEVC codec support with extended
contexts and buffer allocation.
- Implement LCU sizing, motion‑estimation buffers, and align
scratch buffers.
- Unify ROI buffer handling across all encoders.
- Register additional pixel formats (`mfc_
From: Nagaraju Siddineni
- Introduce a generic encoder‑parameter framework
(slice mode, ASO order, QP config, timestamp delta).
- Expose full V4L2 encoder controls (frame tag, RC limits,
level/profile, ROI, weighted prediction, hierarchical coding).
- Implemente ROI handling by building ROI r
From: Nagaraju Siddineni
Introduce new driver headers: mfc_buf.h, mfc_common.h,
mfc_media.h, mfc_mem.h, mfc_regs.h, mfc_sched.h, and mfc_utils.h.
mfc_buf.h
Define buffer allocation/release APIs, common driver constants,
video node identifiers, and feature‑specific V4L2 control IDs.
mfc_common.h
From: Nagaraju Siddineni
- Integrate encoder command API into core flow.
- Extend hardware‑lock handling for encoder state.
- Manage encoder resources on instance open/close.
- Add APIs for buffers, codec parameters, and status.
- Update core ops, macros, headers, and error handling.
Signed-off-
All MTL+ devices supports these correctable and non-fatal error
notification over the IRQ. None of current supported platforms
support error counter directly in the HW.
But since we are already supporting the error interrupt for
these errors, let's incorporate the counter inside the driver
itself
On Sun, 28 Sep 2025 17:50:20 +0300
Leon Romanovsky wrote:
> +static int validate_dmabuf_input(struct vfio_pci_core_device *vdev,
> + struct vfio_device_feature_dma_buf *dma_buf,
> + struct vfio_region_dma_range *dma_ranges,
> +
On 9/29/2025 8:28 AM, Alexandre Courbot wrote:
> On Sun Sep 21, 2025 at 3:22 AM JST, Joel Fernandes wrote:
>> Add support for custom visiblity to allow for users to control visibility
>> of the structure and helpers.
>>
>> Reviewed-by: Elle Rhumsaa
>> Signed-off-by: Joel Fernandes
>
> Just on
Make use of the new drm_gem_shmem_huge_mnt_create() and
drm_gem_shmem_huge_mnt_free() helpers to avoid code duplication.
drm_gem_shmem_huge_mnt_free() handles NULL pointers.
Signed-off-by: Loïc Molinari
---
drivers/gpu/drm/v3d/v3d_gemfs.c | 31 +++
1 file changed, 3
On Thu, Sep 25, 2025 at 3:54 PM Tamir Duberstein wrote:
>
> Changes in v2:
For future reference, this is v3.
Cheers,
Miguel
On 9/29/2025 8:16 AM, Alexandre Courbot wrote:
> On Sun Sep 21, 2025 at 3:22 AM JST, Joel Fernandes wrote:
>> The bitfield-specific into new macro. This will be used to define
>> structs with bitfields, similar to C language.
>>
>> Reviewed-by: Elle Rhumsaa
>> Signed-off-by: Joel Fernandes
>
On Fri, Sep 26, 2025 at 03:00:49PM -0500, Rob Herring (Arm) wrote:
> Add a driver for Arm Ethos-U65/U85 NPUs. The Ethos-U NPU has a
> relatively simple interface with single command stream to describe
> buffers, operation settings, and network operations. It supports up to 8
> memory regions (thoug
On Mon, 2025-09-29 at 05:40 -0400, Harry Wentland wrote:
>
>
> On 2025-09-19 08:42, Louis Chauvet wrote:
> >
> >
> > Le 18/09/2025 à 02:43, Nícolas F. R. A. Prado a écrit :
> > > Add a new cap that drivers can set to signal they support post-
> > > blend
> > > color pipelines.
> > >
> > > Sign
Now that we have DBANC framework and legacy connector functions removed,
handle the HDCP disabling in bridge atomic check rather than in connector
atomic check in !(DBANC) usecase.
Signed-off-by: Harikrishna Shenoy
---
.../drm/bridge/cadence/cdns-mhdp8546-core.c | 23 +++
1 fil
Hi Maxime,
On Mon, 29 Sep 2025 14:43:46 +0200
Maxime Ripard wrote:
> On Fri, Sep 26, 2025 at 05:59:42PM +0200, Luca Ceresoli wrote:
> > The per-encoder bridge chain is currently assumed to be static once it is
> > fully initialized. Work is in progress to add hot-pluggable bridges,
> > breaking
On Mon, Sep 29, 2025 at 4:34 PM Alexandre Courbot wrote:
>
> I think you will also need to explicitly enable the feature somewhere -
> for the kernel crate it is in `rust/kernel/lib.rs`, but Nova being a
> different crate I am not sure where we are supposed to do it...
`rust_allowed_features` in
Hi Maxime,
On Mon, 29 Sep 2025 14:45:10 +0200
Maxime Ripard wrote:
> On Fri, Sep 26, 2025 at 05:59:43PM +0200, Luca Ceresoli wrote:
> > drm_encoder_cleanup() modifies the encoder chain by removing bridges via
> > drm_bridge_detach(). Protect this whole operation by taking the mutex, so
> > any u
The LD070WX3 is a Color Active Matrix Liquid Crystal Display with an
integral Light Emitting Diode (LED) backlight system. The matrix employs
a-Si Thin Film Transistor as the active element. It is a transmissive type
display operating in the normally Black mode. This TFT-LCD has 7.0 inches
diagonal
On 2025-09-26 at 17:27 +1000, Alexandre Courbot wrote...
> On Mon Sep 22, 2025 at 8:30 PM JST, Alistair Popple wrote:
> > Initialise the GSP resource manager arguments (rmargs) which provide
> > initialisation parameters to the GSP firmware during boot. The rmargs
> > structure contains arguments
From: Anton Bambura
LTL106HL02 is a color active matrix TFT (Thin Film Transistor) liquid
crystal display (LCD) that uses amorphous silicon TFT as switching
devices. This model is composed of a TFT LCD panel, a driver circuit and a
backlight unit. The resolution of a 10.6" contains 1920 x 1080 pi
Document Samsung LTL106AL01 simple LVDS panel.
Signed-off-by: Svyatoslav Ryhel
---
.../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
b/Documentation/devicetree/b
On Mon Sep 29, 2025 at 9:39 AM CEST, Alistair Popple wrote:
> On 2025-09-29 at 17:06 +1000, Danilo Krummrich wrote...
>> On Mon Sep 29, 2025 at 2:19 AM CEST, Alistair Popple wrote:
>> > On 2025-09-26 at 22:00 +1000, Danilo Krummrich wrote...
>> >> On Tue Sep 23, 2025 at 6:29 AM CEST, Alistair Pop
On Fri, Sep 26, 2025 at 05:59:43PM +0200, Luca Ceresoli wrote:
> drm_encoder_cleanup() modifies the encoder chain by removing bridges via
> drm_bridge_detach(). Protect this whole operation by taking the mutex, so
> any users iterating over the chain will not access it during the change.
>
> Signe
On Mon, Sep 29, 2025 at 10:25:06AM +0200, Thomas Hellström wrote:
> > > 2) dma-buf pcie-p2p allows transparent fallback to system memory
> > > dma-
> > > buf. I think that is a good thing to keep even for other
> > > interconnects
> > > (if possible). Like if someone wants to pull the network cable
Il 29/09/25 09:46, Nicolas Frattaroli ha scritto:
Various MediaTek SoCs use GPU integration silicon named "MFlexGraphics"
by MediaTek. On the MT8196 and MT6991 SoCs, interacting with this
integration silicon is required to power on the GPU.
This glue silicon is in the form of an embedded microco
On Mon, 29 Sep 2025, Chu Guangqing wrote:
> diff --git a/drivers/gpu/drm/yhgch/yhgch_drm_vdac.c
> b/drivers/gpu/drm/yhgch/yhgch_drm_vdac.c
> new file mode 100644
> index ..2e222af29f69
> --- /dev/null
> +++ b/drivers/gpu/drm/yhgch/yhgch_drm_vdac.c
> @@ -0,0 +1,134 @@
> +// SPDX-Licens
On Mon, Sep 29, 2025 at 01:12:15PM +0300, Ville Syrjälä wrote:
> On Mon, Sep 29, 2025 at 09:36:44AM +0300, Imre Deak wrote:
> > Add helpers to query the DP DSC sink device's per-slice throughput as
> > well as a DSC branch device's overall throughput and line-width
> > capabilities.
> >
> > v2 (Vi
On Mon, Sep 29, 2025 at 09:36:44AM +0300, Imre Deak wrote:
> Add helpers to query the DP DSC sink device's per-slice throughput as
> well as a DSC branch device's overall throughput and line-width
> capabilities.
>
> v2 (Ville):
> - Rename pixel_clock to peak_pixel_rate, document what the value me
With the DBANC framework, the connector is no longer initialized in
bridge_attach()when the display controller sets the
DRM_BRIDGE_ATTACH_NO_CONNECTOR flag.
This causes a null pointer dereference in cdns_mhdp_modeset_retry_fn()
when trying to access &conn->dev->mode_config.mutex.
Observed on a
On 29.09.25 10:16, Thomas Hellström wrote:
> On Fri, 2025-09-26 at 13:00 -0300, Jason Gunthorpe wrote:
>> On Fri, Sep 26, 2025 at 04:51:29PM +0200, Christian König wrote:
>>> On 26.09.25 16:41, Jason Gunthorpe wrote:
On Fri, Sep 26, 2025 at 03:51:21PM +0200, Thomas Hellström wrote:
>
Various MediaTek SoCs use GPU integration silicon named "MFlexGraphics"
by MediaTek. On the MT8196 and MT6991 SoCs, interacting with this
integration silicon is required to power on the GPU.
This glue silicon is in the form of an embedded microcontroller running
special-purpose firmware, which aut
As it stands, panthor keeps a cached current frequency value for when it
wants to retrieve it. This doesn't work well for when things might
switch frequency without panthor's knowledge.
Instead, implement the get_cur_freq operation, and expose it through a
helper function to the rest of panthor.
On the MT8196 and MT6991 SoCs, the GPU power and frequency is controlled
by some integration logic, referred to as "MFlexGraphics" by MediaTek,
which comes in the form of an embedded controller running
special-purpose firmware.
This controller takes care of the regulators and PLL clock frequencies
The MediaTek MT8196 SoC includes an embedded MCU referred to as "GPUEB",
acting as glue logic to control power and frequency of the Mali GPU.
This MCU runs special-purpose firmware for this use, and the main
application processor communicates with it through a mailbox.
Add a binding that describes
This series introduces two new drivers to accomplish controlling the
frequency and power of the Mali GPU on MediaTek MT8196 SoCs.
The reason why it's not as straightforward as with other SoCs is that
the MT8196 has quite complex glue logic in order to squeeze the maximum
amount of performance poss
On 2025-09-29 at 17:06 +1000, Danilo Krummrich wrote...
> On Mon Sep 29, 2025 at 2:19 AM CEST, Alistair Popple wrote:
> > On 2025-09-26 at 22:00 +1000, Danilo Krummrich wrote...
> >> On Tue Sep 23, 2025 at 6:29 AM CEST, Alistair Popple wrote:
> >> > On 2025-09-23 at 12:16 +1000, John Hubbard wro
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