On 11.10.2017 13:13, Daniel Stone wrote:
I'm sorry, but this is not the right way to go about things. If Xorg
or GNOME Shell or Weston or whatever thinks the monitor is DPMS-off,
the fact that someone else has forcibly switched it back on will not
make them continue painting.
User should disab
On 11.10.2017 12:04, Daniel Vetter wrote:
Why exactly is the existing dpms ioctl not good enough? it's implemented
as the "DPMS" property attached to connectors, but that's the only
difference compared to your code here.
Also, that one doesn't have any XXX about atomic like yours.
I also hav
don't implement DPMS at all and
at the same time have TTY switch broken.
Signed-off-by: Alex Ivanov
---
drivers/gpu/drm/drm_crtc_internal.h | 2 ++
drivers/gpu/drm/drm_ioctl.c | 1 +
drivers/gpu/drm/drm_mode_object.c | 41 +
include/uapi/drm/
01.10.2013, 18:16, "Konrad Rzeszutek Wilk" :
> On Tue, Oct 01, 2013 at 12:16:16PM +0200, Thomas Hellstrom wrote:
>
>> Jerome, Konrad
>>
>> Forgive an ignorant question, but it appears like both Nouveau and
>> Radeon may use pci_map_page() when populating TTMs on
>> pages obtained using the ordi
Let's go futher.
25.09.2013, 22:58, "Alex Ivanov" :
> 25.09.2013, 21:28, "Konrad Rzeszutek Wilk" :
>> I took a look at the arch/parisc/kernel/pci-dma.c and I see that
>> is mostly a flat platform. That is bus addresses == physical addresses.
>>
Alex,
> You'd want to add the add the flush to r100_ring_test() in r100.c.
> radeon_cp.c is for the old UMS support.
Right!
Konrad,
Thanks for the code! I'll try asap.
25.09.2013, 21:28, "Konrad Rzeszutek Wilk" :
> I took a look at the arch/parisc/kernel/pci-dma.c and I see that
> is mostly a f
24.09.2013, 00:11, "Konrad Rzeszutek Wilk" :
> On Sat, Sep 21, 2013 at 07:39:10AM +0400, Alex Ivanov wrote:
>
>> 21.09.2013, в 1:27, Alex Deucher написал(а):
>>> The register writes seems to be going through the register backbone
>>> correctly:
>&g
P.S.: don't run means don't allow to run, by either feeding radeon.test=X
or radeon.benchmark=1
22.09.2013, в 5:18, Alex Ivanov написал(а):
> 20.09.2013, в 22:33, Alex Deucher написал(а):
>
>> On Fri, Sep 20, 2013 at 9:36 AM, Alex Ivanov wrote:
>>> Prevent N
20.09.2013, в 22:33, Alex Deucher написал(а):
> On Fri, Sep 20, 2013 at 9:36 AM, Alex Ivanov wrote:
>> Prevent NULL pointer dereference in case when radeon_ring_fini() did it's
>> job.
>>
>> Reading of r100_cp_ring_info and radeon_ring_gfx debugfs entries will
21.09.2013, в 1:27, Alex Deucher написал(а):
> On Tue, Sep 17, 2013 at 3:33 PM, Alex Ivanov wrote:
>> 17.09.2013, в 18:24, Alex Deucher написал(а):
>>
>>> On Tue, Sep 17, 2013 at 5:23 AM, Alex Ivanov wrote:
>>>> Alex,
>>>>
>>>> 10
tch(0x8504)=0xCAFEDEAD)" issue.
Signed-off-by: Alex Ivanov
---
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 2417571..413cdd1 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -2933,10 +2933,11 @@ static int r100_debugfs_cp_r
17.09.2013, в 23:33, Alex Ivanov написал(а):
> 17.09.2013, в 18:24, Alex Deucher написал(а):
>
>> On Tue, Sep 17, 2013 at 5:23 AM, Alex Ivanov wrote:
>>> Alex,
>>>
>>> 10.09.2013, в 16:37, Alex Deucher написал(а):
>>>
>>>> The du
17.09.2013, в 18:24, Alex Deucher написал(а):
> On Tue, Sep 17, 2013 at 5:23 AM, Alex Ivanov wrote:
>> Alex,
>>
>> 10.09.2013, в 16:37, Alex Deucher написал(а):
>>
>>> The dummy page isn't really going to help much. That page is just
>>>
ing pages for the gart.
> You may want to look there.
Ah, sorry. Indeed. Though, my idea with:
On Tue, Sep 10, 2013 at 5:20 AM, Alex Ivanov wrote:
> Thanks! I'll try. Meanwhile i've tried a switch from page_alloc() to
> dma_alloc_coherent() in radeon_dummy_page_*(), which di
Alex,
09.09.2013, в 21:43, Alex Deucher написал(а):
> On Mon, Sep 9, 2013 at 12:44 PM, Alex Ivanov wrote:
>> Folks,
>>
>> We (people at linux-parisc @ vger.kernel.org mail list) are trying to make
>> native video options of the latest PA-RISC servers and workstatio
the chipset time to flush its internal write buffers to
memory.
There are two register fields that control this mechanism:
PRE_WRITE_TIMER and PRE_WRITE_LIMIT.
In the radeon DRM codebase I didn't found anyone using/setting
those registers. Maybe PA-RISC has some problem here?...&
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