Re: [PATCH v2 17/26] drm/rockchip: dw-mipi-dsi: don't enable PHY PLL until it's configured

Hi John This patch do the similar thing with https://patchwork.kernel.org/patch/9530405/ They are changing the phy configuration order, my suggestion is to merge them. On 01/22/2017 12:31 AM, John Keeping wrote: Signed-off-by: John Keeping --- Unchanged in v2 ---

Re: [PATCH v2 14/26] drm/rockchip: dw-mipi-dsi: fix escape clock rate

Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: Use the same calculation as the vendor kernel to derive the escape clock speed. Signed-off-by: John Keeping <j...@metanate.com> --- Unchanged in v2 --- drivers/gpu/drm/rockchip/dw-mi

Re: [PATCH v2 15/26] drm/rockchip: dw-mipi-dsi: ensure PHY is reset

Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: Also don't power up the DSI host at this point since this is not necessary in order to configure the PHY and we do so later when selecting video or command mode. Signed-off-by: John Keep

Re: [PATCH v2 13/26] drm/rockchip: dw-mipi-dsi: allow commands in panel_disable

l be driven -* normally when the display is enabled again later. -*/ - msleep(120); - - dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE); This workaround is from[0], I also think it should be deleted. [0] http://www.spinics.net/lists/dri-devel/msg77192.html Revi

Re: [PATCH v2 12/26] drm/rockchip: dw-mipi-dsi: prepare panel after phy init

Hi John Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: Some panels need to be configured with commands sent over the MIPI link, which they will do in the prepare hook. Call this after the PHY has been initialized so that we are able to send co

Re: [PATCH v2 11/26] drm/rockchip: dw-mipi-dsi: don't assume buffer is aligned

Hi John Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: By dereferencing the MIPI command buffer as a u32* we rely on it being correctly aligned on ARM, but this may not be the case. Copy it into a stack variable that will be correctly a

Re: [PATCH v2 10/26] drm/rockchip: dw-mipi-dsi: only request HS clock when required

Hi John Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: Requesting the HS clock from the PHY before we initialize it causes an invalid signal to be sent out since the input clock is not yet configured. The PHY databook suggests only ass

Re: [PATCH v2 09/26] drm/rockchip: dw-mipi-dsi: respect message flags

Hi John Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: Instead of always sending commands in LP mode, respect the MIPI_DSI_MSG_USE_LPM flag to decide how to send each message. Also request acks if MIPI_DSI_MSG_REQ_ACK is set. Signed-off-by

Re: [PATCH v2 08/26] drm/rockchip: dw-mipi-dsi: include bad value in error message

Hi John Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: As an aid to debugging. Signed-off-by: John Keeping <j...@metanate.com> --- Unchanged in v2 --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 3 ++- 1 file changed, 2 insertions(+)

Re: [PATCH v2 07/26] drm/rockchip: dw-mipi-dsi: avoid out-of-bounds read on tx_buf

Hi John Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: As a side-effect of this, encode the endianness explicitly rather than casting a u16. Signed-off-by: John Keeping <j...@metanate.com> --- Unchanged in v2 --- drivers/gpu/drm/rock

Re: [PATCH v2 06/26] drm/rockchip: dw-mipi-dsi: fix generic packet status check

Hi John Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: We want to check that both the GEN_CMD_EMPTY and GEN_PLD_W_EMPTY bits are set so we can't just check "val & mask" because that will be true if either bit is set. Acco

Re: [PATCH v2 04/26] drm/rockchip: dw-mipi-dsi: remove mode_set hook

Hi John Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: This is not needed since we can access the mode via the CRTC from the enable hook. Also remove the "mode" field that is no longer used. Signed-off-by: John Keeping <j...@me

Re: [PATCH v2 03/26] drm/rockchip: dw-mipi-dsi: pass mode in where needed

Hi John Reviewed-by: Chris Zhong <z...@rock-chips.com> On 01/22/2017 12:31 AM, John Keeping wrote: This shows that we only use the mode from the enable function and prepares us to remove the "mode" field and the mode_set hook in the next commit. Signed-off-by: John Keeping &l

Re: [PATCH v2 01/26] drm/rockchip: dw-mipi-dsi: don't configure hardware in mode_set for MIPI

Hi John On 01/22/2017 12:31 AM, John Keeping wrote: With atomic modesetting the hardware will be powered off when the mode_set function is called. We should configure the hardware in the commit function (or even the enable function, but switching from commit to enable is left for a future

Re: [PATCH v2 26/26] drm/rockchip: dw-mipi-dsi: support read commands

Hi John On 01/22/2017 12:31 AM, John Keeping wrote: I haven't found any method for getting the length of a response, so this just uses the requested rx_len Signed-off-by: John Keeping --- Unchanged in v2 --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 54

Re: [PATCH v2 18/26] drm/rockchip: dw-mipi-dsi: properly configure PHY timing

On 01/22/2017 12:31 AM, John Keeping wrote: These values are specified as constant time periods but the PHY configuration is in terms of the current lane byte clock so using constant values guarantees that the timings will be outside the specification with some display configurations. Derive

[PATCH v3 4/5] dt-bindings: add power domain node for dw-mipi-rockchip

Signed-off-by: Chris Zhong <z...@rock-chips.com> Acked-by: Rob Herring <r...@kernel.org> --- Changes in v3: None .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/disp

[PATCH v3 3/5] drm/rockchip/dsi: remove mode_valid function

The MIPI DSI do not need check the validity of resolution, the max resolution should depend VOP. Hence, remove rk3288_mipi_dsi_mode_valid here. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v3: None drivers/gpu/drm/rockchip/dw-mipi-dsi.

[PATCH v3 5/5] drm/rockchip/dsi: add dw-mipi power domain support

Reference the power domain incase dw-mipi power down when in use. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v3: None drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 16 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-ds

[PATCH v3 1/5] dt-bindings: add rk3399 support for dw-mipi-rockchip

The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has additional phy config clock. Signed-off-by: Chris Zhong <z...@rock-chips.com> Acked-by: Rob Herring <r...@kernel.org> --- Changes in v3: None .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt

[PATCH v3 0/5] Rockchip dw-mipi-dsi driver

/patch/9340251 [25/26] https://patchwork.kernel.org/patch/9340127 [26/26] https://patchwork.kernel.org/patch/9340139 Changes in v3: - base on John Keeping's patch series Chris Zhong (5): dt-bindings: add rk3399 support for dw-mipi-rockchip drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi

[PATCH v3 2/5] drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi

The vopb/vopl switch register of RK3399 mipi is different from RK3288, the default setting for mipi dsi mode is different too, so add a of_device_id structure to distinguish them, and make sure set the correct mode before mipi phy init. Signed-off-by: Chris Zhong <z...@rock-chips.com> Sign

Re: [01/26] drm/rockchip: dw-mipi-dsi: use mode from display state

On 09/20/2016 01:17 AM, John Keeping wrote: There is no need to keep a pointer to the mode around since we know it will be present in the connector state. Signed-off-by: John Keeping --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 31 --- 1 file

Re: [05/26] drm/rockchip: dw-mipi-dsi: fix command header writes

same as https://patchwork.kernel.org/patch/9518417/ Tested-by: Chris Zhong <z...@rock-chips.com> Reviewed-by: Chris Zhong <z...@rock-chips.com> On 09/20/2016 01:17 AM, John Keeping wrote: In a couple of places here we use "val" for the value that is about to be

Re: [PATCH v2 11/11] drm/rockchip/dsi: fix insufficient bandwidth of some panel

Hi John On 01/16/2017 08:44 PM, John Keeping wrote: On Mon, 16 Jan 2017 18:08:31 +0800, Chris Zhong wrote: Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough for some panel, it will cause the screen display is not normal, so increases the badnwidth to 1 / 0.8. Signed-off

[PATCH v2 08/11] drm/rockchip/dsi: fix the issue can not send commands

chips.com> Signed-off-by: Chris Zhong <z...@rock-chips.com> --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 26 +- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index 4ec82

[PATCH v2 09/11] drm/rockchip/dsi: decrease the value of Ths-prepare

From: xubilv <x...@rock-chips.com> Signed-off-by: xubilv <x...@rock-chips.com> Signed-off-by: Chris Zhong <z...@rock-chips.com> --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-ds

[PATCH v2 07/11] drm/rockchip/dsi: fix mipi display can't found at init time

<mark@rock-chips.com> Signed-off-by: Chris Zhong <z...@rock-chips.com> --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 57 +++--- 1 file changed, 39 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/d

[PATCH v2 10/11] drm/rockchip/dsi: fix phy clk lane stop state timeout

Before phy init, the detection of phy state should be controlled manually. After that, we can switch the detection to hardward, it is automatic. Hence move PHY_TXREQUESTCLKHS setting to the end of phy init. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- drivers/gpu/drm/rockchip/d

[PATCH v2 11/11] drm/rockchip/dsi: fix insufficient bandwidth of some panel

Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough for some panel, it will cause the screen display is not normal, so increases the badnwidth to 1 / 0.8. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++-- 1 file chan

[PATCH v2 05/11] drm/rockchip/dsi: add dw-mipi power domain support

Reference the power domain incase dw-mipi power down when in use. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 17 + 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/ro

[PATCH v2 06/11] drm/rockchip/dsi: return probe defer if attach panel failed

From: Mark Yao <mark@rock-chips.com> Return -EINVAL would cause mipi dsi bad behavior, probe defer to ensure mipi find the correct mode, Signed-off-by: Mark Yao <mark@rock-chips.com> Signed-off-by: Chris Zhong <z...@rock-chips.com> --- drivers/gpu/drm/rockchip/

[PATCH v2 04/11] dt-bindings: add power domain node for dw-mipi-rockchip

Signed-off-by: Chris Zhong <z...@rock-chips.com> Acked-by: Rob Herring <r...@kernel.org> --- .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_

[PATCH v2 03/11] drm/rockchip/dsi: remove mode_valid function

The MIPI DSI do not need check the validity of resolution, the max resolution should depend VOP. Hence, remove rk3288_mipi_dsi_mode_valid here. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 39 -- 1 file chang

[PATCH v2 02/11] drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi

The vopb/vopl switch register of RK3399 mipi is different from RK3288, the default setting for mipi dsi mode is different too, so add a of_device_id structure to distinguish them, and make sure set the correct mode before mipi phy init. Signed-off-by: Chris Zhong <z...@rock-chips.com> Sign

[PATCH v2 01/11] dt-bindings: add rk3399 support for dw-mipi-rockchip

The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has additional phy config clock. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff

[PATCH v15.1 3/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399

Hi Mark OK, thanks. I will send the whole series next time, hope it will not bother anyone On 09/12/2016 05:13 PM, Mark Brown wrote: > On Fri, Sep 09, 2016 at 09:16:06PM -0700, Chris Zhong wrote: >> Add support for cdn DP controller which is embedded in the rk3399 >> SoCs. The

[PATCH v15.1 3/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/rockchip/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong Signed-off-by: Sean Paul Reviewed-by: Sean Paul Acked-by: Mark Yao --- Changes

[PATCH v15 4/5] drm/rockchip: cdn-dp: support audio hot-plug

Issue hot-plug detection, EDID update, and ELD update notifications from DP drivers. Signed-off-by: Chris Zhong --- Changes in v15: None Changes in v14: None Changes in v13: None Changes in v12: None Changes in v11: None Changes in v10: None Changes in v9: None Changes in v8: None Changes in v7

[PATCH v15 3/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/rockchip/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong Signed-off-by: Sean Paul Reviewed-by: Sean Paul Acked-by: Mark Yao --- Changes

[PATCH v15 0/5] Rockchip Type-C DisplayPort driver

() - correct the commit message Changes in v1: - add extcon node description - add #sound-dai-cells description - use extcon API - use hdmi-codec for the DP Asoc - do not initialize the "ret" - printk a err log when drm_of_encoder_active_endpoint_id - modify the dclk pin_pol to

[PATCH 1/2] drm/rockchip: cdn-dp: support audio hot-plug

Issue hot-plug detection, EDID update, and ELD update notifications from DP drivers. Signed-off-by: Chris Zhong --- drivers/gpu/drm/rockchip/cdn-dp-core.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c

[PATCH 0/2] Add DP dai-links to the rk3399-gru machine driver

/8887261/ https://patchwork.kernel.org/patch/8887251/ Chris Zhong (2): drm/rockchip: cdn-dp: support audio hot-plug ASoC: rockchip: Add DP dai-links to the rk3399-gru machine driver .../bindings/sound/rockchip,rk3399-gru-sound.txt | 13 +++--- drivers/gpu/drm/rockchip/cdn-dp-core.c

[v14.2 PATCH 5/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/rockchip/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong Reviewed-by: Sean Paul Acked-by: Mark Yao --- Changes in v14.2: - Modify some

[v14.1 PATCH 5/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/rockchip/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong Reviewed-by: Sean Paul Acked-by: Mark Yao --- Changes in v14.1: - power on the power

[v14 PATCH 5/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/rockchip/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong Reviewed-by: Sean Paul Acked-by: Mark Yao --- Changes in v14: - change super speed

[v14 PATCH 0/5] Rockchip Type-C and DisplayPort driver

API - use hdmi-codec for the DP Asoc - do not initialize the "ret" - printk a err log when drm_of_encoder_active_endpoint_id - modify the dclk pin_pol to a single line Chris Zhong (5): Documentation: bindings: add dt doc for Rockchip USB Type-C PHY phy: Add USB Type-C PHY d

[v13 PATCH 5/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/rockchip/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong Reviewed-by: Sean Paul Acked-by: Mark Yao --- Changes in v13: - support suspend

[v13 PATCH 0/5] Rockchip Type-C and DisplayPort driver

clk_get(>dev, "tcpdcore") - add extcon node description - add #sound-dai-cells description - use extcon API - use hdmi-codec for the DP Asoc - do not initialize the "ret" - printk a err log when drm_of_encoder_active_endpoint_id - modify the dclk pin_pol to a single line Chris Zhong

[PATCH v12 PATCH 5/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/rockchip/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong Reviewed-by: Sean Paul Acked-by: Mark Yao --- Changes in v12: - use

[PATCH v12 PATCH 0/5] Rockchip Type-C and DisplayPort driver

clk_get(>dev, "tcpdcore") - add extcon node description - add #sound-dai-cells description - use extcon API - use hdmi-codec for the DP Asoc - do not initialize the "ret" - printk a err log when drm_of_encoder_active_endpoint_id - modify the dclk pin_pol to a single line Chris Zhong

[RESEND PATCH v11 PATCH 5/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/rockchip/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong Reviewed-by: Sean Paul Acked-by: Mark Yao --- Changes in v11: - add best_encoder back

[RESEND PATCH v11 PATCH 0/5] Rockchip Type-C and DisplayPort driver

a err log when drm_of_encoder_active_endpoint_id - modify the dclk pin_pol to a single line Chris Zhong (5): Documentation: bindings: add dt doc for Rockchip USB Type-C PHY phy: Add USB Type-C PHY driver for rk3399 arm64: dts: rockchip: add Type-C phy for RK3399 Documentation: bindings: add dt d

[PATCH v11 PATCH 5/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/rockchip/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong Reviewed-by: Sean Paul Acked-by: Mark Yao --- Changes in v11: - add best_encoder back

[PATCH v11 PATCH 0/5] Rockchip Type-C and DisplayPort driver

ove ADDR_ADJ define - use devm_clk_get(>dev, "tcpdcore") - add extcon node description - add #sound-dai-cells description - use extcon API - use hdmi-codec for the DP Asoc - do not initialize the "ret" - printk a err log when drm_of_encoder_active_endpoint_id - modify the dclk pi

[v10.2 PATCH 5/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/rockchip/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong Reviewed-by: Sean Paul Acked-by: Mark Yao --- Changes in v10.2: - remove best_encoder

[v10 PATCH 0/5] Rockchip Type-C and DisplayPort driver

Hi Chanwoo On 08/10/2016 08:37 AM, Chanwoo Choi wrote: > Hi Chris, > > On 2016년 08월 10일 08:32, Chris Zhong wrote: >> Hi all >> >> This series patch is for rockchip Type-C phy and DisplayPort controller >> driver. >> >> The USB Type-C PHY is des

[v10.1 PATCH 5/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/rockchip/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong Reviewed-by: Sean Paul Acked-by: Mark Yao --- Changes in v10.1: - support read sink

[v10 PATCH 5/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/rockchip/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong Reviewed-by: Sean Paul Acked-by: Mark Yao --- Changes in v10: - control the grf_clk

[v10 PATCH 4/5] Documentation: bindings: add dt documentation for cdn DP controller

This patch adds a binding that describes the cdn DP controller for rk3399. Signed-off-by: Chris Zhong Acked-by: Rob Herring --- Changes in v10: - add pclk_vio_grf clock Changes in v9: - modify the reference phy = < 0>, < 0>; Changes in v8: None Changes in v7: None Changes

[v10 PATCH 0/5] Rockchip Type-C and DisplayPort driver

API - use hdmi-codec for the DP Asoc - do not initialize the "ret" - printk a err log when drm_of_encoder_active_endpoint_id - modify the dclk pin_pol to a single line Chris Zhong (5): Documentation: bindings: add dt doc for Rockchip USB Type-C PHY phy: Add USB Type-C PHY d

[v9 PATCH 6/6] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/rockchip/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong Reviewed-by: Sean Paul Acked-by: Mark Yao --- Changes in v9: - do not need reset

[v9 PATCH 5/6] Documentation: bindings: add dt documentation for cdn DP controller

This patch adds a binding that describes the cdn DP controller for rk3399. Signed-off-by: Chris Zhong Acked-by: Rob Herring --- Changes in v9: - modify the reference phy = < 0>, < 0>; Changes in v8: None Changes in v7: None Changes in v6: - add assigned-clocks and assigned-clock

[v9 PATCH 0/6] Rockchip Type-C and DisplayPort driver

get clk failed - remove ADDR_ADJ define - use devm_clk_get(>dev, "tcpdcore") - add extcon node description - add #sound-dai-cells description - use extcon API - use hdmi-codec for the DP Asoc - do not initialize the "ret" - printk a err log when drm_of_encoder_active_endpoin

[v8 PATCH 6/6] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/rockchip/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong Reviewed-by: Sean Paul Acked-by: Mark Yao --- Changes in v8: - optimization the err

[v8 PATCH 5/6] Documentation: bindings: add dt documentation for cdn DP controller

This patch adds a binding that describes the cdn DP controller for rk3399. Signed-off-by: Chris Zhong Acked-by: Rob Herring --- Changes in v8: None Changes in v7: None Changes in v6: - add assigned-clocks and assigned-clock-rates - add power-domains Changes in v5: None Changes in v4: - add

[v8 PATCH 0/6] Rockchip Type-C and DisplayPort driver

iled - remove ADDR_ADJ define - use devm_clk_get(>dev, "tcpdcore") - add extcon node description - add #sound-dai-cells description - use extcon API - use hdmi-codec for the DP Asoc - do not initialize the "ret" - printk a err log when drm_of_encoder_active_endpoint_id

[v7 PATCH 6/6] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/rockchip/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong Reviewed-by: Sean Paul Acked-by: Mark Yao --- Changes in v7: - support firmware

[v7 PATCH 5/6] Documentation: bindings: add dt documentation for cdn DP controller

This patch adds a binding that describes the cdn DP controller for rk3399. Signed-off-by: Chris Zhong Acked-by: Rob Herring --- Changes in v7: None Changes in v6: - add assigned-clocks and assigned-clock-rates - add power-domains Changes in v5: None Changes in v4: - add a reset node

[v7 PATCH 0/6] Rockchip Type-C and DisplayPort driver

dd #sound-dai-cells description - use extcon API - use hdmi-codec for the DP Asoc - do not initialize the "ret" - printk a err log when drm_of_encoder_active_endpoint_id - modify the dclk pin_pol to a single line Chris Zhong (6): extcon: Add EXTCON_DISP_DP and the property for USB Typ

[v6.1 PATCH 6/6] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/rockchip/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong Reviewed-by: Sean Paul Acked-by: Mark Yao --- Changes in v6.1: - correct the path

[v6 PATCH 6/6] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/cdn/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong Reviewed-by: Sean Paul --- Changes in v6: - add a port struct - select SND_SOC_HDMI_CODEC

[v6 PATCH 5/6] Documentation: bindings: add dt documentation for cdn DP controller

This patch adds a binding that describes the cdn DP controller for rk3399. Signed-off-by: Chris Zhong Acked-by: Rob Herring --- Changes in v6: - add assigned-clocks and assigned-clock-rates - add power-domains Changes in v5: None Changes in v4: - add a reset node - support 2 phys Changes

[v6 PATCH 0/6] Rockchip Type-C and DisplayPort driver

not initialize the "ret" - printk a err log when drm_of_encoder_active_endpoint_id - modify the dclk pin_pol to a single line Chris Zhong (6): extcon: Add Type-C and DP support Documentation: bindings: add dt doc for Rockchip USB Type-C PHY phy: Add USB Type-C PHY driver for rk3399 arm64: dts: rockchip: a

[v5.2 PATCH 5/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/cdn/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong --- Changes in v5.2: - fixed the fw_wait always 0 Changes in v5.1: - modify according

[v5.1 PATCH 5/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/cdn/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong --- Changes in v5.1: - modify according to Sean Paul's comments Changes in v5

[v5 PATCH 5/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399

Hi Sean Thanks for your detailed review. I'm working to modify most of code according to comment. And there is reply for some comment On 07/13/2016 09:59 PM, Sean Paul wrote: > On Tue, Jul 12, 2016 at 8:09 AM, Chris Zhong wrote: >> Add support for cdn DP controller which is

[v5 PATCH 5/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/cdn/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong --- Changes in v5: - alphabetical order - do not use long, use u32 or u64 - return

[v5 PATCH 4/5] Documentation: bindings: add dt documentation for cdn DP controller

This patch adds a binding that describes the cdn DP controller for rk3399. Signed-off-by: Chris Zhong Acked-by: Rob Herring --- Changes in v5: None Changes in v4: - add a reset node - support 2 phys Changes in v3: - add SoC specific compatible string - remove reg = <1>; Changes in v2

[v5 PATCH 0/5] Rockchip Type-C and DisplayPort driver

lize the "ret" - printk a err log when drm_of_encoder_active_endpoint_id - modify the dclk pin_pol to a single line Chris Zhong (5): extcon: Add Type-C and DP support Documentation: bindings: add dt doc for Rockchip USB Type-C PHY phy: Add USB Type-C PHY driver for rk3399 Documentation: bindings: add dt documen

[PATCH 7/7] drm/rockchip: dw-mipi: fix insufficient bandwidth of some panel

Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough for some panel, it will cause the screen display is not normal, so increases the badnwidth to 1 / 0.8. Signed-off-by: Chris Zhong --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2

[PATCH 6/7] drm/rockchip: dw-mipi: fix phy clk lane stop state timeout

Before phy init, the detection of phy state should be controlled manually. After that, we can switch the detection to hardward, it is automatic. Hence move PHY_TXREQUESTCLKHS setting to the end of phy init. Signed-off-by: Chris Zhong --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 3 ++- 1 file

[PATCH 5/7] drm/rockchip: dw-mipi: support HPD poll

At the first time of bind, there is no any panel attach in mipi. Add a DRM_CONNECTOR_POLL_HPD porperty to detect the panel status, when panel probe, the dw_mipi_dsi_host_attach would be called, then mipi-dsi will trigger a event to notify the drm framework. Signed-off-by: Chris Zhong

[PATCH 4/7] drm/rockchip: dw-mipi: add dw-mipi power domain support

Reference the power domain incase dw-mipi power down when in use. Signed-off-by: Chris Zhong --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 17 + 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index

[PATCH 3/7] dt-bindings: add power domain node for dw-mipi-rockchip

Signed-off-by: Chris Zhong --- .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt| 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip

[PATCH 2/7] DRM: mipi: support rk3399 mipi dsi

The vopb/vopl switch register of rk3399 mipi is different from rk3288, the default setting for mipi dsi mode is different too, so add a of_device_id structure to distinguish them, and make sure set the correct mode before mipi phy init. Signed-off-by: Chris Zhong Signed-off-by: Mark Yao

[PATCH 1/7] dt-bindings: add rk3399 support for dw-mipi-rockchip

The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has additional phy config clock. Signed-off-by: Chris Zhong --- .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt| 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings

[PATCH 0/7] Rockchip dw-mipi-dsi driver

Hi all This is a bunch of dw-mipi-dsi driver for RK3399 and RK3288, they have been tested on rk3399 and rk3288 evb board. This series is based on Mark Yao's branch: https://github.com/markyzq/kernel-drm-rockchip/tree/drm-rockchip-next-2016-05-23 Chris Zhong (7): dt-bindings: add rk3399

[v4 PATCH 5/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/cdn/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong --- Changes in v4: - use phy framework to control DP phy - support 2 phys Changes in v3

[v4 PATCH 4/5] Documentation: bindings: add dt documentation for cdn DP controller

This patch adds a binding that describes the cdn DP controller for rk3399. Signed-off-by: Chris Zhong Acked-by: Rob Herring --- Changes in v4: - add a reset node - support 2 phys Changes in v3: - add SoC specific compatible string - remove reg = <1>; Changes in v2: None Changes in v1:

[v4 PATCH 0/5] Rockchip Type-C and DispplayPort driver

con API - use hdmi-codec for the DP Asoc - do not initialize the "ret" - printk a err log when drm_of_encoder_active_endpoint_id - modify the dclk pin_pol to a single line Chris Zhong (5): extcon: Add Type-C and DP support Documentation: bindings: add dt doc for Rockchip USB Type-C PH

[v3 PATCH 5/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/cdn/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong --- Changes in v3: - use EXTCON_DISP_DP and EXTCON_DISP_DP_ALT cable to get dp port state

[v3 PATCH 4/5] Documentation: bindings: add dt documentation for cdn DP controller

This patch adds a binding that describes the cdn DP controller for rk3399. Signed-off-by: Chris Zhong --- Changes in v3: - add SoC specific compatible string - remove reg = <1>; Changes in v2: None Changes in v1: - add extcon node description - add #sound-dai-cells description .../bi

[v3 PATCH 0/5] Rockchip Type-C and DispplayPort driver

description - add #sound-dai-cells description - use extcon API - use hdmi-codec for the DP Asoc - do not initialize the "ret" - printk a err log when drm_of_encoder_active_endpoint_id - modify the dclk pin_pol to a single line Chris Zhong (5): extcon: Add Type-C and DP support Documentation:

[v1,4/4] drm/rockchip: cdn-dp: add cdn DP support for rk3399

Hi Guenter Thanks for your comments On 06/09/2016 06:13 AM, Guenter Roeck wrote: >> +if (ret < 0) { >> >+ dev_err(dp->dev, "failed to request firmware %d\n", ret); >> >+ return ret; >> >+ } >> >+ >> >+ hdr = (struct cdn_firmware_header *)fw->data; >> >+ if (fw->size

[v2 PATCH 4/4] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/cdn/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong --- Changes in v2: - Alphabetic order - remove excess error message - use define clk_rate

[v2 PATCH 3/4] Documentation: bindings: add dt documentation for cdn DP controller

This patch adds a binding that describes the cdn DP controller for rk3399. Signed-off-by: Chris Zhong --- Changes in v2: None Changes in v1: - add extcon node description - add #sound-dai-cells description .../bindings/display/rockchip/cdn-dp-rockchip.txt | 62 ++ 1 file

[v2 PATCH 0/4] Rockchip Type-C and DispplayPort driver

"ret" - printk a err log when drm_of_encoder_active_endpoint_id - modify the dclk pin_pol to a single line Chris Zhong (4): Documentation: bindings: add dt doc for Rockchip USB Type-C PHY phy: Add USB Type-C PHY driver for rk3399 Documentation: bindings: add dt documentation for cdn DP con

[v1 PATCH 4/4] drm/rockchip: cdn-dp: add cdn DP support for rk3399

/firmware/cdn/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong --- Changes in v1: - use extcon API - use hdmi-codec for the DP Asoc - do not initialize

[v1 PATCH 3/4] Documentation: bindings: add dt documentation for cdn DP controller

This patch adds a binding that describes the cdn DP controller for rk3399. Signed-off-by: Chris Zhong --- Changes in v1: - add extcon node description - add #sound-dai-cells description .../bindings/display/rockchip/cdn-dp-rockchip.txt | 62 ++ 1 file changed, 62

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