Re: [PATCH 0/4] fixes for Adreno A5Xx preemption

On Wed, Jul 17, 2024 at 5:33 PM Vladimir Lypak wrote: > > On Wed, Jul 17, 2024 at 10:40:26AM +0100, Connor Abbott wrote: > > On Thu, Jul 11, 2024 at 11:10 AM Vladimir Lypak > > wrote: > > > > > > There are several issues with preemption on Adreno A5XX GPU

Re: [PATCH 0/4] fixes for Adreno A5Xx preemption

On Thu, Jul 11, 2024 at 11:10 AM Vladimir Lypak wrote: > > There are several issues with preemption on Adreno A5XX GPUs which > render system unusable if more than one priority level is used. Those > issues include persistent GPU faults and hangs, full UI lockups with > idling GPU. > > --- >

[PATCH v2 2/3] drm/msm: Expand UBWC config setting

. ubwc_mode is expanded and renamed to ubwc_swizzle to match the name on the display side. Similarly macrotile_mode should match the display side. Signed-off-by: Connor Abbott --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 34

[PATCH v2 3/3] drm/msm: Expose expanded UBWC config uapi

This adds extra parameters that affect UBWC tiling that will be used by the Mesa implementation of VK_EXT_host_image_copy. Signed-off-by: Connor Abbott --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 ++ include/uapi/drm/msm_drm.h | 2 ++ 2 files changed, 8 insertions(+) diff

[PATCH v2 1/3] drm/msm: Update a6xx register XML

Update to Mesa commit 81fd13913a97 ("freedreno: Fix RBBM_NC_MODE_CNTL variants"). Signed-off-by: Connor Abbott --- drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 1617 - 1 file changed, 1603 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm

[PATCH v2 0/3] drm/msm: Further expose UBWC tiling parameters

erent UBWC configurations and I cannot test them all. [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26578 Signed-off-by: Connor Abbott --- Changes in v2: - Move ubwc_config field descriptions to kerneldoc comments on the struct - Link to v1: https://lore.kernel.org/r/20240702-msm-tiling-c

Re: [PATCH 2/3] drm/msm: Expand UBWC config setting

On Tue, Jul 2, 2024 at 3:31 PM Rob Clark wrote: > > On Tue, Jul 2, 2024 at 5:56 AM Connor Abbott wrote: > > > > According to downstream we should be setting RBBM_NC_MODE_CNTL to a > > non-default value on a663 and a680, we don't support a663 and on a680 > >

[PATCH 1/3] drm/msm: Update a6xx register XML

Update to Mesa commit 81fd13913a97 ("freedreno: Fix RBBM_NC_MODE_CNTL variants"). Signed-off-by: Connor Abbott --- drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 1617 - 1 file changed, 1603 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm

[PATCH 3/3] drm/msm: Expose expanded UBWC config uapi

This adds extra parameters that affect UBWC tiling that will be used by the Mesa implementation of VK_EXT_host_image_copy. Signed-off-by: Connor Abbott --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 ++ include/uapi/drm/msm_drm.h | 2 ++ 2 files changed, 8 insertions(+) diff

[PATCH 2/3] drm/msm: Expand UBWC config setting

. ubwc_mode is expanded and renamed to ubwc_swizzle to match the name on the display side. Similarly macrotile_mode should match the display side. Signed-off-by: Connor Abbott --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 36

[PATCH 0/3] drm/msm: Further expose UBWC tiling parameters

erent UBWC configurations and I cannot test them all. [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26578 Signed-off-by: Connor Abbott --- Connor Abbott (3): drm/msm: Update a6xx register XML drm/msm: Expand UBWC config setting drm/msm: Expose expanded UBWC config uapi d

Re: [PATCH] drm/msm/adreno: fix a743 and a740 cx mem init

Remove the scm call since it's not done downstream either and > works fine without. > > Fixes: 14b27d5df3ea ("drm/msm/a7xx: Initialize a750 "software fuse"") > Signed-off-by: Neil Armstrong > --- Reviewed-by: Connor Abbott

Re: [PATCH v2 5/7] drm/msm/adreno: Add A702 support

On Fri, Feb 23, 2024 at 9:28 PM Konrad Dybcio wrote: > > The A702 is a weird mix of 600 and 700 series.. Perhaps even a > testing ground for some A7xx features with good ol' A6xx silicon. > It's basically A610 that's been beefed up with some new registers > and hw features (like APRIV!), that was

Re: [PATCH v5 09/18] drm/msm: import A6xx XML display registers database

On Mon, Apr 1, 2024 at 3:52 AM Dmitry Baryshkov wrote: > > Import Adreno registers database for A6xx from the Mesa, commit > 639488f924d9 ("freedreno/registers: limit the rules schema"). > > Signed-off-by: Dmitry Baryshkov > --- > drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 4970 >

Re: drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c:843:6: error: variable 'out' set but not used

On Tue, Mar 26, 2024 at 7:47 PM Dmitry Baryshkov wrote: > > On Tue, 26 Mar 2024 at 21:32, Abhinav Kumar wrote: > > > > > > > > On 3/26/2024 12:10 PM, Dmitry Baryshkov wrote: > > > On Tue, 26 Mar 2024 at 20:31, Abhinav Kumar > > > wrote: > > >> > > >> > > >> > > >> On 3/26/2024 11:19 AM, Dmitry

Re: [PATCH] drm/msm/a6xx: specify UBWC config for sc7180

eck. > > Rather than adding the check to a6xx_set_ubwc_config(), fill in the > UBWC config for a618 (based on readings from SC7180). > > Reported-by: Leonard Lausen > Link: https://gitlab.freedesktop.org/drm/msm/-/issues/49 > Fixes: 8814455a0e54 ("drm/msm: Refactor UBWC config s

Re: [PATCH] drm/msm/a6xx: skip programming of UBWC registers for a618

k. Thus it ends up rewriting hardware registers with the default > (incorrect) values. Add the !a618 check to this function. > > Reported-by: Leonard Lausen > Link: https://gitlab.freedesktop.org/drm/msm/-/issues/49 > Fixes: 8814455a0e54 ("drm/msm: Refactor UBWC config setting