On Thu, 18 Apr 2024 14:56:58 -0700, Andi Shyti wrote:
>
> > v2: Change commit message and other minor code changes
> > v3: Cleanup from i915_hwmon_register on error (Armin Wolf)
> > v4: Eliminate potential static analyzer warning (Rodrigo)
> > Eliminate fetch_and_zero (Jani)
> > v5: Restore
On Wed, 17 Apr 2024 01:28:48 -0700, Andi Shyti wrote:
>
Hi Andi,
> > @@ -839,16 +837,38 @@ void i915_hwmon_register(struct drm_i915_private
> > *i915)
> > if (!hwm_gt_is_visible(ddat_gt, hwmon_energy,
> > hwmon_energy_input, 0))
> > continue;
> >
> > -
On Tue, 16 Apr 2024 11:55:20 -0700, Rodrigo Vivi wrote:
>
Hi Rodrigo,
> > @@ -849,5 +849,26 @@ void i915_hwmon_register(struct drm_i915_private *i915)
> >
> > void i915_hwmon_unregister(struct drm_i915_private *i915)
> > {
> > - fetch_and_zero(>hwmon);
> > + struct i915_hwmon *hwmon =
On Mon, 15 Apr 2024 16:35:02 -0700, Armin Wolf wrote:
>
Hi Armin,
> Am 16.04.24 um 00:36 schrieb Ashutosh Dixit:
> > @@ -818,10 +818,10 @@ void i915_hwmon_register(struct drm_i915_private
> > *i915)
> > hwm_get_preregistration_info(i915);
> >
> > /* hwmon_dev points to device hwmon */
On Tue, 12 Mar 2024 13:34:25 -0700, Janusz Krzysztofik wrote:
>
Hi Janusz,
> On Tuesday, 12 March 2024 17:25:14 CET Dixit, Ashutosh wrote:
> > On Mon, 11 Mar 2024 13:34:58 -0700, Janusz Krzysztofik wrote:
> > >
> > > In i915 hwmon sysfs getter path we now t
On Mon, 11 Mar 2024 13:34:58 -0700, Janusz Krzysztofik wrote:
>
> In i915 hwmon sysfs getter path we now take a hwmon_lock, then acquire an
> rpm wakeref. That results in lock inversion:
>
> <4> [197.079335] ==
> <4> [197.085473] WARNING:
On Tue, 27 Jun 2023 12:13:36 -0700, Vinay Belgaumkar wrote:
>
> GuC load takes longer sometimes due to GT frequency not ramping up.
> Add perf_limit_reasons to the existing warn print to see if frequency
> is being throttled.
>
> v2: Review comments (Ashutosh)
Reviewed-by: Ashutosh Dixit
>
>
On Mon, 26 Jun 2023 21:02:14 -0700, Belgaumkar, Vinay wrote:
>
>
> On 6/26/2023 8:17 PM, Dixit, Ashutosh wrote:
> > On Mon, 26 Jun 2023 19:12:18 -0700, Vinay Belgaumkar wrote:
> >> GuC load takes longer sometimes due to GT frequency not ramping up.
> >> Add perf_l
On Mon, 26 Jun 2023 19:12:18 -0700, Vinay Belgaumkar wrote:
>
> GuC load takes longer sometimes due to GT frequency not ramping up.
> Add perf_limit_reasons to the existing warn print to see if frequency
> is being throttled.
>
> Signed-off-by: Vinay Belgaumkar
> ---
>
On Fri, 09 Jun 2023 15:02:52 -0700, Vinay Belgaumkar wrote:
>
Hi Vinay,
> We were skipping when min_softlimit was equal to RPn. We need to apply
> it rergardless as efficient frequency will push the SLPC min to RPe.
> This will break scenarios where user sets a min softlimit < RPe before
> reset
On Fri, 09 Jun 2023 15:02:52 -0700, Vinay Belgaumkar wrote:
>
Hi Vinay,
> We were skipping when min_softlimit was equal to RPn. We need to apply
> it rergardless as efficient frequency will push the SLPC min to RPe.
regardless
> This will break scenarios where user sets a min softlimit < RPe
On Fri, 02 Jun 2023 03:16:20 -0700, Jani Nikula wrote:
>
> On Thu, 01 Jun 2023, Ashutosh Dixit wrote:
> > An inadvertent 'dim push -d' can delete remote branches. Disallow such
> > remote branch deletions.
>
> Please see
> https://drm.pages.freedesktop.org/maintainer-tools/CONTRIBUTING.html
>
>
On Wed, 24 May 2023 10:53:20 -0700, Tvrtko Ursulin wrote:
>
Hi Tvrtko,
> On 24/05/2023 18:38, Dixit, Ashutosh wrote:
> > On Wed, 24 May 2023 04:38:18 -0700, Tvrtko Ursulin wrote:
> >> On 23/05/2023 16:19, Ashutosh Dixit wrote:
> >>> No functional changes but w
On Wed, 24 May 2023 02:12:31 -0700, Andrzej Hajda wrote:
>
Hi Andrzej,
> On 23.05.2023 17:19, Ashutosh Dixit wrote:
> > pmu_needs_timer() keeps the timer running even when GT is parked,
> > ostensibly to sample requested/actual frequencies. However
> > frequency_sample() has the following:
> >
>
On Wed, 24 May 2023 04:38:18 -0700, Tvrtko Ursulin wrote:
>
Hi Tvrtko,
> On 23/05/2023 16:19, Ashutosh Dixit wrote:
> > No functional changes but we can remove some unsightly index computation
> > and read/write functions if we convert the PMU sample array from a
> > one-dimensional to a
On Fri, 12 May 2023 01:59:08 -0700, Tvrtko Ursulin wrote:
>
Hi Tvrtko,
> On 12/05/2023 02:53, Ashutosh Dixit wrote:
> > pmu_needs_timer() keeps the timer running even when GT is parked,
> > ostensibly to sample requested/actual frequencies. However
> > frequency_sample() has the following:
> >
>
On Mon, 22 May 2023 14:34:18 -0700, Umesh Nerlige Ramappa wrote:
>
> On Mon, May 22, 2023 at 01:17:49PM -0700, Ashutosh Dixit wrote:
> > Clearing out report id and timestamp as means to detect unlanded reports
> > only works if report size is power of 2. That is, only when report size is
> > a
On Tue, 16 May 2023 02:24:45 -0700, Tvrtko Ursulin wrote:
>
> From: Tvrtko Ursulin
>
> Having it as u64 was a confusing (but harmless) mistake.
>
> Also add some asserts to make sure the internal field does not overflow
> in the future.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Ashutosh Dixit
>
On Mon, 15 May 2023 15:58:26 -0700, Dixit, Ashutosh wrote:
>
> On Mon, 15 May 2023 15:23:58 -0700, Belgaumkar, Vinay wrote:
> >
> >
> > On 5/12/2023 5:39 PM, Dixit, Ashutosh wrote:
> > > On Fri, 12 May 2023 16:56:03 -0700, Vinay Belgaumkar wrote:
> > >
On Mon, 15 May 2023 15:23:58 -0700, Belgaumkar, Vinay wrote:
>
>
> On 5/12/2023 5:39 PM, Dixit, Ashutosh wrote:
> > On Fri, 12 May 2023 16:56:03 -0700, Vinay Belgaumkar wrote:
> > Hi Vinay,
> >
> >> rps_boost debugfs shows host turbo related info. This is
On Fri, 12 May 2023 16:56:03 -0700, Vinay Belgaumkar wrote:
>
Hi Vinay,
> rps_boost debugfs shows host turbo related info. This is not valid
> when SLPC is enabled.
A couple of thoughts about this. It appears people are know only about
rps_boost_info and don't know about guc_slpc_info? So:
a.
On Fri, 12 May 2023 02:33:33 -0700, Andi Shyti wrote:
>
Hi Andi,
>
> On Thu, May 11, 2023 at 10:43:30AM -0700, Dixit, Ashutosh wrote:
> > On Wed, 10 May 2023 11:36:06 -0700, Ashutosh Dixit wrote:
> > >
> > > Loading i915 on UBSAN enabled kernels (CONFIG_UBSA
On Wed, 10 May 2023 11:36:06 -0700, Ashutosh Dixit wrote:
>
> Loading i915 on UBSAN enabled kernels (CONFIG_UBSAN/CONFIG_UBSAN_BOOL)
> causes the following warning:
>
> UBSAN: invalid-load in drivers/gpu/drm/i915/gt/uc/intel_uc.c:558:2
> load of value 255 is not a valid value for type '_Bool'
On Thu, 20 Apr 2023 08:43:52 -0700, Rodrigo Vivi wrote:
>
Hi Rodrigo,
> On Thu, Apr 20, 2023 at 08:57:24AM +0100, Tvrtko Ursulin wrote:
> >
> > On 19/04/2023 23:10, Dixit, Ashutosh wrote:
> > > On Wed, 19 Apr 2023 06:21:27 -0700, Tvrtko Ursulin wrote:
&g
On Wed, 19 Apr 2023 12:40:44 -0700, Rodrigo Vivi wrote:
>
Hi Rodrigo,
> On Tue, Apr 18, 2023 at 10:23:50AM -0700, Dixit, Ashutosh wrote:
> > On Mon, 17 Apr 2023 22:35:58 -0700, Rodrigo Vivi wrote:
> > >
> >
> > Hi Rodrigo,
> >
> > > On Mon, Apr 10
On Wed, 19 Apr 2023 06:21:27 -0700, Tvrtko Ursulin wrote:
>
Hi Tvrtko,
> On 10/04/2023 23:35, Ashutosh Dixit wrote:
> > Instead of erroring out when GuC reset is in progress, block waiting for
> > GuC reset to complete which is a more reasonable uapi behavior.
> >
> > v2: Avoid race between
On Mon, 17 Apr 2023 22:35:58 -0700, Rodrigo Vivi wrote:
>
Hi Rodrigo,
> On Mon, Apr 10, 2023 at 03:35:09PM -0700, Ashutosh Dixit wrote:
> > Instead of erroring out when GuC reset is in progress, block waiting for
> > GuC reset to complete which is a more reasonable uapi behavior.
> >
> > v2:
On Fri, 14 Apr 2023 15:34:15 -0700, Vinay Belgaumkar wrote:
>
> @@ -457,6 +458,34 @@ int intel_guc_slpc_get_max_freq(struct intel_guc_slpc
> *slpc, u32 *val)
> return ret;
> }
>
> +int intel_guc_slpc_set_ignore_eff_freq(struct intel_guc_slpc *slpc, bool val)
> +{
> + struct
On Fri, 07 Apr 2023 04:04:06 -0700, Rodrigo Vivi wrote:
>
Hi Rodrigo,
> On Wed, Apr 05, 2023 at 09:45:22PM -0700, Ashutosh Dixit wrote:
> > Instead of erroring out when GuC reset is in progress, block waiting for
> > GuC reset to complete which is a more reasonable uapi behavior.
> >
> >
On Fri, 07 Apr 2023 04:08:31 -0700, Rodrigo Vivi wrote:
>
Hi Rodrigo,
> On Wed, Apr 05, 2023 at 09:45:21PM -0700, Ashutosh Dixit wrote:
> > On dGfx, the PL1 power limit being enabled and set to a low value results
> > in a low GPU operating freq. It also negates the freq raise operation which
>
On Wed, 05 Apr 2023 13:12:29 -0700, Rodrigo Vivi wrote:
>
> On Wed, Apr 05, 2023 at 12:42:30PM -0700, Dixit, Ashutosh wrote:
> > On Wed, 05 Apr 2023 06:57:42 -0700, Rodrigo Vivi wrote:
> > >
Hi Rodrigo,
> >
> > > On Fri, Mar 31, 2023 at 08:11:29PM -0700, Dixit
On Tue, 28 Mar 2023 02:14:42 -0700, Tvrtko Ursulin wrote:
>
Hi Tvrtko,
> On 27/03/2023 18:47, Rodrigo Vivi wrote:
> >
> > +Daniel
> >
> > On Mon, Mar 27, 2023 at 09:58:52AM -0700, Dixit, Ashutosh wrote:
> >> On Sun, 26 Mar 2023 04:52:59 -0700, Rodrigo
On Mon, 27 Mar 2023 10:47:25 -0700, Rodrigo Vivi wrote:
>
Hi Rodrigo,
Sorry for the delay, I got pulled away into a couple of other things and
could only now get back to this.
>
> +Daniel
>
> On Mon, Mar 27, 2023 at 09:58:52AM -0700, Dixit, Ashutosh wrote:
> > On Sun, 26 Ma
On Wed, 05 Apr 2023 06:57:42 -0700, Rodrigo Vivi wrote:
>
Hi Rodrigo,
> On Fri, Mar 31, 2023 at 08:11:29PM -0700, Dixit, Ashutosh wrote:
> > On Fri, 31 Mar 2023 19:00:49 -0700, Vinay Belgaumkar wrote:
> > >
> >
> > Hi Vinay,
> >
> > > @@ -478,20 +
On Fri, 31 Mar 2023 19:00:49 -0700, Vinay Belgaumkar wrote:
>
Hi Vinay,
> @@ -478,20 +507,15 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc
> *slpc, u32 val)
> val > slpc->max_freq_softlimit)
> return -EINVAL;
>
> + /* Ignore efficient freq if lower min
On Fri, 31 Mar 2023 03:23:33 -0700, Tvrtko Ursulin wrote:
>
Hi Tvrtko,
> > @@ -385,8 +395,22 @@ static int
> > hwm_power_max_write(struct hwm_drvdata *ddat, long val)
> > {
> > struct i915_hwmon *hwmon = ddat->hwmon;
> > + intel_wakeref_t wakeref;
> > u32 nval;
> > + if (val ==
On Thu, 30 Mar 2023 08:44:34 -0700, Rodrigo Vivi wrote:
>
> On Wed, Mar 29, 2023 at 10:50:09PM -0700, Dixit, Ashutosh wrote:
> > On Tue, 28 Mar 2023 16:35:43 -0700, Ashutosh Dixit wrote:
> > >
> > > On ATSM the PL1 limit is disabled at power up. The previous uapi as
On Tue, 28 Mar 2023 16:35:43 -0700, Ashutosh Dixit wrote:
>
> On ATSM the PL1 limit is disabled at power up. The previous uapi assumed
> that the PL1 limit is always enabled and therefore did not have a notion of
> a disabled PL1 limit. This results in erroneous PL1 limit values when the
> PL1
On Sun, 26 Mar 2023 04:52:59 -0700, Rodrigo Vivi wrote:
>
Hi Rodrigo,
> On Fri, Mar 24, 2023 at 04:31:22PM -0700, Dixit, Ashutosh wrote:
> > On Fri, 24 Mar 2023 11:15:02 -0700, Belgaumkar, Vinay wrote:
> > >
> >
> > Hi Vinay,
> >
> > Thanks for the
On Fri, 24 Mar 2023 17:06:33 -0700, Belgaumkar, Vinay wrote:
>
Hi Vinay,
> On 3/24/2023 4:31 PM, Dixit, Ashutosh wrote:
> > On Fri, 24 Mar 2023 11:15:02 -0700, Belgaumkar, Vinay wrote:
> > Hi Vinay,
> >
> > Thanks for the review. Comments inline below.
> Sorry ab
On Fri, 24 Mar 2023 11:15:02 -0700, Belgaumkar, Vinay wrote:
>
Hi Vinay,
Thanks for the review. Comments inline below.
> On 3/15/2023 8:59 PM, Ashutosh Dixit wrote:
> > On dGfx, the PL1 power limit being enabled and set to a low value results
> > in a low GPU operating freq. It also negates the
On Fri, 17 Mar 2023 20:28:58 -0700, Dixit, Ashutosh wrote:
>
> Jani/Rodrigo,
>
> Original Subject: Re: [Intel-gfx] [PATCH] Revert "drm/i915/hwmon: Enable PL1
> power limit"
>
> On Wed, 15 Feb 2023 09:19:07 -0800, Rodrigo Vivi wrote:
> >
> > On W
Jani/Rodrigo,
Original Subject: Re: [Intel-gfx] [PATCH] Revert "drm/i915/hwmon: Enable PL1
power limit"
On Wed, 15 Feb 2023 09:19:07 -0800, Rodrigo Vivi wrote:
>
> On Wed, Feb 15, 2023 at 08:24:51AM -0800, Dixit, Ashutosh wrote:
> > On Wed, 15 Feb 2023 07:37:30 -0
On Thu, 16 Mar 2023 15:06:32 -0700, john.c.harri...@intel.com wrote:
>
> From: John Harrison
>
> A failure to load the GuC is occasionally observed where the GuC log
> actually showed that the GuC had loaded just fine. The implication
> being that the load just took ever so slightly longer than
On Tue, 14 Mar 2023 02:35:07 -0700, Jani Nikula wrote:
>
Hi Jani,
Thanks for the review. I have posted v3, comments inline below.
> On Mon, 13 Mar 2023, Ashutosh Dixit wrote:
> > On dGfx, the PL1 power limit being enabled and set to a low value results
> > in a low GPU operating freq. It also
On Wed, 15 Mar 2023 02:43:30 -0700, Tvrtko Ursulin wrote:
>
> On 10/03/2023 00:59, Ashutosh Dixit wrote:
> > Expose intel_rps_read_actual_frequency_fw to read the actual freq without
> > taking forcewake for use by PMU. The code is refactored to use a common set
> > of functions across sysfs and
On Wed, 15 Mar 2023 02:50:17 -0700, Tvrtko Ursulin wrote:
>
> On 10/03/2023 00:59, Ashutosh Dixit wrote:
> > The fallback to requested freq does not work for SLPC because SLPC does not
> > use 'struct intel_rps'. Also for SLPC requested freq can only be obtained
> > from a hw register after
On Tue, 14 Mar 2023 19:29:06 -0700, Vinay Belgaumkar wrote:
>
> Use hex format so that it is easier to decode.
>
> Fixes: fe5979665f64 ('Add perf_limit_reasons in debugfs')
>
> Signed-off-by: Vinay Belgaumkar
> ---
> drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 2 +-
> 1 file changed, 1
On Fri, 10 Mar 2023 17:01:42 -0800, John Harrison wrote:
>
> >> + for (count = 0; count < 20; count++) {
> >> + ret = wait_for(guc_load_done(uncore, , ), 1000);
> >
> > Isn't 20 secs a bit too long for an in-place wait? I get that if the GuC
> > doesn't load (or fail to) within a few
On Fri, 10 Mar 2023 16:33:58 -0800, Ashutosh Dixit wrote:
>
> On dGfx, the PL1 power limit being enabled and set to a low value results
> in a low GPU operating freq. It also negates the freq raise operation which
> is done before GuC firmware load. As a result GuC firmware load can time
> out.
On Thu, 09 Mar 2023 01:20:09 -0800, Tvrtko Ursulin wrote:
>
Hi Tvrtko,
> On 09/03/2023 03:46, Ashutosh Dixit wrote:
> > Expose intel_rps_read_actual_frequency_fw to read the actual freq without
> > taking forcewake for use by PMU. The code is refactored to use a common set
> > of functions
On Tue, 07 Mar 2023 22:12:49 -0800, Belgaumkar, Vinay wrote:
>
Hi Vinay,
> On 3/7/2023 9:33 PM, Ashutosh Dixit wrote:
> > Using common freq functions with sysfs in PMU (but without taking
> > forcewake) solves the following issues (a) missing support for MTL (b)
>
> For the requested_freq, we
On Mon, 06 Mar 2023 03:10:24 -0800, Tvrtko Ursulin wrote:
>
Hi Tvrtko,
> On 04/03/2023 01:27, Ashutosh Dixit wrote:
> > SLPC does not use 'struct intel_rps'. Use UNSLICE_RATIO bits from
>
> Would it be more accurate to say 'SLPC does not use rps->cur_freq' rather
> than it not using struct
On Mon, 06 Mar 2023 03:04:40 -0800, Tvrtko Ursulin wrote:
>
Hi Tvrtko,
> On 04/03/2023 01:27, Ashutosh Dixit wrote:
> > On newer generations, the GEN12_RPSTAT1 register contains more than freq
> > information, e.g. see GEN12_VOLTAGE_MASK. Therefore use only the freq bits
> > to decide whether to
On Wed, 01 Mar 2023 11:48:06 -0800, Deepak R Varma wrote:
>
> A call to platform_get_irq() already prints an error on failure within
> its own implementation. So printing another error based on its return
> value in the caller is redundant and should be removed. The clean up
> also makes if
On Wed, 01 Mar 2023 11:35:41 -0800, Deepak R Varma wrote:
>
> According to Documentation/filesystems/sysfs.rst, the show() callback
> function of kobject attributes should strictly use sysfs_emit() instead
> of sprintf() family functions. So, make this change.
> Issue identified using the
On Fri, 12 Aug 2022 11:06:58 -0700, Guenter Roeck wrote:
>
Hi Guenter/linux-hwmon,
> On 8/12/22 10:37, Badal Nilawar wrote:
> > From: Dale B Stimson
> >
> > Use i915 HWMON to display/modify dGfx power PL1 limit and TDP setting.
> >
/snip/
>
> Acked-by: Guenter Roeck
>
> > ---
> >
On Wed, 15 Feb 2023 07:37:30 -0800, Jani Nikula wrote:
>
> On Wed, 08 Feb 2023, Rodrigo Vivi wrote:
> > On Wed, Feb 08, 2023 at 11:03:12AM -0800, Ashutosh Dixit wrote:
> >> This reverts commit 0349c41b05968befaffa5fbb7e73d0ee6004f610.
> >>
> >> 0349c41b0596 ("drm/i915/hwmon: Enable PL1 power
On Mon, 13 Feb 2023 22:16:44 -0800, Guenter Roeck wrote:
>
Hi Guenter,
> On 2/13/23 21:33, Ashutosh Dixit wrote:
> > On ATSM the PL1 power limit is disabled at power up. The previous uapi
> > assumed that the PL1 limit is always enabled and therefore did not have a
> > notion of a disabled PL1
On Tue, 07 Feb 2023 08:12:25 -0800, Dixit, Ashutosh wrote:
>
> On Tue, 07 Feb 2023 01:32:44 -0800, Matthew Auld wrote:
> >
> > On Fri, 3 Feb 2023 at 15:54, Ashutosh Dixit
> > wrote:
> > >
> > > Previous documentation suggested that PL1 power limit is
On Tue, 07 Feb 2023 01:32:44 -0800, Matthew Auld wrote:
>
> On Fri, 3 Feb 2023 at 15:54, Ashutosh Dixit wrote:
> >
> > Previous documentation suggested that PL1 power limit is always
> > enabled. However we now find this not to be the case on some
> > platforms (such as ATSM). Therefore enable
On Thu, 12 Jan 2023 20:26:34 -0800, Belgaumkar, Vinay wrote:
>
> I think the ABI was changed by the patch mentioned in the commit
> (a8a4f0467d70).
The ABI was originally changed in 80cf8af17af04 and 56a709cf77468.
On Thu, 12 Jan 2023 18:27:52 -0800, Vinay Belgaumkar wrote:
>
> Reading current root sysfs entries gives a min/max of all
> GTs. Updating this so we return default (GT0) values when root
> level sysfs entries are accessed, instead of min/max for the card.
> Tests that are not multi GT capable will
On Sun, 14 Aug 2022 16:46:54 -0700, Vinay Belgaumkar wrote:
>
> Host Turbo operates at efficient frequency when GT is not idle unless
> the user or workload has forced it to a higher level. Replicate the same
> behavior in SLPC by allowing the algorithm to use efficient frequency.
> We had
On Fri, 18 Nov 2022 10:37:37 -0800, Vivi, Rodrigo wrote:
>
> On Sat, 2022-11-19 at 00:03 +0530, Badal Nilawar wrote:
> > From: Vinay Belgaumkar
> >
> > By defaut idle messaging is disabled for GSC CS so to unblock RC6
> > entry on media tile idle messaging need to be enabled.
> >
> > v2:
> > -
On Tue, 22 Feb 2022 00:57:02 -0800, Andi Shyti wrote:
>
Old thread, new comment below at the bottom. Please take a look. Thanks.
> Hi Tvrtko and Joonas,
>
> > > > > > Now tiles have their own sysfs interfaces under the gt/
> > > > > > directory. Because RC6 is a property that can be configured
On Tue, 01 Nov 2022 03:58:13 -0700, Jani Nikula wrote:
>
> On Mon, 31 Oct 2022, Ashutosh Dixit wrote:
> > FIELD_PREP and REG_FIELD_PREP have checks requiring a compile time constant
> > mask. When the mask comes in as the argument of a function these checks can
> > can fail depending on the
On Mon, 24 Oct 2022 15:54:53 -0700, Vinay Belgaumkar wrote:
>
> GuC will set the min/max frequencies to theoretical max on
> ATS-M. This will break kernel ABI, so limit min/max frequency
> to RP0(platform max) instead.
>
> Also modify the SLPC selftest to update the min frequency
> when we have a
On Fri, 21 Oct 2022 09:35:32 -0700, Rodrigo Vivi wrote:
>
Hi Rodrigo,
> On Wed, Oct 19, 2022 at 04:37:21PM -0700, Ashutosh Dixit wrote:
> > From: Badal Nilawar
> >
> > Add support for C6 residency and C state type for MTL SAMedia. Also add
> > mtl_drpc.
>
> I believe this patch deserves a slip
On Sat, 22 Oct 2022 10:56:03 -0700, Belgaumkar, Vinay wrote:
>
Hi Vinay,
> >> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
> >> b/drivers/gpu/drm/i915/gt/intel_rps.c
> >> index fc23c562d9b2..32e1f5dde5bb 100644
> >> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> >> +++
On Fri, 21 Oct 2022 18:38:57 -0700, Belgaumkar, Vinay wrote:
> On 10/20/2022 3:57 PM, Dixit, Ashutosh wrote:
> > On Tue, 18 Oct 2022 11:30:31 -0700, Vinay Belgaumkar wrote:
> > Hi Vinay,
> >
> >> diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c
> >> b/
On Fri, 21 Oct 2022 17:24:52 -0700, Vinay Belgaumkar wrote:
>
Hi Vinay,
> Waitboost (when SLPC is enabled) results in a H2G message. This can result
> in thousands of messages during a stress test and fill up an already full
> CTB. There is no need to request for RP0 if boost_freq and the min
On Fri, 21 Oct 2022 11:24:42 -0700, Belgaumkar, Vinay wrote:
>
>
> On 10/20/2022 4:36 PM, Dixit, Ashutosh wrote:
> > On Thu, 20 Oct 2022 13:16:00 -0700, Belgaumkar, Vinay wrote:
> >> On 10/20/2022 11:33 AM, Dixit, Ashutosh wrote:
> >>> On Wed, 19 Oct 2022 17
On Wed, 19 Oct 2022 16:37:19 -0700, Ashutosh Dixit wrote:
>
> From: Badal Nilawar
>
> Update CAGF functions for MTL to get actual resolved frequency of 3D and
> SAMedia.
>
> v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR)
> Move MTL branches in cagf functions to top (MattR)
>
On Thu, 20 Oct 2022 13:16:00 -0700, Belgaumkar, Vinay wrote:
>
> On 10/20/2022 11:33 AM, Dixit, Ashutosh wrote:
> > On Wed, 19 Oct 2022 17:29:44 -0700, Vinay Belgaumkar wrote:
> > Hi Vinay,
> >
> >> Waitboost (when SLPC is enabled) results in a H2G message.
On Tue, 18 Oct 2022 11:30:31 -0700, Vinay Belgaumkar wrote:
>
Hi Vinay,
> diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c
> b/drivers/gpu/drm/i915/gt/selftest_slpc.c
> index 4c6e9257e593..e42bc215e54d 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_slpc.c
> +++
On Wed, 19 Oct 2022 17:29:44 -0700, Vinay Belgaumkar wrote:
>
Hi Vinay,
> Waitboost (when SLPC is enabled) results in a H2G message. This can result
> in thousands of messages during a stress test and fill up an already full
> CTB. There is no need to request for RP0 if GuC is already requesting
The freedesktop Patchwork seems to have a "feature" where in some cases the
submitter for a series changes randomly to a person who did not actually
submit a version of the series.
Not sure but this changed submitter seems to be a maintainer:
On Wed, 19 Oct 2022 07:58:13 -0700, Rodrigo Vivi wrote:
>
> On Tue, Oct 18, 2022 at 10:20:41PM -0700, Ashutosh Dixit wrote:
> > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
> > b/drivers/gpu/drm/i915/gt/intel_rps.c
> > index df21258976d86..5a743ae4dd11e 100644
> > ---
On Wed, 19 Oct 2022 08:06:26 -0700, Rodrigo Vivi wrote:
>
Hi Rodrigo,
> On Tue, Oct 18, 2022 at 10:20:40PM -0700, Ashutosh Dixit wrote:
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index 36d95b79022c0..a7a0129d0e3fc 100644
> > ---
On Mon, 17 Oct 2022 13:12:33 -0700, Dixit, Ashutosh wrote:
>
> On Fri, 14 Oct 2022 20:26:18 -0700, Ashutosh Dixit wrote:
> >
> > From: Badal Nilawar
>
> Hi Badal,
>
> One question below.
>
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_d
On Wed, 19 Oct 2022 00:51:45 -0700, Jani Nikula wrote:
>
> On Tue, 18 Oct 2022, Ashutosh Dixit wrote:
> > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.h
> > b/drivers/gpu/drm/i915/gt/intel_rc6.h
> > index b6fea71afc223..3105bc72c096b 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_rc6.h
> > +++
On Mon, 17 Oct 2022 01:27:35 -0700, Jani Nikula wrote:
Hi Jani,
Thanks for reviewing, great suggestions overall. I have taken care of most
of them in series version v6. Please see below.
> On Fri, 14 Oct 2022, Ashutosh Dixit wrote:
> > @@ -811,9 +809,23 @@ u64 intel_rc6_residency_ns(struct
On Fri, 14 Oct 2022 20:26:18 -0700, Ashutosh Dixit wrote:
>
> From: Badal Nilawar
Hi Badal,
One question below.
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> index 1fb053cbf52db..3a9bb4387248e 100644
> ---
On Tue, 20 Sep 2022 01:06:52 -0700, Jani Nikula wrote:
>
> On Mon, 19 Sep 2022, "Dixit, Ashutosh" wrote:
> > On Mon, 19 Sep 2022 05:13:18 -0700, Jani Nikula wrote:
> >>
> >> On Mon, 19 Sep 2022, Badal Nilawar wrote:
> >> > For MTL SAMedia upda
On Mon, 19 Sep 2022 09:49:07 -0700, Andi Shyti wrote:
>
> Hi Badal,
Hi Andi,
Badal is out for a bit so I am sending out this version.
> On Mon, Sep 19, 2022 at 05:29:05PM +0530, Badal Nilawar wrote:
> > Updated the CAGF functions to get actual resolved frequency of
> > 3D and SAMedia
>
> can
On Mon, 19 Sep 2022 15:49:17 -0700, Matt Roper wrote:
>
> On Mon, Sep 19, 2022 at 03:46:47PM -0700, Matt Roper wrote:
> > On Mon, Sep 19, 2022 at 05:29:05PM +0530, Badal Nilawar wrote:
> > > Updated the CAGF functions to get actual resolved frequency of
> > > 3D and SAMedia
> > >
> > > Bspec:
On Thu, 13 Oct 2022 08:55:24 -0700, Vinay Belgaumkar wrote:
>
Hi Vinay,
> GuC will set the min/max frequencies to theoretical max on
> ATS-M. This will break kernel ABI, so limit min/max frequency
> to RP0(platform max) instead.
Isn't what we are calling "theoretical max" or "RPmax" really just
On Mon, 03 Oct 2022 14:32:36 -0700, Andi Shyti wrote:
>
Hi Andi,
> > diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> > b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> > index f9d6d3b08bba..19b9fe3ef237 100644
> > ---
On Mon, 03 Oct 2022 14:13:10 -0700, Andi Shyti wrote:
>
Hi Andi,
> [...]
>
> > > diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> > > b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> > > index 16e697b1db3d..7525db243d74 100644
> > > ---
On Fri, 30 Sep 2022 09:52:28 -0700, Rodrigo Vivi wrote:
>
Hi Rodrigo,
> On Tue, Sep 27, 2022 at 11:20:17AM +0530, Badal Nilawar wrote:
> > From: Dale B Stimson
> >
> > Use i915 HWMON to display device level energy input.
> >
> > v2: Updated the date and kernel version in feature description
> >
On Mon, 03 Oct 2022 14:05:14 -0700, Andi Shyti wrote:
>
> Hi Badal,
>
> [...]
>
> > hwm_get_preregistration_info(struct drm_i915_private *i915)
> > {
> > struct i915_hwmon *hwmon = i915->hwmon;
> > + struct intel_uncore *uncore = >uncore;
> > + intel_wakeref_t wakeref;
> > + u32
On Wed, 21 Sep 2022 05:02:48 -0700, Gupta, Anshuman wrote:
>
> > diff --git a/drivers/gpu/drm/i915/intel_mchbar_regs.h
> > b/drivers/gpu/drm/i915/intel_mchbar_regs.h
> > index b74df11977c6..1014d0b7cc16 100644
> > --- a/drivers/gpu/drm/i915/intel_mchbar_regs.h
> > +++
On Mon, 03 Oct 2022 13:56:05 -0700, Andi Shyti wrote:
Hi Andi,
Badal is out for a bit so I am posting this version of the patches.
>
> Hi Badal,
>
> [...]
>
> > static void
> > hwm_get_preregistration_info(struct drm_i915_private *i915)
> > {
> > + struct i915_hwmon *hwmon = i915->hwmon;
>
On Tue, 04 Oct 2022 06:00:22 -0700, Tvrtko Ursulin wrote:
>
Hi Tvrtko,
>
> On 04/10/2022 10:29, Tvrtko Ursulin wrote:
> >
> > On 03/10/2022 20:24, Ashutosh Dixit wrote:
> >> PMU and sysfs use different wakeref's to "interpret" zero freq. Sysfs
> >> uses
> >> runtime PM wakeref (see
On Wed, 28 Sep 2022 11:35:18 -0700, Rodrigo Vivi wrote:
>
> On Wed, Sep 28, 2022 at 11:17:06AM -0700, Dixit, Ashutosh wrote:
> > On Wed, 28 Sep 2022 04:38:46 -0700, Jani Nikula wrote:
> > >
> > > On Mon, 19 Sep 2022, Ashutosh Dixit wrote:
> > > >
On Wed, 28 Sep 2022 04:38:46 -0700, Jani Nikula wrote:
>
> On Mon, 19 Sep 2022, Ashutosh Dixit wrote:
> > Register GT0_PERF_LIMIT_REASONS (0x1381a8) is available only for
> > Gen11+. Therefore ensure perf_limit_reasons sysfs/debugfs files are created
> > only for Gen11+. Otherwise on Gen < 5
On Tue, 27 Sep 2022 04:35:29 -0700, Badal Nilawar wrote:
>
> From: Don Hiatt
>
> On GEN12 and above use GEN12_RPSTAT register to get Current
> Actual Graphics Frequency of GT
I think even for the purposes of reviewing this it would be good to mention
in the commit message that:
a. GEN12_RPSTAT
On Fri, 23 Sep 2022 12:56:42 -0700, Badal Nilawar wrote:
>
> From: Ashutosh Dixit
>
> Expose power1_max_interval, that is the tau corresponding to PL1.
I think let's change the above sentence to: "Expose power1_max_interval,
that is the tau corresponding to PL1, as a custom hwmon attribute".
On Fri, 23 Sep 2022 12:56:40 -0700, Badal Nilawar wrote:
>
> diff --git a/drivers/gpu/drm/i915/i915_hwmon.h
> b/drivers/gpu/drm/i915/i915_hwmon.h
> index 7ca9cf2c34c9..4e5b6c149f3a 100644
> --- a/drivers/gpu/drm/i915/i915_hwmon.h
> +++ b/drivers/gpu/drm/i915/i915_hwmon.h
> @@ -17,4 +17,5 @@
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