The current settings for 28nm PHY data lane CFG4 registers do
not work with certain panels. This change is to modify them to
hw recommended values.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a
The current settings for 28nm PHY data lane CFG4 registers do
not work with certain panels. This change is to modify them to
hw recommended values.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a
Lane swap configuration is based on the board design.
This change allows the DSI host to get this information
from device tree, instead of hardcoding in driver.
Signed-off-by: Hai Li
---
Documentation/devicetree/bindings/drm/msm/dsi.txt | 13 ++
drivers/gpu/drm/msm/dsi/dsi_host.c
Hi Werner,
Based on the discussion with our hw team, changing the LNn_CFG4 to all 0 is the
solution for this issue.
I will prepare a change to this.
Thanks,
Hai
From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
Werner Johansson
Sent: Friday, August 28, 2015
Thanks Werner to test it out. I will focus on the dphy timing calculation then.
Itâs better to avoid discussing the excel formula publicly. :)
Thanks,
Hai
From: Werner Johansson [mailto:werner.johans...@gmail.com]
Sent: Wednesday, August 26, 2015 1:39 PM
To: Hai Li
Cc: Rob Clark
...@gmail.com]
Sent: Monday, August 24, 2015 9:24 PM
To: Hai Li
Cc: Rob Clark; Johansson, Werner; dri-devel at lists.freedesktop.org
Subject: Re: drm/msm/dsi: hs_zero timing
On Mon, Aug 24, 2015 at 7:32 AM, Hai Li wrote:
> Hi Werner,
>
> Yes, the register is to adjust hs_zero.
> Could y
ation code making the
difference.
Thanks,
Hai
-Original Message-
From: Rob Clark [mailto:robdcl...@gmail.com]
Sent: Saturday, August 22, 2015 9:25 AM
To: Johansson, Werner
Cc: Hai Li; dri-devel at lists.freedesktop.org
Subject: Re: drm/msm/dsi: hs_zero timing
On Fri, Aug 21, 2015 at 4:
Hi Werner,
I will prepare a change to make the lane swap configurable.
Thanks,
Hai
-Original Message-
From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
Johansson, Werner
Sent: Thursday, August 20, 2015 8:54 PM
To: dri-devel at lists.freedesktop.org
Subject: d
Hi Werner,
When I made DSI changes, I tried to limit the information in DT (like our
downstream driver), until there is a case driver really cannot figure it out by
the existing information.
I think this is the requirement of upstream kernel.
If we see a panel requires different value in PHY_LN
With more platforms supported, the DSI host
configuration array keeps expanding. This change
moves those to a separate dsi_cfg module.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 92 ++
drivers/gpu/drm/msm/dsi
On a certain platform, only one type of DSI PHY is used.
This change allows the user to only compile the PHY type
which is being used.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/Kconfig | 14 ++
drivers/gpu/drm/msm/Makefile | 11 +++
drivers/gpu/drm/msm
This change moves each PHY type specific code into
separate files.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/Makefile | 6 +-
drivers/gpu/drm/msm/dsi/dsi_phy.c | 756 -
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 448
We are not checking the return value from msm_dsi_phy_disable().
Change the return type to void.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/dsi.h | 2 +-
drivers/gpu/drm/msm/dsi/dsi_phy.c | 16 +---
2 files changed, 6 insertions(+), 12 deletions(-)
diff --git a/drivers
The bit position to configure source PLL will change
on new types of PHYs. The caller should pass down
this information.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/dsi_phy.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi
This change is to update DSI register definition changes
introduced by the following change:
rnndb/dsi: Add more bits for DSI PHY
More registers and bit fields are added for PHY timings
and bitclk source selection.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/dsi.xml.h | 5
The DSI PHY driver currently includes the implementation of all PHY types.
To support more types in the future, this patch series is moving each PHY
code into a separate file and making them compile independent. Some clean
up patches for DSI PHY are also included.
Hai Li (5):
drm/msm/dsi
More registers and bit fields are added for PHY timings
and bitclk source selection.
Signed-off-by: Hai Li
---
rnndb/dsi/dsi.xml | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/rnndb/dsi/dsi.xml b/rnndb/dsi/dsi.xml
index 02cfa3b..956f3ff 100644
--- a/rnndb/dsi
AHB clock should be enabled before accessing registers during
enable/disable_vblank(). Since these 2 callbacks are called in
atomic context while clk_prepare may cause thread sleep, a work
is scheduled to control vblanks.
v2: fixup spinlock initialization
Signed-off-by: Hai Li
---
drivers/gpu
AHB clock should be enabled before accessing registers during
enable/disable_vblank(). Since these 2 callbacks are called in
atomic context while clk_prepare may cause thread sleep, a work
is scheduled to control vblanks.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp4/mdp4_irq.c | 9
match HW status with cached status
in clock driver.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/dsi.h | 9 +++
drivers/gpu/drm/msm/dsi/dsi_manager.c | 21 +++
drivers/gpu/drm/msm/dsi/pll/dsi_pll.c | 42 +-
drivers/gpu/drm/msm
This change takes advantage of a HW feature that synchronize
flush operation on CTL1 to CTL0, to keep dual DSI pipes in
sync.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 140
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h | 4 +-
drivers
associate a CTL with each interface.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c | 12 --
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c| 26 +++--
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 49 +
drivers/gpu/drm/msm/mdp/mdp5
Instead of allocating CTL for each CRTC, we start to associate CTL
to each display interface, which reflects real HW requirement.
It also helps in making use of HW single FLUSH feature to sync
between dual DSI pipes.
Hai Li (2):
drm/msm/mdp5: Allocate CTL for each display interface
drm/msm
table and treat it as the whole pipe's limitation for MDP5. The size
limit on MDP4 is not changed.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c | 5 +
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 8
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 2 ++
drivers/gpu/d
DSI controller on msm8x94 is version 1.3, which requires different
power supplies and works with 20nm DSI PHY. This change is to add
the basic support for this version.
Signed-off-by: Hai Li
---
Documentation/devicetree/bindings/drm/msm/dsi.txt | 7 ++
drivers/gpu/drm/msm/dsi/dsi.h
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/dsi.xml.h | 192 +++---
1 file changed, 181 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h
b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index 9791ea0..9bb63a9 100644
--- a/drivers/gpu/drm
Hai Li (2):
drm/msm/dsi: Update generated headers with 20nm PHY support
drm/msm/dsi: Add support for msm8x94
Documentation/devicetree/bindings/drm/msm/dsi.txt | 7 +
drivers/gpu/drm/msm/dsi/dsi.h | 1 +
drivers/gpu/drm/msm/dsi/dsi.xml.h | 192
This change introduces new domains of PHY and PHY_REGULATOR
for 20nm DSI PHY registers.
Signed-off-by: Hai Li
---
rnndb/dsi/dsi.xml | 91 +++
1 file changed, 91 insertions(+)
diff --git a/rnndb/dsi/dsi.xml b/rnndb/dsi/dsi.xml
index d19bea9
Some targets use pinctrl framework to configure some
pins. This change allows DSI driver to set default and
sleep pinctrl status.
Signed-off-by: Hai Li
---
Documentation/devicetree/bindings/drm/msm/dsi.txt | 7 +++
drivers/gpu/drm/msm/dsi/dsi_host.c| 12
2
The current term of *dual panel* in DSI driver code causes confusion.
It is supposed to indicate the panel using two DSI links. Rename it
to *dual DSI*.
Signed-off-by: Hai Li
---
Documentation/devicetree/bindings/drm/msm/dsi.txt | 12 ++--
drivers/gpu/drm/msm/dsi/dsi_manager.c | 84
manager and PHY.
With this change, PLL selection can be supported on different
targets.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/dsi.h | 14 +-
drivers/gpu/drm/msm/dsi/dsi_manager.c | 15 ++-
drivers/gpu/drm/msm/dsi/dsi_phy.c | 34
These changes are for code cleanup and better support new targets in the future.
Hai Li (2):
drm/msm/dsi: Update source PLL selection in DSI PHY
drm/msm/dsi: Rename *dual panel* to *dual DSI*
Documentation/devicetree/bindings/drm/msm/dsi.txt | 12 +--
drivers/gpu/drm/msm/dsi/dsi.h
DSI video mode engine can only take active-high sync signals. This
change prevents MDP5 sending active-low sync signals to DSI in any
case.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a
clock consumer make DSI driver better fit into
common clock framework.
Signed-off-by: Hai Li
---
Documentation/devicetree/bindings/drm/msm/dsi.txt | 59 +++--
drivers/gpu/drm/msm/dsi/dsi.c | 45 +++-
drivers/gpu/drm/msm/dsi/dsi.h | 25 +-
drivers/gpu/drm/msm
This change activates PLL driver for DSI to work with
common clock framework.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/dsi.c | 14 +++
drivers/gpu/drm/msm/dsi/dsi.h | 43 ---
drivers/gpu/drm/msm/dsi/dsi_host.c| 60
DSI byte clock and pixel clocks are sourced from DSI PLL.
This change adds the DSI PLL source clock driver under
common clock framework.
This change handles DSI 28nm PLL only.
Signed-off-by: Hai Li
Signed-off-by: Archit Taneja
Signed-off-by: Stephane Viau
Signed-off-by: Wentao Xu
DSI PLL driver can work with common clock framework and provide source of DSI
byte clock and pixel clock, as a clock provider.
Hai Li (3):
drm/msm/dsi: Add DSI PLL clock driver support
drm/msm/dsi: Enable PLL driver in MSM DSI
drm/msm/dsi: Separate PHY to another platform device
ption for more bit fields
- Rebase on change "rnndb: dsi: Add DSI_LANE_CTRL info"
Signed-off-by: Stephane Viau
Signed-off-by: Hai Li
---
rnndb/dsi/dsi.xml | 80 +
rnndb/edp/edp.xml | 51 ++
rnndb/hdm
some registers
may not be implemented the same way for each interface PHY.
v2:
- Add description for more bit fields
- Rebase on change "rnndb: dsi: Add DSI_LANE_CTRL info"
Signed-off-by: Stephane Viau
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/ds
Yes, this is a bug in DSI driver. I have sent a patch to fix it.
http://lists.freedesktop.org/archives/dri-devel/2015-April/081893.html
Sorry for any inconvenience it caused.
Hai
-Original Message-
From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
David Bind
the data type to detect error.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 473d417..72d4d5f 100644
--- a/drivers/gpu
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index fdc54e3..473d417 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi
These 2 patches are to fix the issues during DSI command rx.
Hai Li (2):
drm/msm/dsi: Fixup missing *break* statement during cmd rx
drm/msm/dsi: Simplify the code to get the number of read byte
drivers/gpu/drm/msm/dsi/dsi_host.c | 15 +--
1 file changed, 5 insertions(+), 10
CRTCs in DSI command mode data path should wait for pingpong done,
instead of vblank, to finish atomic commit.
This change is to enable PP_DONE irq on command mode CRTCs and wait for
this irq happens before atomic commit completion.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp5
*_wait_for_commit_done
functions to wait for FLUSH register cleared at vsync, before commit
completion.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c | 39 ++
drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c | 7
drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h | 1
flag to differentiate cmd mode wait
function from video mode. (From Rob Clark)
Hai Li (2):
drm/msm: Use customized function to wait for atomic commit done
drm/msm/mdp5: Wait for PP_DONE irq for command mode CRTC atomic commit
drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c| 39
CRTCs in DSI command mode data path should wait for pingpong done,
instead of vblank, to finish atomic commit.
This change is to enable PP_DONE irq on command mode CRTCs and wait for
this irq happens before atomic commit completion.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp5
*_wait_for_commit_done
functions to wait for FLUSH register cleared at vsync, before commit
completion.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c | 46
drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c | 7
drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h | 1
The current way to wait for atomic commit done may cause unnecessary wait for
another vsync for video mode path. Also, for command mode path, we need to wait
for PP_DONE event other than vsync before finish. This patch series is to fix
these issues.
Hai Li (2):
drm/msm: Use customized function
drm_mode_connector_attach_encoder() function call is missing
during eDP and DSI connector initialization. As a result,
no encoder is returned by DRM_IOCTL_MODE_GETCONNECTOR system
call. This change is to fix this issue.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/dsi.c | 10
Signed-off-by: Hai Li
---
Documentation/devicetree/bindings/drm/msm/edp.txt | 61 +++
1 file changed, 61 insertions(+)
create mode 100644 Documentation/devicetree/bindings/drm/msm/edp.txt
diff --git a/Documentation/devicetree/bindings/drm/msm/edp.txt
b/Documentation
Signed-off-by: Hai Li
---
Documentation/devicetree/bindings/drm/msm/dsi.txt | 97 +++
1 file changed, 97 insertions(+)
create mode 100644 Documentation/devicetree/bindings/drm/msm/dsi.txt
diff --git a/Documentation/devicetree/bindings/drm/msm/dsi.txt
b/Documentation
This change adds the DSI connector support in msm drm driver.
v1: Initial change
v2:
- Address comments from Archit + minor clean-ups
- Rebase to not depend on msm_drm_sub_dev change [Rob's comment]
v3: Fix issues when initialization is failed
Signed-off-by: Hai Li
---
drivers/gpu/dr
o not depend on msm_drm_sub_dev change
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/Makefile| 3 +-
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 4 +
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c | 343
drivers/gpu/drm/msm/mdp/mdp5/mdp5_c
This change adds the DSI connector support in msm drm driver.
v1: Initial change
v2:
- Address comments from Archit + minor clean-ups
- Rebase to not depend on msm_drm_sub_dev change [Rob's comment]
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/Kconfig | 11 +
drivers/gpu/dr
This change is to add an interface to MDP for connector devices
setting split display information.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/msm_kms.h | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
index 3a78cb4..a9f17bd
This change is to make the content in construct_encoder reflect its
name.
Also, DSI connector may be connected to video mode or command mode
encoder, so that 2 different encoders need to be constructed for DSI.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 89
Resending initial MSM DSI patches
DSI is supported by both mdp4 and mdp5. This patch series adds the common DSI
controller driver and also enable it in mdp5.
Hai Li (4):
drm/msm/mdp5: Move *_modeset_init out of construct_encoder function
drm/msm: Add split display interface
drm/msm: Initial
This change adds the DSI connector support in msm drm driver.
v1: Initial change
v2: Address comments from Archit + minor clean-ups
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/Kconfig | 11 +
drivers/gpu/drm/msm/Makefile |4 +
drivers/gpu/drm/msm/dsi/dsi.c
This change adds the support in mdp5 kms driver for single
and dual DSI. Dual DSI case depends on the framework API
and sequence change to support dual data path.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 4 +
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c| 11
This change adds the DSI connector support in msm drm driver.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/Kconfig | 11 +
drivers/gpu/drm/msm/Makefile |4 +
drivers/gpu/drm/msm/dsi/dsi.c | 203
drivers/gpu/drm/msm/dsi/dsi.h | 115 ++
drivers/gpu
This change is to add an interface to MDP for connector devices
setting split display information.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/msm_kms.h | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
index 3a78cb4..a9f17bd
Prepare for initial DSI implementation
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/dsi.xml.h | 418 ++
1 file changed, 376 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h
b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index abf1bba
DSI is supported by both mdp4 and mdp5. This patch series adds the common DSI
controller driver and also enable it in mdp5.
Hai Li (4):
drm/msm/dsi: Update generated DSI header file
drm/msm: Add split display interface
drm/msm: Initial add DSI connector support
drm/msm/mdp5: Enable DSI
, which are used in 8084 and some other
chips.
Signed-off-by: Hai Li
---
rnndb/dsi/dsi.xml | 212 --
1 file changed, 191 insertions(+), 21 deletions(-)
diff --git a/rnndb/dsi/dsi.xml b/rnndb/dsi/dsi.xml
index 19898e1..480ec46 100644
--- a/rnndb
-off-by: Hai Li
---
drivers/gpu/drm/msm/msm_fbdev.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_fbdev.c b/drivers/gpu/drm/msm/msm_fbdev.c
index df60f65..d3e8b14 100644
--- a/drivers/gpu/drm/msm/msm_fbdev.c
+++ b/drivers/gpu/drm/msm/msm_fbdev.c
The width and height in SSPP_SRC_IMG_SIZE register should be the
size of the entire source framebuffer, not the fetch size.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5
This change adds the registers in mdp5 ping pong blocks
and split display control registers.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 105
1 file changed, 105 insertions(+)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
b
Pingpong register base addresses are different across platforms.
This change adds this information to config table and initialize
the values for 8x74 and 8084.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 8
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 1 +
2 files
Pingpong registers are needed by dsi command mode operation
for tearing check.
Split display registers are needed by dual dsi broadcast mode
for synchronization.
Signed-off-by: Hai Li
---
rnndb/mdp/mdp5.xml | 48
1 file changed, 48 insertions
mments and rebase on top of atomic changes
Remove edp_bridge_mode_fixup
Remove backlight control code and rely on pwm-backlight
Remove continuous splash screen support for now
Change to gpiod_* APIs
V4: Fix kbuild test issue
Signed-off-by: Hai Li
---
drivers/gpu/drm/ms
Modified the hard-coded hdmi connector/encoder implementations in msm drm
driver to support both edp and hdmi.
V1: Initial change
V2: Address Thierry's change
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 38 +++--
drivers/gpu/drm/msm/mdp
mments and rebase on top of atomic changes
Remove edp_bridge_mode_fixup
Remove backlight control code and rely on pwm-backlight
Remove continuous splash screen support for now
Change to gpiod_* APIs
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/Makefile|6 +
drive
Modified the hard-coded hdmi connector/encoder implementations in msm drm
driver to support both edp and hdmi.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 38 +--
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 47
This change adds a new eDP connector in msm drm driver. With this
change, eDP panel can work with msm platform under drm framework.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/Makefile|6 +
drivers/gpu/drm/msm/edp/edp.c | 211
drivers/gpu/drm/msm/edp/edp.h
Modified the hard-coded hdmi connector/encoder implementations in msm drm
driver to support both edp and hdmi.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 38 +--
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 47
This change adds a new eDP connector in msm drm driver. With this
change, eDP panel can work with msm platform under drm framework.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/Makefile|6 +
drivers/gpu/drm/msm/edp/edp.c | 211
drivers/gpu/drm/msm/edp/edp.h
introduced to establish the links
between hdmi connector, encoder and bridge.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 61 +++
drivers/gpu/drm/msm/hdmi/hdmi.h | 14 ---
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c| 3 +-
drivers
All the sub-systems in mdss share the same irq. This change provides
the sub-systems with the interfaces to register/unregister their own
irq handlers.
With this change, struct mdp5_kms does not have to keep the hdmi or
edp context.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/hdmi/hdmi.c
This change implements msm drm specific fb_mmap function for fb device
to properly map the fb address to userspace.
Signed-off-by: Hai Li
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/msm_fbdev.c | 38 --
1 file changed, 36 insertions(+), 2 deletions
This change implements msm drm specific fb_mmap function for fb device
to properly map the fb address to userspace.
Signed-off-by: Hai Li
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/msm_fbdev.c | 37 -
1 file changed, 36 insertions(+), 1 deletion
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