Aradhya Bhatia
Signed-off-by: Jayesh Choudhary
---
Changelog v1->v2:
- Fix typo in commit message
- Put the oldi parent and child node in case of error before returning
(as pointed out by Aradhya in v1)
- Pick up "R-by" tags
v1 patch link:
<https://lore.kernel.org/all/20250701055
dispc_pclk_diff()"
before it is called.
This will make the existing compatibles reusable if DSS features are
same across two SoCs with the only difference being the pixel clock.
Fixes: 7246e0929945 ("drm/tidss: Add OLDI bridge support")
Reviewed-by: Devarsh Thakkar
Signed-o
init().
Fixes: 7246e0929945 ("drm/tidss: Add OLDI bridge support")
Reviewed-by: Devarsh Thakkar
Signed-off-by: Jayesh Choudhary
---
drivers/gpu/drm/tidss/tidss_drv.h | 2 ++
drivers/gpu/drm/tidss/tidss_oldi.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/tids
I support series as all of its
patches are reviewed and tested and it touches one of the functions
used.
v1 patch link:
https://lore.kernel.org/all/20250618075804.139844-1-j-choudh...@ti.com/
Jayesh Choudhary (3):
drm/tidss: oldi: Add property to identify OLDI supported VP
drm/tidss: Rem
pport")
Reviewed-by: Devarsh Thakkar
Signed-off-by: Jayesh Choudhary
---
drivers/gpu/drm/tidss/tidss_oldi.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/tidss/tidss_oldi.c
b/drivers/gpu/drm/tidss/tidss_oldi.c
index 63e07c8edeaa..486e73735
Hello Devarsh,
On 01/07/25 19:00, Devarsh Thakkar wrote:
On 01/07/25 15:25, Jayesh Choudhary wrote:
In an effort to make the existing compatibles more usable, we are
removing the max_pclk_khz form dispc_features structure and doing the
correspondig checks using "curr_max_pclk[]".
C
Hello Devarsh,
On 01/07/25 18:42, Devarsh Thakkar wrote:
Hi Jayesh,
On 01/07/25 15:25, Jayesh Choudhary wrote:
TIDSS hardware by itself does not have variable max_pclk for each VP.
The maximum pixel clock is determined by the limiting factor between
the functional clock and the PLL
and the
Hello Devarsh,
On 01/07/25 19:22, Devarsh Thakkar wrote:
On 01/07/25 15:25, Jayesh Choudhary wrote:
Since OLDI consumes DSS VP clock directly as serial clock, certain
checks cannot be performed in tidss driver which should be checked
in oldi driver. Add check for mode clock and set the
efore it is called.
This will make the existing compatibles reusable.
Signed-off-by: Jayesh Choudhary
---
drivers/gpu/drm/tidss/tidss_dispc.c | 77 +++--
drivers/gpu/drm/tidss/tidss_dispc.h | 1 -
drivers/gpu/drm/tidss/tidss_drv.h | 2 +
3 files changed, 31 insert
Since OLDI consumes DSS VP clock directly as serial clock, certain
checks cannot be performed in tidss driver which should be checked
in oldi driver. Add check for mode clock and set the curr_max_pclk
field for tidss in case the VP is OLDI.
Signed-off-by: Jayesh Choudhary
---
drivers/gpu/drm
50618100509.20386-1-j-choudh...@ti.com/
Changelog v1->v2:
- Rebase it on linux-next after OLDI support series as all of its
patches are reviewed and tested and it touches one of the functions
used.
v1 patch link:
https://lore.kernel.org/all/20250618075804.139844-1-j-choudh...@ti.com/
Jay
TIDSS should know which VP has OLDI output to avoid calling clock
functions for that VP as those are controlled by oldi driver. Add a
property "is_oldi_vp" to "tidss_device" structure for that. Mark it
'true' in tidss_oldi_init() and 'false' in tidss_oldi_de
DRM bridges now uses "devm_drm_bridge_alloc()" for allocation and
initialization. "devm_kzalloc()" is not allowed anymore and it results
in WARNING. So convert it.
Fixes: 7246e0929945 ("drm/tidss: Add OLDI bridge support")
Signed-off-by: Jayesh Choud
Hello Aradhya, Tomi,
On 28/05/25 17:55, Aradhya Bhatia wrote:
From: Aradhya Bhatia
The AM62x and AM62Px SoCs feature 2 OLDI TXes each, which makes it
possible to connect them in dual-link or cloned single-link OLDI display
modes. The current OLDI support in tidss_dispc.c can only support for
a
TIDSS uses crtc_* fields to propagate its registers and set the
clock rates. So set the CRTC modesetting timing parameters with
the adjusted mode when needed, to set correct values.
Cc: Tomi Valkeinen
Signed-off-by: Jayesh Choudhary
---
Hello All,
After the DSI fixes[0], TIDSS is using crtc_
Hello Tomi,
On 24/06/25 17:29, Tomi Valkeinen wrote:
Hi,
On 18/06/2025 13:05, Jayesh Choudhary wrote:
TIDSS hardware by itself does not have variable max_pclk for each VP.
Each VP supports a fixed maximum pixel clock. K2 devices and AM62*
devices uses "ultra-light" version whe
, the caller functions for the cdns_mhdp_transfer in drm_dp_helper.c
(which calls it 32 times), has debug log level in case transfer fails.
So having a superseding log level in cdns_mhdp_transfer seems bad.
Signed-off-by: Jayesh Choudhary
---
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 4
250116111636.157641-1-j-choudh...@ti.com/>
Changelog v1->v2:
- Remove !DRM_BRIDGE_ATTACH_NO_CONNECTOR entirely
- Add mode_valid in drm_bridge_funcs[0]
- Fix NULL POINTER differently since we cannot access atomic_state
- Reduce log level in cdns_mhdp_transfer call
[0]: https://lore.kernel.org/al
(along with the DSI support as posted in
https://lore.kernel.org/all/20250624082619.324851-1-j-choudh...@ti.com/)
I can see that display comes up for 800x600 and 1280x1024 resolution.
Tested-by: Jayesh Choudhary
I observed that we still need something like drm_mode_set_crtcinfo()
to propagate c
.
Fixes: c932ced6b585 ("drm/tidss: Update encoder/bridge chain connect model")
Signed-off-by: Jayesh Choudhary
---
.../drm/bridge/cadence/cdns-mhdp8546-core.c | 187 +-
1 file changed, 10 insertions(+), 177 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdn
Hello Tomi,
On 18/06/25 15:29, Tomi Valkeinen wrote:
The timings calculation gets it wrong for DSI event mode, resulting in
too large hbp value. Fix the issue by taking into account the
pulse/event mode difference.
Tested-by: Parth Pancholi
Signed-off-by: Tomi Valkeinen
Reviewed-by: Jayesh
tidss: Update encoder/bridge chain connect model")
Signed-off-by: Jayesh Choudhary
---
.../drm/bridge/cadence/cdns-mhdp8546-core.c | 20 +++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
b/drivers/gpu/drm/bridge/cadence/cdn
in bridge_disable(), and make appropriate changes.
Fixes: c932ced6b585 ("drm/tidss: Update encoder/bridge chain connect model")
Signed-off-by: Jayesh Choudhary
---
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 12 ++--
drivers/gpu/drm/bridge/cadence/cdns-mhdp854
initialised in bridge_attach(). So set the mhdp->connector
in atomic_enable() earlier to avoid possible NULL pointer.
Fixes: c932ced6b585 ("drm/tidss: Update encoder/bridge chain connect model")
Signed-off-by: Jayesh Choudhary
---
.../drm/bridge/cadence/cdns-mhdp8546-
Hello Doug,
On 23/06/25 21:00, Doug Anderson wrote:
Hi,
On Mon, Jun 16, 2025 at 9:24 AM Doug Anderson wrote:
Hi,
On Mon, Jun 16, 2025 at 2:32 AM Jayesh Choudhary wrote:
@@ -1220,6 +1231,27 @@ static void ti_sn65dsi86_debugfs_init(struct drm_bridge
*bridge, struct dentry
32)
Fixes: c312b0df3b13 ("drm/bridge: ti-sn65dsi86: Implement bridge connector
operations for DP")
Cc: Max Krummenacher
Reviewed-by: Douglas Anderson
Tested-by: Ernest Van Hoecke
Signed-off-by: Jayesh Choudhary
---
Changelog v5->v6:
- Drop pm_runtime_mark_last_busy()
- Pick up t
lly the max resolution, driver ends up checking the maximum clock
the first time itself which is used in subsequent checks)
Since TIDSS display controller provides clock tolerance of 5%, we use
this while checking the max_pclk. Also, move up "dispc_pclk_diff()"
before it is called
On 18/06/25 13:28, Jayesh Choudhary wrote:
TIDSS hardware by itself does not have variable max_pclk for each VP.
Each VP supports a fixed maximum pixel clock. K2 devices and AM62*
devices uses "ultra-light" version where each VP supports a max of
300MHz whereas J7* devices uses T
Hello Maxime,
On 18/06/25 14:02, Maxime Ripard wrote:
Hi,
On Wed, Jun 18, 2025 at 01:28:04PM +0530, Jayesh Choudhary wrote:
TIDSS hardware by itself does not have variable max_pclk for each VP.
Each VP supports a fixed maximum pixel clock. K2 devices and AM62*
devices uses "ultra-
lly the max resolution, driver ends up checking the maximum clock
the first time itself which is used in subsequent checks)
Since TIDSS display controller provides clock tolerance of 5%, we use
this while checking the max_pclk. Also, move up "dispc_pclk_diff()"
before it is called
32)
Fixes: c312b0df3b13 ("drm/bridge: ti-sn65dsi86: Implement bridge connector
operations for DP")
Cc: Max Krummenacher
Signed-off-by: Jayesh Choudhary
---
Changelog v4->v5:
- Make suspend asynchronous in hpd_disable()
- Update HPD_DISABLE in probe function to address the case fo
Hello Doug,
On 12/06/25 20:21, Doug Anderson wrote:
Hi,
On Wed, Jun 11, 2025 at 9:39 PM Jayesh Choudhary wrote:
Hello Doug,
On 12/06/25 03:08, Doug Anderson wrote:
Hi,
On Tue, Jun 10, 2025 at 10:29 PM Jayesh Choudhary wrote:
@@ -1195,9 +1203,17 @@ static enum drm_connector_status
Hello Tomi,
On 12/06/25 11:55, Tomi Valkeinen wrote:
Hi,
On 11/06/2025 08:29, Jayesh Choudhary wrote:
By default, HPD was disabled on SN65DSI86 bridge. When the driver was
added (commit "a095f15c00e27"), the HPD_DISABLE bit was set in pre-enable
call which was moved to other func
Hello Michael,
On 10/06/25 12:45, Michael Walle wrote:
Hi Jayesh,
+ /*
+ * After EN is deasserted and an external clock is detected,
the bridge
+ * will sample GPIO3:1 to determine its frequency. The
driver will
+ * overwrite this setting. But this is racy. Thus we
Hello Doug,
On 12/06/25 03:08, Doug Anderson wrote:
Hi,
On Tue, Jun 10, 2025 at 10:29 PM Jayesh Choudhary wrote:
@@ -1195,9 +1203,17 @@ static enum drm_connector_status
ti_sn_bridge_detect(struct drm_bridge *bridge)
struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge
2b0df3b13 ("drm/bridge: ti-sn65dsi86: Implement bridge connector
operations for DP")
Cc: Max Krummenacher
Signed-off-by: Jayesh Choudhary
---
Changelog v3->v4:
- Remove "no-hpd" support due to backward compatibility issues
- Change the conditional from "no-hpd" ba
Hello Doug,
On 10/06/25 03:39, Doug Anderson wrote:
Hi,
On Mon, Jun 2, 2025 at 4:05 AM Jayesh Choudhary wrote:
Hello Geert, Krzysztof,
(continuing discussion from both patches on this thread...)
On 30/05/25 13:25, Geert Uytterhoeven wrote:
Hi Jayesh,
CC devicetree
On Fri, 30 May 2025
Hello Michael, Doug,
On 10/06/25 03:59, Doug Anderson wrote:
Hi,
On Wed, May 28, 2025 at 6:21 AM Michael Walle wrote:
The bridge has three bootstrap pins which are sampled to determine the
frequency of the external reference clock. The driver will also
(over)write that setting. But it seems
Hello Geert, Krzysztof,
(continuing discussion from both patches on this thread...)
On 30/05/25 13:25, Geert Uytterhoeven wrote:
Hi Jayesh,
CC devicetree
On Fri, 30 May 2025 at 04:54, Jayesh Choudhary wrote:
On 29/05/25 16:34, Jayesh Choudhary wrote:
By default, HPD was disabled on
.
Fixes: c932ced6b585 ("drm/tidss: Update encoder/bridge chain connect model")
Signed-off-by: Jayesh Choudhary
---
.../drm/bridge/cadence/cdns-mhdp8546-core.c | 184 +-
1 file changed, 9 insertions(+), 175 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8
initialised in bridge_attach(). So set the mhdp->connector
in atomic_enable() earlier to avoid possible NULL pointer.
Fixes: c932ced6b585 ("drm/tidss: Update encoder/bridge chain connect model")
Signed-off-by: Jayesh Choudhary
---
.../drm/bridge/cadence/cdns-mhdp8546-
r_for_encoder()
to a separate patch
- Drop "R-by" considering the changes in v2[1/3]
- Add Fixes tag to first 4 patches:
commit c932ced6b585 ("drm/tidss: Update encoder/bridge chain connect model")
This added DBANC flag in tidss while attaching bridge to the encoder
- Dr
in bridge_disable(), and make appropriate changes.
Fixes: c932ced6b585 ("drm/tidss: Update encoder/bridge chain connect model")
Signed-off-by: Jayesh Choudhary
---
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 12 ++--
drivers/gpu/drm/bridge/cadence/cdns-mhdp854
, the caller functions for the cdns_mhdp_transfer in drm_dp_helper.c
(which calls it 32 times), has debug log level in case transfer fails.
So having a superseding log level in cdns_mhdp_transfer seems bad.
Signed-off-by: Jayesh Choudhary
---
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 4
tidss: Update encoder/bridge chain connect model")
Signed-off-by: Jayesh Choudhary
---
.../drm/bridge/cadence/cdns-mhdp8546-core.c | 20 +++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
b/drivers/gpu/drm/bridge/cadence/cdn
On 29/05/25 16:34, Jayesh Choudhary wrote:
By default, HPD was disabled on SN65DSI86 bridge. When the driver was
added (commit "a095f15c00e27"), the HPD_DISABLE bit was set in pre-enable
call which was moved to other function calls subsequently.
Later on, commit "c312b0df3b1
Fixes: c312b0df3b13 ("drm/bridge: ti-sn65dsi86: Implement bridge connector
operations for DP")
Cc: Max Krummenacher
Signed-off-by: Jayesh Choudhary
---
Changelog v2->v3:
- Change conditional based on no-hpd property to address [1]
- Remove runtime calls in detect() with appropriate
eDP now.
On Thu, May 08, 2025 at 05:24:33PM +0530, Jayesh Choudhary wrote:
+ if (pdata->bridge.type == DRM_MODE_CONNECTOR_eDP)
+ regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
+HPD_DISABLE);
On my setup it seems that
Hi,
On 27/05/25 17:07, Tomi Valkeinen wrote:
Hi,
On 27/05/2025 13:39, Jayesh Choudhary wrote:
On 27/05/25 14:59, Jayesh Choudhary wrote:
Hello Tomi,
On 27/05/25 13:28, Tomi Valkeinen wrote:
Hi,
On 21/05/2025 10:32, Jayesh Choudhary wrote:
After adding DBANC framework, mhdp->connec
On 27/05/25 14:59, Jayesh Choudhary wrote:
Hello Tomi,
On 27/05/25 13:28, Tomi Valkeinen wrote:
Hi,
On 21/05/2025 10:32, Jayesh Choudhary wrote:
After adding DBANC framework, mhdp->connector is not initialised during
bridge calls. But the asyncronous work scheduled depends on
On 27/05/25 14:47, Tomi Valkeinen wrote:
Hi,
On 27/05/2025 11:41, Jayesh Choudhary wrote:
Hello Tomi,
On 27/05/25 13:08, Tomi Valkeinen wrote:
Hi,
On 21/05/2025 10:32, Jayesh Choudhary wrote:
Now that we have DBANC framework, remove the connector initialisation
code
as that piece of
Hello Tomi,
On 27/05/25 13:28, Tomi Valkeinen wrote:
Hi,
On 21/05/2025 10:32, Jayesh Choudhary wrote:
After adding DBANC framework, mhdp->connector is not initialised during
bridge calls. But the asyncronous work scheduled depends on the connector.
We cannot get to drm_atomic_state in th
Hello Tomi,
On 27/05/25 13:08, Tomi Valkeinen wrote:
Hi,
On 21/05/2025 10:32, Jayesh Choudhary wrote:
Now that we have DBANC framework, remove the connector initialisation code
as that piece of code is not called if DRM_BRIDGE_ATTACH_NO_CONNECTOR flag
is used. Only TI K3 platforms consume
Hello Dmitry, Doug,
Thanks a lot for the review.
On 22/05/25 18:44, Dmitry Baryshkov wrote:
On Wed, May 21, 2025 at 06:10:59PM -0700, Doug Anderson wrote:
Hi,
On Thu, May 8, 2025 at 4:54 AM Jayesh Choudhary wrote:
By default, HPD was disabled on SN65DSI86 bridge. When the driver was
added
Hello Tomi,
On 28/01/25 11:27, Jayesh Choudhary wrote:
Hello Tomi, Alexander,
On 24/01/25 13:38, Alexander Stein wrote:
Hi,
Am Donnerstag, 23. Januar 2025, 17:20:34 CET schrieb Tomi Valkeinen:
Hi,
On 16/01/2025 13:16, Jayesh Choudhary wrote:
For the cases we have
ore we can retry the
asyncronous work in case of any failure.
Fixes: fb43aa0acdfd ("drm: bridge: Add support for Cadence MHDP8546 DPI/DP
bridge")
Signed-off-by: Jayesh Choudhary
---
.../drm/bridge/cadence/cdns-mhdp8546-core.c | 28 +--
.../drm/bridge/cadence/cdns-mhdp85
, the caller functions for the cdns_mhdp_transfer in drm_dp_helper.c
(which calls it 32 times), has debug log level in case transfer fails.
So having a superseding log level in cdns_mhdp_transfer seems bad.
Signed-off-by: Jayesh Choudhary
---
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 4
.
Signed-off-by: Jayesh Choudhary
---
.../drm/bridge/cadence/cdns-mhdp8546-core.c | 186 +++---
1 file changed, 25 insertions(+), 161 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
index b431e7efd1f0
mic_state
- Reduce log level in cdns_mhdp_transfer call
[0]: https://lore.kernel.org/all/20240530091757.433106-1-j-choudh...@ti.com/
Jayesh Choudhary (3):
drm/bridge: cadence: cdns-mhdp8546-core: Remove legacy support for
connector initialisation in bridge
drm/bridge: cadence: cdns-mhdp8546
_dp_dpcd_read_link_status'
to find if we have something connected at the sink.
[0]: <https://www.ti.com/lit/gpn/SN65DSI86> (Pg. 32)
Fixes: c312b0df3b13 ("drm/bridge: ti-sn65dsi86: Implement bridge connector
operations for DP")
Cc: Max Krummenacher
Signed-off-by: Jayesh Choud
Hello Max,
On 06/05/25 22:14, Max Krummenacher wrote:
On Thu, May 01, 2025 at 08:38:15PM -0700, Doug Anderson wrote:
Hi,
On Thu, May 1, 2025 at 12:48 AM wrote:
From: Max Krummenacher
The bridge driver currently disables handling the hot plug input and
relies on a always connected eDP pane
Hello Max,
On 01/05/25 13:42, Max Krummenacher wrote:
On Mon, Apr 28, 2025 at 02:15:12PM -0700, Doug Anderson wrote:
Hello Jayesh,
Hi,
On Thu, Apr 24, 2025 at 6:32 PM Kumar, Udit wrote:
Hello Jayesh,
On 4/24/2025 4:24 PM, Jayesh Choudhary wrote:
For TI SoC J784S4, the display pipeline
Hello Krzysztof,
On 25/04/25 11:04, Krzysztof Kozlowski wrote:
On 24/04/2025 12:54, Jayesh Choudhary wrote:
For TI SoC J784S4, the display pipeline looks like:
TIDSS -> CDNS-DSI -> SN65DSI86 -> DisplayConnector -> DisplaySink
This requires HPD to detect connection form the c
7; as mentioned in the comments in the
driver.
Signed-off-by: Jayesh Choudhary
---
Hello All,
Sending this RFC patch to get some thoughts on hpd for sn65dsi86.
Now that we have a usecase for hpd in sn65dsi86, I wanted to get
some comments on this approach to "NOT DISABLE" hpd in the bri
Hello Doug,
On 17/04/25 02:40, Jayesh Choudhary wrote:
Hello Doug,
On 13/04/25 07:22, Doug Anderson wrote:
Hi,
On Fri, Apr 11, 2025 at 2:23 AM Jayesh Choudhary
wrote:
Enable NO_EOT and SYNC flags for DSI to use VIDEO_SYNC_PULSE_MODE
with EOT disabled.
Any chance you could add some
Hello Doug,
On 13/04/25 07:22, Doug Anderson wrote:
Hi,
On Fri, Apr 11, 2025 at 2:23 AM Jayesh Choudhary wrote:
Enable NO_EOT and SYNC flags for DSI to use VIDEO_SYNC_PULSE_MODE
with EOT disabled.
Any chance you could add some details to this commit message? Your
subject says that these
Hello Tomi,
On 02/04/25 19:00, Tomi Valkeinen wrote:
The timings calculation gets it wrong for DSI event mode, resulting in
too large hbp value. Fix the issue by taking into account the
pulse/event mode difference.
Signed-off-by: Tomi Valkeinen
Reviewed-by: Jayesh Choudhary
---
drivers
nnector
(https://lore.kernel.org/all/20250411105155.303657-1-j-choudh...@ti.com/)
Tested-by: Jayesh Choudhary
Signed-off-by: Tomi Valkeinen
---
Changes in v2:
- Change the tidss clock adjustment from mode_fixup() to atomic_check()
- Link to v1:
https://lore.kernel.org/r/20250320-cdns-dsi-impro-
Enable NO_EOT and SYNC flags for DSI to use VIDEO_SYNC_PULSE_MODE
with EOT disabled.
Signed-off-by: Jayesh Choudhary
---
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
b/drivers/gpu/drm/bridge/ti
if (funcs) {
if (funcs->atomic_enable)
I have tested display on J784S4-EVM for MHDP and DSI with this diff on
top of your series.
With the above change addressed,
Reviewed-by: Jayesh Choudhary
drm_atomic_helper_commit_writebacks(dev, old_state);
Warm Regards,
Jayesh
Hello Tomi, Alexander,
On 24/01/25 13:38, Alexander Stein wrote:
Hi,
Am Donnerstag, 23. Januar 2025, 17:20:34 CET schrieb Tomi Valkeinen:
Hi,
On 16/01/2025 13:16, Jayesh Choudhary wrote:
For the cases we have DRM_BRIDGE_ATTACH_NO_CONNECTOR flag set,
Any idea if any other platform than K3
mpatible:
enum:
- ti,am625-dss
- ti,am62a7,dss
+ - ti,am62l,dss
s/ti,am62l,dss/ti,am62l-dss
There seems to be inconsistency in the usage of the compatible name in
the conditional below.
Same is with the compatible "ti,am62a7,dss".
Can you fix that too?
With
t;drm: bridge: Add support for Cadence MHDP8546 DPI/DP
bridge")
Signed-off-by: Jayesh Choudhary
---
NOTE: Found this issue in one particular board where edid read failed.
Issue log: <https://gist.github.com/Jayesh2000/233f87f9becdf1e66f1da6fd53f77429>
Adding conditional fixes the null po
Hello Dmitry,
On 18/06/24 15:45, Dmitry Baryshkov wrote:
On Tue, 18 Jun 2024 at 12:56, Jayesh Choudhary wrote:
Hello Dmitry,
Thanks for the review.
On 18/06/24 14:29, Dmitry Baryshkov wrote:
On Tue, Jun 18, 2024 at 01:44:17PM GMT, Jayesh Choudhary wrote:
Add the atomic_check hook to
Hello Dmitry,
On 18/06/24 14:33, Dmitry Baryshkov wrote:
On Tue, Jun 18, 2024 at 01:44:18PM GMT, Jayesh Choudhary wrote:
During code inspection, it was found that due to integer calculations,
the rounding off can cause errors in the final value propagated in the
registers.
Considering the
Hello Dmitry,
Thanks for the review.
On 18/06/24 14:29, Dmitry Baryshkov wrote:
On Tue, Jun 18, 2024 at 01:44:17PM GMT, Jayesh Choudhary wrote:
Add the atomic_check hook to ensure that the parameters are within the
valid range.
As of now, dsi clock freqency is being calculated in
0x96. So add check for that.
[0]: <https://www.ti.com/lit/gpn/sn65dsi86>
Signed-off-by: Jayesh Choudhary
---
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 65 +++
1 file changed, 46 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
b/d
during
code inspection.
v1 patch:
<https://lore.kernel.org/all/20240408073623.186489-1-j-choudh...@ti.com/>
[0]: <https://www.ti.com/lit/gpn/sn65dsi86>
Jayesh Choudhary (2):
drm/bridge: ti-sn65dsi86: Add atomic_check hook for the bridge
drm/bridge: ti-sn65dsi86: Fix ti_sn_bri
idge driver")
Signed-off-by: Jayesh Choudhary
---
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
index d13b42d7c512..5bf12af6b657 100644
--- a
Hello Doug,
On 11/04/24 10:12, Doug Anderson wrote:
Hi,
On Wed, Apr 10, 2024 at 4:42 AM Jayesh Choudhary wrote:
Hello Doug,
Thanks for the review.
On 08/04/24 14:33, Doug Anderson wrote:
Hi,
On Mon, Apr 8, 2024 at 12:36 AM Jayesh Choudhary wrote:
Due to integer calculations, the
re clear
- Add the hook for drm_bridge_funcs as well
- Add check in atomic_check dunction call (in a separate patch)
v1 patch:
<https://lore.kernel.org/all/20240408081435.216927-1-j-choudh...@ti.com/>
Jayesh Choudhary (3):
drm/bridge: sii902x: Fix mode_valid hook
drm/bridge: sii902x: Sup
Check the pixel clock for the mode in atomic_check and ensure that
it is within the range supported by the bridge.
Signed-off-by: Jayesh Choudhary
---
drivers/gpu/drm/bridge/sii902x.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/bridge/sii902x.c b/drivers/gpu/drm
t actually checking the
modes.
So move the mode_valid hook to drm_bridge_funcs with proper clock
checks for maximum and minimum pixel clock supported by the bridge.
Signed-off-by: Jayesh Choudhary
Reviewed-by: Dmitry Baryshkov
Acked-by: Sui Jingfeng
---
drivers/gpu/drm/bridge/sii9
Change exisitig enable() and disable() bridge hooks to their atomic
counterparts as the former hooks are deprecated.
Signed-off-by: Jayesh Choudhary
---
drivers/gpu/drm/bridge/sii902x.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/bridge
Hello Sui, Sam!
Thanks for the review.
(Sorry for delayed response. I was OoO last week)
On 31/05/24 19:34, Sui Jingfeng wrote:
Hi, Jayesh
On 5/31/24 21:33, Sam Ravnborg wrote:
Hi Jayesh,
+
static const struct drm_bridge_funcs sii902x_bridge_funcs = {
.attach = sii902x_bridge_at
Hello Maxime,
On 30/05/24 15:04, Maxime Ripard wrote:
Hi,
On Thu, May 30, 2024 at 02:59:30PM GMT, Jayesh Choudhary wrote:
Check the pixel clock for the mode in atomic_check and ensure that
it is within the range supported by the bridge.
Signed-off-by: Jayesh Choudhary
---
drivers/gpu/drm
Check the pixel clock for the mode in atomic_check and ensure that
it is within the range supported by the bridge.
Signed-off-by: Jayesh Choudhary
---
drivers/gpu/drm/bridge/sii902x.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/bridge/sii902x.c b/drivers/gpu/drm
(in a separate patch)
v1 patch:
<https://lore.kernel.org/all/20240408081435.216927-1-j-choudh...@ti.com/>
Jayesh Choudhary (2):
drm/bridge: sii902x: Fix mode_valid hook
drm/bridge: Add pixel clock check in atomic_check
drivers/gpu/drm/bridge/sii902x.c | 38
id hook to drm_bridge_funcs with proper clock
checks for maximum and minimum pixel clock supported by the bridge.
Signed-off-by: Jayesh Choudhary
---
drivers/gpu/drm/bridge/sii902x.c | 32 +++-
1 file changed, 23 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/
the modes.
Signed-off-by: Jayesh Choudhary
---
Changelog v1->v2:
- Remove mode_valid hook from connector_helper_funcs as it is not required.
(Function despite being identical has been moved below with other
bridge_funcs instead of keeping it up with drm_connector_helper_funcs)
v1
On 24/05/24 15:13, Dmitry Baryshkov wrote:
On Fri, May 24, 2024 at 12:43:48PM +0530, Jayesh Choudhary wrote:
With the support for the 'DRM_BRIDGE_ATTACH_NO_CONNECTOR' case,
the connector_helper funcs are not initialized if the encoder has this
flag in its bridge_attach call. Till
On 25/05/24 01:16, Dmitry Baryshkov wrote:
On Fri, May 24, 2024 at 05:54:02PM +0530, Jayesh Choudhary wrote:
Hello Dmitry,
On 24/05/24 15:11, Dmitry Baryshkov wrote:
On Fri, May 24, 2024 at 03:05:08PM +0530, Jayesh Choudhary wrote:
Currently, mode_valid hook returns all mode as valid and
Hello Dmitry,
On 24/05/24 15:11, Dmitry Baryshkov wrote:
On Fri, May 24, 2024 at 03:05:08PM +0530, Jayesh Choudhary wrote:
Currently, mode_valid hook returns all mode as valid and it is
defined only in drm_connector_helper_funcs. With the introduction of
'DRM_BRIDGE_ATTACH_NO_CONN
Check the pixel clock for the mode in atomic_check and ensure that
it is within the range supported by the bridge.
Signed-off-by: Jayesh Choudhary
---
drivers/gpu/drm/bridge/sii902x.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/bridge/sii902x.c b/drivers/gpu/drm
id hook in drm_bridge_funcs as well with proper
clock checks for maximum and minimum pixel clock supported by the
bridge.
Signed-off-by: Jayesh Choudhary
---
drivers/gpu/drm/bridge/sii902x.c | 37 ++--
1 file changed, 35 insertions(+), 2 deletions(-)
diff --git a/drive
408081435.216927-1-j-choudh...@ti.com/>
Jayesh Choudhary (2):
drm/bridge: sii902x: Fix mode_valid hook
drm/bridge: Add pixel clock check in atomic_check
drivers/gpu/drm/bridge/sii902x.c | 43 ++--
1 file changed, 41 insertions(+), 2 deletions(-)
--
2.25.1
Hello Sam,
On 24/05/24 13:48, Sam Ravnborg wrote:
Hi Jayesh,
On Fri, May 24, 2024 at 01:03:04PM +0530, Jayesh Choudhary wrote:
Currently, mode_valid hook returns all mode as valid and it is
defined only in drm_connector_helper_funcs. With the introduction of
'DRM_BRIDGE_ATTACH_NO_CONN
id hook in drm_bridge_funcs as well with proper
clock checks for maximum and minimum pixel clock supported by the
bridge.
Signed-off-by: Jayesh Choudhary
---
drivers/gpu/drm/bridge/sii902x.c | 38 ++--
1 file changed, 36 insertions(+), 2 deletions(-)
diff --git a/drive
Check the pixel clock for the mode in atomic_check and ensure that
it is within the range supported by the bridge.
Signed-off-by: Jayesh Choudhary
---
drivers/gpu/drm/bridge/sii902x.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/sii902x.c b
check in atomic_check dunction call (in a separate patch)
v1 patch:
<https://lore.kernel.org/all/20240408081435.216927-1-j-choudh...@ti.com/>
Jayesh Choudhary (2):
drm/bridge: sii902x: Fix mode_valid hook
drm/bridge: Add pixel clock check in atomic_check
drivers/gpu/drm/bridge/
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