Hi guys, Hyun,
Has it ever been evaluated to let the vdma cycle through the multiple "stores"
it can handle without reconfiguration on a per-frame basis (with park bit off)?
One could program the two areas of memory of a double buffer setup in the vdma
registers and use the dma complete to tell
> On Jul 5, 2017, at 18:56, Hyun Kwon wrote:
>
> For VDMA, I think you can use the DMA engine complete callback to generate
> the vblank.
>
> But, please note that it's not a global solution, and it doesn't work for
> some other pipelines. For example, the ZU+ DPDMA operation is synchronized
Hi Hyun,
> On Jun 27, 2017, at 20:53, Hyun Kwon wrote:
>
>
> As you noted, the Xilinx DRM driver in Xilinx tree is missing many mainline
> features including the atomic mode setting and needs some restructuring.
> Please feel free to send patches to Xilinx git-dev, but note that we are also
Hi guys,
Note: I was a total DRM newbie at the beginning of this exercise. Now I would
say I'm just newbie. ;)
I am trying to implement our lvds panel using xilinx_drm on zynqmp. We are
composing our pipeline starting with the xilinx-vdma, then a few logic parts
from the ALI3 on zedboard ref d
Hi gang!
I was wondering why lvds-encoder.c is named like that.
(https://github.com/torvalds/linux/commit/67cc3e22b00f9027eaa0902ecf52ac5f4f5cac97)
The driver is clearly a drm_bridge, nested in the drm/bridge subdir... so why
not "lvds-bridge.c"?
Also, the associated bindings document is named "
Bonjour Laurent!
I was wondering why you choose to name the lvds-encoder.c driver like so.
(https://github.com/torvalds/linux/commit/67cc3e22b00f9027eaa0902ecf52ac5f4f5cac97)
The driver is clearly a drm_bridge, nested in the drm/bridge subdir... so why
not "lvds-bridge.c"?
Also, the associated b