Hi Maxime,
Il 17/02/2021 12:03, Maxime Ripard ha scritto:
Hi,
On Wed, Feb 10, 2021 at 05:22:37PM +0100, Marjan Pascolo wrote:
On Allwinner SoC interrupt debounce can be controlled by two oscillator
(32KHz and 24MHz) and a prescale divider.
Oscillator and prescale divider are set through
med "input-debounce-ns".
"input-debounce-ns" is checked only if "input-debounce"
property is not defined.
Suggested-by: Maxime Ripard
Signed-off-by: Marjan Pascolo
---
---
.../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 9 +++
drivers/pinctrl/sunxi/pinctrl-sun
y: Giulio Benetti
Tested-by: Marjan Pascolo
[Tested successfully with A13]
---
V2->V3:
- squash 2 patches into 1
V3->V4:
- add SUN4I_TCON0_IO_POL_DCLK_POSITIVE to regmap_update_bits() as suggested by
Maxime
V4->V5:
polarity is still wrong so:
- let's use SUN4I_TCON0_I
Hi Giulio,
You did a typo
Il 13/01/2021 17:05, Giulio Benetti ha scritto:
From: Giulio Benetti
During commit 88bc4178568b ("drm: Use new
DRM_BUS_FLAG_*_(DRIVE|SAMPLE)_(POS|NEG)EDGE flags") DRM_BUS_FLAG_*
macros have been changed to avoid ambiguity but just because of this
ambiguity previous D
Hi,
Quote "
I'm not really sure why we need the first patch of this series here?
That patch only seem to undo what you did in patch 1
"
And another question (probably could be a stupid one):
in "/[PATCH v2 2/2] drm/sun4i: tcon: improve DCLK polarity handling/" I
see you deleted:
-
