GPU,
>>>> providing graphics acceleration capabilities on the Lichee Pi 4A and
>>>> other boards based on the TH1520 SoC.
>>>>
>>>> Add fixed clock gpu_mem_clk, as the MEM clock on the T-HEAD SoC can't be
>>>> controlled program
391f30b41c5a24bb46dc6ef4161921e782d
[2/4] dt-bindings: gpu: img,powervr-rogue: Add TH1520 GPU support
commit: 337ebfda8a4f2627bf52e200cacf6f3a2f5ccf48
[4/4] drm/imagination: Enable PowerVR driver for RISC-V
commit: 6b53cf48d9339c75fa51927b0a67d8a6751066bd
Best regards,
--
Matt Coster
lable. For other platforms, it
> falls back to the existing manual clock and reset handling. The runtime
> PM callbacks continue to call the appropriate functions via the ops
> table.
>
> Signed-off-by: Michal Wilczynski
Reviewed-by: Matt Coster
Would you like me to take the non-D
t systems (RISCV && 64BIT) as
> the driver currently has an implicit dependency on a 64-bit platform.
>
> Add a dependency on MMU to fix a build warning on RISC-V configurations
> without an MMU.
>
> Reviewed-by: Ulf Hansson
> Reviewed-by: Bartosz Golaszewski
> S
Ulf Hansson
> Reviewed-by: Drew Fustini
> Reviewed-by: Bartosz Golaszewski
> Signed-off-by: Michal Wilczynski
I still don't really know if I should be Rb-ing DTS changes, so:
Acked-by: Matt Coster
Cheers,
Matt
> ---
> arch/riscv/boot/dts/thead/th1520.dtsi | 21 ++
/
> [1]
>
> Reviewed-by: Krzysztof Kozlowski
> Signed-off-by: Michal Wilczynski
Reviewed-by: Matt Coster
Cheers,
Matt
> ---
> .../devicetree/bindings/gpu/img,powervr-rogue.yaml | 37
> +-
> 1 file changed, 29 insertions(+), 8 deletions(-)
>
> dif
BLED(CONFIG_POWER_SEQUENCING)
>
> Again, this should not be needed. Instead, the call to
> devm_pwrseq_get() should return an error from a stub function if
> CONFIG_POWER_SEQUENCING is not set, right?
>
> The similar should apply to pwrseq_power_on|off(), right?
>
>> +
e")
> Fixes: 000a45dce7ad ("drm/gpuvm: Pass map arguments through a struct")
> Suggested-by: Boris Brezillon
> Suggested-by: Danilo Krummrich
> Cc: Danilo Krummrich
> Cc: Matt Coster
> Cc: Boris Brezillon
> Cc: Rob Clark
> Cc: Matthew Brost
> Cc:
al argument is added.
>
> Cc: Danilo Krummrich
> Cc: Brendan King
> Cc: Matt Coster
> Cc: Boris Brezillon
> Cc: Caterina Shablia
> Cc: Rob Clark
> Cc: Matthew Brost
> Cc:
> Co-developed-by: Himal Prasad Ghimiray
> Signed-off-by: Himal Prasad Ghimiray
>properties:
> power-domains:
> - minItems: 2
> + items:
> +- description: Power domain A
> +- description: Power domain B
> power-domain-names:
>minItems: 2
> + required:
> +- power-domains
> +- power-domain-names
>
>- if:
>properties:
>
--
Matt Coster
E: matt.cos...@imgtec.com
OpenPGP_signature.asc
Description: OpenPGP digital signature
On 25/07/2025 12:08, Krzysztof Kozlowski wrote:
> On 25/07/2025 11:00, Matt Coster wrote:
>> On 25/07/2025 07:59, Krzysztof Kozlowski wrote:
>>> On Thu, Jul 24, 2025 at 04:18:59PM +0200, Michal Wilczynski wrote:
>>>> Update the img,powervr-rogue.yaml to i
>>- items:
>>- enum:
>>- ti,j721s2-gpu
>> @@ -84,11 +89,29 @@ allOf:
>> compatible:
>>contains:
>> const: img,img-rogue
>> + not:
>
> Previous patch was completely different!
>
> You cannot keep tags when you completely rewrite the patch. Drop all
> reviews and all acks.
>
> Above code is confusing and not correct, you just stuffed multiple if
> causes.
>
> Best regards,
> Krzysztof
>
--
Matt Coster
E: matt.cos...@imgtec.com
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On 23/07/2025 17:26, Michal Wilczynski wrote:
> On 7/23/25 11:45, Matt Coster wrote:
>> On 25/06/2025 15:41, Krzysztof Kozlowski wrote:
>>> On 25/06/2025 16:18, Michal Wilczynski wrote:
>>>>
>>>>
>>>> On 6/25/25 15:55, Krzysztof Kozlowski wro
return 0;
>
> -err_reset_assert:
> - reset_control_assert(pvr_dev->reset);
> -
> -err_mem_clk_disable:
> - clk_disable_unprepare(pvr_dev->mem_clk);
> -
> -err_sys_clk_disable:
> - clk_disable_unprepare(pvr_dev->sys_clk);
> -
> -err_core
On 25/06/2025 15:41, Krzysztof Kozlowski wrote:
> On 25/06/2025 16:18, Michal Wilczynski wrote:
>>
>>
>> On 6/25/25 15:55, Krzysztof Kozlowski wrote:
>>> On 25/06/2025 14:45, Michal Wilczynski wrote:
>>>>
>>>>
>>>> On 6/24/25 15:5
struct_size_t() macro and
put it to good use wherever the size of the structure in question is
computed.
[1]:
https://lore.kernel.org/r/20250606-sprase-reasoning-comments-v1-1-433c0ff11...@imgtec.com
Signed-off-by: Matt Coster
---
Matt Coster (2):
drm/imagination: Add and use FLEX_ARRAY_CHECK
It makes little to no sense to use SIZE_CHECK() on flexible structures, so
let's validate something that actually matters instead.
Signed-off-by: Matt Coster
---
drivers/gpu/drm/imagination/pvr_rogue_fwif_check.h | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
The helpers for dealing with flexible structures exist, so let's use them.
Signed-off-by: Matt Coster
---
drivers/gpu/drm/imagination/pvr_queue.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/imagination/pvr_queue.c
b/drivers/gp
d073c64e75e150510d7e6b4b04f7
Best regards,
--
Matt Coster
2ce1d7d27533c4b98307380804c
Best regards,
--
Matt Coster
r
> state if acquiring a power reference is not possible.
>
> Signed-off-by: Alessio Belle
Reviewed-by: Matt Coster
I'll apply this to drm-misc-next on Friday if nobody has any objections.
Cheers,
Matt
> ---
> drivers/gpu/drm/imagination/pvr_power.c | 59
> +
Alessio Belle
Thanks for this fix! I'll push it to drm-misc-fixes on Friday if there
are no objections (with the blank line above removed; no need to re-send
for that), so:
Reviewed-by: Matt Coster
Cheers,
Matt
> ---
> drivers/gpu/drm/imagination/pvr_power.c | 4 ++--
>
h that as far as the
GPU is concerned (see the attached snippet from integration guide).
Since power nodes are ref-counted anyway, do we just use the same node
for both domains and let the driver up/down-count it twice?
Cheers,
Matt
> then:
>properties:
> power-domains:
>
--
Matt Coster
E: matt.cos...@imgtec.com
OpenPGP_signature.asc
Description: OpenPGP digital signature
depends on MMU
Nit: can you keep this alphabetical?
Cheers,
Matt
[1]: https://lore.kernel.org/r/202506191323.zd1fszqb-...@intel.com/
[2]: https://lore.kernel.org/r/202506201103.gx6da9gx-...@intel.com/
> select DRM_EXEC
> select DRM_GEM_SHMEM_HELPER
> select DRM_SCHED
>
--
Matt Coster
E: matt.cos...@imgtec.com
OpenPGP_signature.asc
Description: OpenPGP digital signature
> + goto err_power_off;
> }
>
> drm_dev_exit(idx);
>
> return 0;
>
> -err_reset_assert:
> - reset_control_assert(pvr_dev->reset);
> -
> -err_mem_clk_disable:
> - clk_disable_unprepare(pvr_dev->mem_clk);
> -
> -err_sys_clk_disable:
> - clk_disable_unprepare(pvr_dev->sys_clk);
> -
> -err_core_clk_disable:
> - clk_disable_unprepare(pvr_dev->core_clk);
> -
> +err_power_off:
> + pvr_dev->soc_data->power_off(pvr_dev);
> err_drm_dev_exit:
> drm_dev_exit(idx);
>
> diff --git a/drivers/gpu/drm/imagination/pvr_power.h
> b/drivers/gpu/drm/imagination/pvr_power.h
> index
> ada85674a7ca762dcf92df40424230e1c3910342..d91d5f3f39b61f81121357f4187b1a6e09b3dec0
> 100644
> --- a/drivers/gpu/drm/imagination/pvr_power.h
> +++ b/drivers/gpu/drm/imagination/pvr_power.h
> @@ -41,4 +41,10 @@ pvr_power_put(struct pvr_device *pvr_dev)
> int pvr_power_domains_init(struct pvr_device *pvr_dev);
> void pvr_power_domains_fini(struct pvr_device *pvr_dev);
>
> +/* Power sequence functions */
> +int pvr_power_on_sequence_manual(struct pvr_device *pvr_dev);
> +int pvr_power_off_sequence_manual(struct pvr_device *pvr_dev);
> +int pvr_power_on_sequence_pwrseq(struct pvr_device *pvr_dev);
> +int pvr_power_off_sequence_pwrseq(struct pvr_device *pvr_dev);
Perhaps the extracted structure of function pointers could be declared
here as e.g. struct pvr_power_sequence_ops, allowing these functions to
be contained to pvr_power.c.
Cheers,
Matt
> +
> #endif /* PVR_POWER_H */
>
--
Matt Coster
E: matt.cos...@imgtec.com
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Description: OpenPGP digital signature
On 05/06/2025 10:57, Ulf Hansson wrote:
> On Wed, 4 Jun 2025 at 18:48, Matt Coster wrote:
>>
>> On 03/06/2025 13:27, Ulf Hansson wrote:
>>> On Fri, 30 May 2025 at 00:24, Michal Wilczynski
>>> wrote:
>>>>
>>>> Add a device tree node for t
k-names = "core", "mem", "sys";
>> + power-domains = <&aon TH1520_GPU_PD>;
>> + power-domain-names = "a";
>
> If the power-domain-names are really needed, please pick a
> useful/descriptive name.
This isn't the first time our unfortunate power domain names have come
up [1][2]. Sadly, we're stuck with them for Rogue.
Matt
[1]: https://lore.kernel.org/r/ff4e96e4-ebc2-4c50-9715-82ba3d7b8...@imgtec.com/
[2]: https://lore.kernel.org/r/cc6a19b3-ba35-465c-9fa6-a764df7c0...@imgtec.com/
>
> [...]
>
> Kind regards
> Uffe
--
Matt Coster
E: matt.cos...@imgtec.com
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Description: OpenPGP digital signature
it: 1300a7f8a7d4c5f88de30312cf34448b96539c23
[2/2] drm/imagination: Add reset controller support for GPU initialization
commit: 3a2b7389feea9a7afd18d58cda59b7a989445f38
Best regards,
--
Matt Coster
ion: avoid unused-const-variable warning
commit: 3206a96675342badb0254558ba4b4c8764aa3ae7
Best regards,
--
Matt Coster
e haven't always
made it easy for you!
This series (sub-series?) is:
Reviewed-by: Matt Coster
If nobody has any objections, I'll apply it to drm-misc-next tomorrow.
Cheers,
Matt
>
> [1] -
> https://lore.kernel.org/all/20250414-apr_14_for_sending-v2-0-70c5a
like
enough of my concerns were due solely to my ignorance that I'd rather
just take this patch as-is than spend time reworking it. (Thanks to Jani
and Andi for filling gaps in my knowledge too!)
To that end,
Reviewed-by: Matt Coster
And I'll take this through drm-misc-next tomorrow
nge in the DT bindings,
> doesn’t appear to conflict with the work you're doing for Rogue series
> enablement.
Agreed, it still applies cleanly on top of drm-misc-next after we landed
the BXS series.
>
> Would you prefer if I re-send them as a mini-series so you can consid
On 10/04/2025 10:55, Matt Coster wrote:
> Use the new compatible string introduced earlier (in "dt-bindings: gpu:
> img: More explicit compatible strings") and add a name to the single power
> domain for this GPU (introduced in "dt-bindings: gpu: img: Power domain
&
if (err)
>> +return err;
>> +}
>
> So, how does that work for devfreq? I can understand the rationale for
> resets and the sys clock, but the core clock at least should really be
> handled by the driver.
I agree, this feels a bit "all or nothing
On 01/04/2025 17:45, Michal Wilczynski wrote:
> On 3/26/25 17:48, Matt Coster wrote:
>> The first compatible strings added for the AXE-1-16M are not sufficient to
>> accurately describe all the IMG Rogue GPUs. The current "img,img-axe"
>> string refers to the entire
). That patch adds the function pvr_vm_unmap_obj()
which is used here.
[1]:
https://lore.kernel.org/r/20250226-hold-drm_gem_gpuva-lock-for-unmap-v2-1-3fdacded2...@imgtec.com
Signed-off-by: Sarah Walker
Signed-off-by: Matt Coster
Reviewed-by: Frank Binns
---
Changes in v6:
- Add Frank'
Since we already added a generic compatible string for all IMG Rogue GPUs
("img,img-rogue"), all that's needed here is to link the appropriate
firmware for the BXS-4-64 GPU in the AM68.
Signed-off-by: Matt Coster
Reviewed-by: Frank Binns
---
Changes in v6:
- Add Frank's Rb
different GPU power
topologies.
Signed-off-by: Matt Coster
Reviewed-by: Frank Binns
---
Changes in v6:
- Add Frank's Rb
- Link to v5:
https://lore.kernel.org/r/20250326-sets-bxs-4-64-patch-v1-v5-5-e4c46e828...@imgtec.com
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/r/
Currently only MIPS firmware processors use ELF-formatted firmware. When
adding support for RISC-V firmware processors, it will be useful to have
ELF handling functions ready to go.
Signed-off-by: Matt Coster
Reviewed-by: Frank Binns
---
Changes in v6:
- Move loop variable as per
https
from it e.g. via pvr_power_reset().
Note that Rogue GPUs may send interrupts to the host for all types of
safety events, not just the two above. For events not handled by the host,
clearing the associated interrupt is sufficient.
Signed-off-by: Alessio Belle
Signed-off-by: Matt Coster
Reviewed-by
Use the new compatible string introduced earlier (in "dt-bindings: gpu:
img: More explicit compatible strings") and add a name to the single power
domain for this GPU (introduced in "dt-bindings: gpu: img: Power domain
details").
Signed-off-by: Matt Coster
---
Changes in v6:
memory allocations through the CPU cache. In fact, this
can be done whenever the dma_coherent attribute is present.
Signed-off-by: Matt Coster
Reviewed-by: Frank Binns
---
Changes in v6:
- Add Frank's Rb
- Link to v5:
https://lore.kernel.org/r/20250326-sets-bxs-4-64-patch-v1-v5-15-e4c4
errogated from the device at runtime,
we can match on the generic "img,img-rogue" and avoid adding more entries
with NULL data members (barring hardware quirks).
Signed-off-by: Matt Coster
Reviewed-by: Frank Binns
---
Changes in v6:
- Add Frank's Rb
- Link to v5:
https://lore.kern
ard
declaration down here. Can you move it up to the top of the file with
the others?
>
> @@ -73,6 +72,5 @@ void pvr_fw_trace_mask_update(struct pvr_device *pvr_dev,
> u32 old_mask,
> u32 new_mask);
>
> void pvr_fw_trace_debugfs_init(struct pvr_device *pvr_dev, struct dentry
> *dir);
> -#endif /* defined(CONFIG_DEBUG_FS) */
Having said that, surely it makes sense to keep at least
*_debugfs_init() gated behind CONFIG_DEBUG_FS?
>
> #endif /* PVR_FW_TRACE_H */
--
Matt Coster
E: matt.cos...@imgtec.com
OpenPGP_signature.asc
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This is currently a callback function which takes no parameters; there's
no reason for this so let's make it a straightforward value in pvr_fw_defs.
Signed-off-by: Matt Coster
Reviewed-by: Frank Binns
---
Changes in v6:
- Add Frank's Rb
- Link to v5:
https://lore.kernel.org/r/20
o not have
an equivalent register.
Signed-off-by: Matt Coster
Reviewed-by: Frank Binns
---
Changes in v6:
- Add Frank's Rb
- Link to v5:
https://lore.kernel.org/r/20250326-sets-bxs-4-64-patch-v1-v5-8-e4c46e828...@imgtec.com
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/r/2025
- Use normal reg syntax for 64-bit values (P8/P21)
- Link to v1:
https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-0-4ed30e865...@imgtec.com
---
Alessio Belle (3):
drm/imagination: Update register defs for newer GPUs
drm/imagination: Mask GPU IRQs in threaded handler
d
With more than two firmware processor types, the if/else chain in
pvr_fw_init() gets a bit ridiculous. Use a static array indexed on
pvr_fw_processor_type (which is now a proper enum instead of #defines)
instead.
Signed-off-by: Matt Coster
Reviewed-by: Frank Binns
---
Changes in v6:
- Add
[1]: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel
[2]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/clocks.html
[3]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/devices.html
Signed-off-by: Matt Coster
---
Changes in v6:
- None
- Link to v5:
https://lore.ke
-to-be-added RISC-V firmware
processors cannot be masked in hardware. This change allows us to continue
using the threaded handler in GPUs with a RISC-V firmware.
For simplicity, the same approach is taken for all firmware processors.
Signed-off-by: Alessio Belle
Signed-off-by: Matt Coster
This allows for more versatility in checking and clearing firmware
registers used for interrupt handling.
Signed-off-by: Matt Coster
Reviewed-by: Frank Binns
---
Changes in v6:
- Add Frank's Rb
- Link to v5:
https://lore.kernel.org/r/20250326-sets-bxs-4-64-patch-v1-v5-12-e4c4
Unlike AXE-1-16M, BXS-4-64 uses two power domains.
Like the existing AXE-1-16M integration, BXS-4-64 uses the single clock
integration in the TI k3-j721s2.
Signed-off-by: Matt Coster
Reviewed-by: Krzysztof Kozlowski
---
Changes in v6:
- Add Krzysztof's Rb
- Link to v5:
https://lore.kerne
From: Alessio Belle
Update the register define header to a newer version that covers more
recent GPUs, including BXS-4-64.
Signed-off-by: Alessio Belle
Signed-off-by: Matt Coster
Reviewed-by: Frank Binns
---
Changes in v6:
- Add Frank's Rb
- Link to v5:
https://lore.kernel.org/r/202
Now that enable_reg isn't used, rename the previously shared event_mask to
status_mask since it's only used with status_reg.
Signed-off-by: Matt Coster
Reviewed-by: Frank Binns
---
Changes in v6:
- Add Frank's Rb
- Link to v5:
https://lore.kernel.org/r/20250326-sets-bxs-4-6
and
this property should be applied wherever it accurately describes the
vendor integration.
Note that the new required properties for power domains are conditional on
the new base compatible string to avoid an ABI break.
Signed-off-by: Matt Coster
Reviewed-by: Krzysztof Kozlowski
---
Changes in
06a9697d068711140e9c47
Best regards,
--
Matt Coster
With more than two firmware processor types, the if/else chain in
pvr_fw_init() gets a bit ridiculous. Use a static array indexed on
pvr_fw_processor_type (which is now a proper enum instead of #defines)
instead.
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https
). That patch adds the function pvr_vm_unmap_obj()
which is used here.
[1]:
https://lore.kernel.org/r/20250226-hold-drm_gem_gpuva-lock-for-unmap-v2-1-3fdacded2...@imgtec.com
Signed-off-by: Sarah Walker
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/r
ad.
>
> Ensure all firmware GEM objects are destroyed if firmware image
> processing fails.
>
> [...]
Applied, thanks!
[1/1] drm/imagination: fix firmware memory leaks
commit: a5b230e7f3a55bd8bd8d012eec75a4b7baa671d5
Best regards,
--
Matt Coster
[1]: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel
[2]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/clocks.html
[3]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/devices.html
Signed-off-by: Matt Coster
---
Changes in v4:
- None
- Link to v3:
https://lore.ke
Use the new compatible string introduced earlier (in "dt-bindings: gpu:
img: More explicit compatible strings") and add a name to the single power
domain for this GPU (introduced in "dt-bindings: gpu: img: Power domain
details").
Signed-off-by: Matt Coster
---
Changes in v4:
-to-be-added RISC-V firmware
processors cannot be masked in hardware. This change allows us to continue
using the threaded handler in GPUs with a RISC-V firmware.
For simplicity, the same approach is taken for all firmware processors.
Signed-off-by: Alessio Belle
Signed-off-by: Matt Coster
From: Alessio Belle
Update the register define header to a newer version that covers more
recent GPUs, including BXS-4-64.
Signed-off-by: Alessio Belle
Signed-off-by: Matt Coster
---
Changes in v4:
- None
- Link to v3:
https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-3-143b3dbef
[1]: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel
[2]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/clocks.html
[3]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/devices.html
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https://lore.ke
Since we already added a generic compatible string for all IMG Rogue GPUs
("img,img-rogue"), all that's needed here is to link the appropriate
firmware for the BXS-4-64 GPU in the AM68.
Signed-off-by: Matt Coster
---
Changes in v4:
- None
- Link to v3:
https://lore.kernel.org/
). That patch adds the function pvr_vm_unmap_obj()
which is used here.
[1]:
https://lore.kernel.org/r/20250226-hold-drm_gem_gpuva-lock-for-unmap-v2-1-3fdacded2...@imgtec.com
Signed-off-by: Sarah Walker
Signed-off-by: Matt Coster
---
Changes in v4:
- Use pvr_vm_unmap_obj() in pvr_riscv_vm_unmap
memory allocations through the CPU cache. In fact, this
can be done whenever the dma_coherent attribute is present.
Signed-off-by: Matt Coster
---
Changes in v4:
- None
- Link to v3:
https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-15-143b3dbef...@imgtec.com
Changes in v3:
- Change
tps://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-0-4ed30e865...@imgtec.com
---
Alessio Belle (3):
drm/imagination: Update register defs for newer GPUs
drm/imagination: Mask GPU IRQs in threaded handler
drm/imagination: Handle Rogue safety event IRQs
Matt Coster (14):
On 02/04/2025 09:40, Alexandru Dadu wrote:
> Reduce the scope of some loop counters as these aren't needed outside
> the loops they're used in.
>
> Signed-off-by: Alexandru Dadu
Hi Alexandru,
Thanks for dragging us into the bright, bright future of (C)99!
Reviewed-by: Ma
fe53a1736b064
Best regards,
--
Matt Coster
errogated from the device at runtime,
we can match on the generic "img,img-rogue" and avoid adding more entries
with NULL data members (barring hardware quirks).
Signed-off-by: Matt Coster
---
Changes in v4:
- None
- Link to v3:
https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v
Use the new compatible string introduced earlier (in "dt-bindings: gpu:
img: More explicit compatible strings") and add a name to the single power
domain for this GPU (introduced in "dt-bindings: gpu: img: Power domain
details").
Signed-off-by: Matt Coster
---
Changes in v5:
This allows for more versatility in checking and clearing firmware
registers used for interrupt handling.
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/r/20250320-sets-bxs-4-64-patch-v1-v4-12-d987cf4ca...@imgtec.com
Changes in v4:
- None
- Link to v3
Unlike AXE-1-16M, BXS-4-64 uses two power domains.
Like the existing AXE-1-16M integration, BXS-4-64 uses the single clock
integration in the TI k3-j721s2.
Signed-off-by: Matt Coster
---
Changes in v5:
- Replace anyOf/const with enum
- Link to v4:
https://lore.kernel.org/r/20250320-sets-bxs-4
-to-be-added RISC-V firmware
processors cannot be masked in hardware. This change allows us to continue
using the threaded handler in GPUs with a RISC-V firmware.
For simplicity, the same approach is taken for all firmware processors.
Signed-off-by: Alessio Belle
Signed-off-by: Matt Coster
memory allocations through the CPU cache. In fact, this
can be done whenever the dma_coherent attribute is present.
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/r/20250320-sets-bxs-4-64-patch-v1-v4-15-d987cf4ca...@imgtec.com
Changes in v4:
- None
This is currently a callback function which takes no parameters; there's
no reason for this so let's make it a straightforward value in pvr_fw_defs.
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/r/20250320-sets-bxs-4-64-patch-v1-v4-10
and
this property should be applied wherever it accurately describes the
vendor integration.
Note that the new required properties for power domains are conditional on
the new base compatible string to avoid an ABI break.
Signed-off-by: Matt Coster
---
Changes in v5:
- Remove extra
o not have
an equivalent register.
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/r/20250320-sets-bxs-4-64-patch-v1-v4-8-d987cf4ca...@imgtec.com
Changes in v4:
- None
- Link to v3:
https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-8
Since we already added a generic compatible string for all IMG Rogue GPUs
("img,img-rogue"), all that's needed here is to link the appropriate
firmware for the BXS-4-64 GPU in the AM68.
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/
Currently only MIPS firmware processors use ELF-formatted firmware. When
adding support for RISC-V firmware processors, it will be useful to have
ELF handling functions ready to go.
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/r/20250320-sets-bxs-4
different GPU power
topologies.
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/r/20250320-sets-bxs-4-64-patch-v1-v4-5-d987cf4ca...@imgtec.com
Changes in v4:
- None
- Link to v3:
https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-5-143b3d
Now that enable_reg isn't used, rename the previously shared event_mask to
status_mask since it's only used with status_reg.
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/r/20250320-sets-bxs-4-64-patch-v1-v4-9-d987cf4ca...@imgtec.com
Cha
errogated from the device at runtime,
we can match on the generic "img,img-rogue" and avoid adding more entries
with NULL data members (barring hardware quirks).
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/r/20250320-sets-bxs-4-64-patch-v1-
from it e.g. via pvr_power_reset().
Note that Rogue GPUs may send interrupts to the host for all types of
safety events, not just the two above. For events not handled by the host,
clearing the associated interrupt is sufficient.
Signed-off-by: Alessio Belle
Signed-off-by: Matt Coster
---
Changes
From: Alessio Belle
Update the register define header to a newer version that covers more
recent GPUs, including BXS-4-64.
Signed-off-by: Alessio Belle
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/r/20250320-sets-bxs-4-64-patch-v1-v4-3-d987cf4ca
d30e865...@imgtec.com
---
Alessio Belle (3):
drm/imagination: Update register defs for newer GPUs
drm/imagination: Mask GPU IRQs in threaded handler
drm/imagination: Handle Rogue safety event IRQs
Matt Coster (14):
dt-bindings: gpu: img: Future-proofing enhancements
dt-
_kmalloc_large_node_noprof+0x2c/0x13c
> __kmalloc_noprof+0x48/0x4c0
> pvr_fw_init+0xb0c/0x1f50 [powervr]
>
> Cc: sta...@vger.kernel.org
> Fixes: cc1aeedb98ad ("drm/imagination: Implement firmware infrastructure and
> META FW support")
> Signed-off-by: Brendan
-after-free in
> pvr_queue_prepare_job+0x108/0x868 [powervr]
> [ 124.264893] Read of size 1 at addr 084cb960 by task
> kworker/u16:4/63
>
> Cc: sta...@vger.kernel.org
> Fixes: eaf01ee5ba28 ("drm/imagination: Implement job submission and
> scheduling")
> Si
This is currently a callback function which takes no parameters; there's
no reason for this so let's make it a straightforward value in pvr_fw_defs.
Signed-off-by: Matt Coster
---
Changes in v4:
- None
- Link to v3:
https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-10
and
this property should be applied wherever it accurately describes the
vendor integration.
Note that the new required properties for power domains are conditional on
the new base compatible string to avoid an ABI break.
Signed-off-by: Matt Coster
---
Changes in v4:
- Add img,img-rogue ba
from it e.g. via pvr_power_reset().
Note that Rogue GPUs may send interrupts to the host for all types of
safety events, not just the two above. For events not handled by the host,
clearing the associated interrupt is sufficient.
Signed-off-by: Alessio Belle
Signed-off-by: Matt Coster
---
Changes
With more than two firmware processor types, the if/else chain in
pvr_fw_init() gets a bit ridiculous. Use a static array indexed on
pvr_fw_processor_type (which is now a proper enum instead of #defines)
instead.
Signed-off-by: Matt Coster
---
Changes in v4:
- None
- Link to v3:
https
o not have
an equivalent register.
Signed-off-by: Matt Coster
---
Changes in v4:
- None
- Link to v3:
https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-8-143b3dbef...@imgtec.com
Changes in v3:
- Reference a different commit removing use of enable/disable ops.
- Link to v2:
https://lore.
Now that enable_reg isn't used, rename the previously shared event_mask to
status_mask since it's only used with status_reg.
Signed-off-by: Matt Coster
---
Changes in v4:
- None
- Link to v3:
https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-9-143b3dbef...@imgtec.com
Cha
This allows for more versatility in checking and clearing firmware
registers used for interrupt handling.
Signed-off-by: Matt Coster
---
Changes in v4:
- None
- Link to v3:
https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-12-143b3dbef...@imgtec.com
Changes in v3:
- None
- Link to v2
different GPU power
topologies.
Signed-off-by: Matt Coster
---
Changes in v4:
- None
- Link to v3:
https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-5-143b3dbef...@imgtec.com
Changes in v3:
- None
- Link to v2:
https://lore.kernel.org/r/20241118-sets-bxs-4-64-patch-v1-v2-6-3fd45d
Unlike AXE-1-16M, BXS-4-64 uses two power domains.
Like the existing AXE-1-16M integration, BXS-4-64 uses the single clock
integration in the TI k3-j721s2.
Signed-off-by: Matt Coster
---
Changes in v4:
- Add minItems: 1 to power-domain-names so we don't break single domain
bindings
- Add
Currently only MIPS firmware processors use ELF-formatted firmware. When
adding support for RISC-V firmware processors, it will be useful to have
ELF handling functions ready to go.
Signed-off-by: Matt Coster
---
Changes in v4:
- None
- Link to v3:
https://lore.kernel.org/r/20250310-sets-bxs-4
from it e.g. via pvr_power_reset().
Note that Rogue GPUs may send interrupts to the host for all types of
safety events, not just the two above. For events not handled by the host,
clearing the associated interrupt is sufficient.
Signed-off-by: Alessio Belle
Signed-off-by: Matt Coster
---
Changes
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