The changed name looks more accurate to the edp 1.4b spec.
Looks good to me.
Reviewed-by: Gwan-gyeong Mun
On Wed, 2021-04-21 at 15:02 -0700, José Roberto de Souza wrote:
> DP_PSR_EN_CFG bit 5 aka "Selective Update Region Scan Line Capture
> Indication" in eDP spec has a ambiguous name, so renami
On Fri, 2020-12-18 at 10:46 -0800, José Roberto de Souza wrote:
> Much more clear to read one function call than four lines doing this
> conversion.
>
> v7:
> - function renamed
> - calculating width and height before truncate
> - inlined
>
> Cc: Ville Syrjälä
> Cc: dri-devel@lists.freedesktop.o
On Mon, 2020-12-14 at 09:49 -0800, José Roberto de Souza wrote:
> Much more clear to read one function call than four lines doing this
> conversion.
>
> Cc: dri-devel@lists.freedesktop.org
> Cc: Gwan-gyeong Mun
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/drm_rect.c | 15 +
On Mon, 2020-12-14 at 08:55 +, Simon Ser wrote:
> > Userspace can set a damage clip with a negative coordinate,
> > negative
> > width or height or larger than the plane.
> > This invalid values could cause issues in some HW or even worst
> > enable
> > security flaws.
> >
> > v2:
> > - add de
Hi Ville,
Thank you for notifying me that. I definitely missed the crash.
Sorry for that.
Danial and Jani, I' under debugging the crash case.
If you are availabe please do not merge current version.
Br,
G.G.
>
On Fri, 2020-05-15 at 16:14 +0200, Daniel Vetter wrote:
> On Fri, May 15, 2020 at 04:
Hi Bartlomiej and Laurent Pinchart, can I have your ack for merging
this via drm-intel along
with the rest of the series, please?
BR,
G.G.
On Thu, 2020-05-14 at 09:07 +0300, Gwan-gyeong Mun wrote:
> It adds an unpack only function for DRM infoframe for dynamic range
> and
> mastering infoframe r
On Fri, 2020-03-27 at 14:56 +0200, Ville Syrjälä wrote:
> On Fri, Mar 27, 2020 at 07:27:56AM +0000, Mun, Gwan-gyeong wrote:
> > On Fri, 2020-03-20 at 13:57 +0200, Laurent Pinchart wrote:
> > > Hi Jani,
> > >
> > > On Fri, Mar 20, 2020 at 01:32:17PM +0200, Jani
On Fri, 2020-03-20 at 13:57 +0200, Laurent Pinchart wrote:
> Hi Jani,
>
> On Fri, Mar 20, 2020 at 01:32:17PM +0200, Jani Nikula wrote:
> > On Fri, 20 Mar 2020, Jani Nikula
> > wrote:
> > > On Tue, 11 Feb 2020, Gwan-gyeong Mun
> > > wrote:
> > > > It adds an unpack only function for DRM infoframe
On Wed, 2020-02-05 at 22:21 +0530, Shankar, Uma wrote:
> > -Original Message-
> > From: Intel-gfx On Behalf
> > Of Gwan-
> > gyeong Mun
> > Sent: Tuesday, February 4, 2020 4:50 AM
> > To: intel-...@lists.freedesktop.org
> > Cc: linux-fb...@vger.kernel.org; dri-devel@lists.freedesktop.org
>
On Wed, 2020-02-05 at 21:59 +0530, Shankar, Uma wrote:
> > -Original Message-
> > From: dri-devel On Behalf
> > Of Gwan-
> > gyeong Mun
> > Sent: Tuesday, February 4, 2020 4:50 AM
> > To: intel-...@lists.freedesktop.org
> > Cc: linux-fb...@vger.kernel.org; dri-devel@lists.freedesktop.org
>
On Wed, 2020-02-05 at 21:39 +0530, Shankar, Uma wrote:
> > -Original Message-
> > From: dri-devel On Behalf
> > Of Gwan-
> > gyeong Mun
> > Sent: Tuesday, February 4, 2020 4:50 AM
> > To: intel-...@lists.freedesktop.org
> > Cc: linux-fb...@vger.kernel.org; dri-devel@lists.freedesktop.org
>
On Wed, 2020-02-05 at 20:12 +0530, Shankar, Uma wrote:
> > -Original Message-
> > From: dri-devel On Behalf
> > Of Gwan-
> > gyeong Mun
> > Sent: Tuesday, February 4, 2020 4:50 AM
> > To: intel-...@lists.freedesktop.org
> > Cc: linux-fb...@vger.kernel.org; dri-devel@lists.freedesktop.org
>
On Sat, 2020-02-01 at 14:43 +0200, Jani Nikula wrote:
> On Fri, 31 Jan 2020, Gwan-gyeong Mun
> wrote:
> > When receiving video it is very useful to be able to log DP VSC
> > SDP.
> > This greatly simplifies debugging.
>
> Seems like a lot of the functions should really be in drm core.
>
> BR,
>
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Add comments to explain the ilk pipe csc operation a bit better.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 26 +---
> --
> 1 file changed, 21 insertions
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We're configuring the AVI infoframe quantization range bits as if
> we're always transmitting RGB pixels. Let's fix this so that we
> correctly indicate limited range YCC quantization range when
> transmitting YCbCr
Except typo, the changes look good to me.
Reviewed-by: Gwan-gyeong Mun
On Wed, 2019-09-18 at 19:05 +, Mun, Gwan-gyeong wrote:
> On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > On ILK-IVB the pipe colorspace is configured via PIP
Except typo, the changes look good to me.
Reviewed-by: Gwan-gyeong Mun
On Wed, 2019-09-18 at 19:03 +, Mun, Gwan-gyeong wrote:
> On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > On HSW the pipe colorspace is configured via PIPECO
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Prepare the pipe csc for YCbCr output on ilk/snb. The main difference
> to IVB+ is the lack of explicit post offsets, and instead we must
> configure the CSC info RGB->YUV mode (which takes care of offsetting
> Cb/C
On Wed, 2019-09-18 at 17:13 +0300, Ville Syrjälä wrote:
> On Mon, Sep 16, 2019 at 10:11:49AM +0300, Gwan-gyeong Mun wrote:
> > Function intel_dp_setup_hdr_metadata_infoframe_sdp handles
> > Infoframe SDP
> > header and data block setup for HDR Static Metadata. It enables
> > writing of
> > HDR meta
On Wed, 2019-09-18 at 17:08 +0300, Ville Syrjälä wrote:
> On Mon, Sep 16, 2019 at 10:11:46AM +0300, Gwan-gyeong Mun wrote:
> > Because between HDMI and DP have different colorspaces, it renames
> > drm_mode_create_colorspace_property() function to
> > drm_mode_create_hdmi_colorspace_property() func
On Wed, 2019-09-18 at 17:15 +0300, Ville Syrjälä wrote:
> On Mon, Sep 16, 2019 at 10:11:45AM +0300, Gwan-gyeong Mun wrote:
> > When BT.2020 Colorimetry output is used for DP, we should program
> > BT.2020
> > Colorimetry to MSA and VSC SDP. It adds output_colorspace to
> > intel_crtc_state struct a
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> On ILK-IVB the pipe colorspace is configured via PIPECONF
> (as opposed to PIPEMISC in BDW+). Let's configure+readout
> that stuff correctly.
>
> Enablling YCbCr 4:4:4 output will now be a simple matter of
Typo: En
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> On HSW the pipe colorspace is configured via PIPECONF
> (as opposed to PIPEMISC in BDW+). Let's configure+readout
> that stuff correctly.
>
> Enablling YCbCr 4:4:4 output will now be a simple matter of
Typo: Enabll
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Make intel_get_crtc_ycbcr_config() simpler and rename it
> to bdw_get_pipemisc_output_format() to better reflect what
> it does.
>
> Also toss in some comments to document that the 4:2:0 PIPECONF
> bits are glk+ on
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Now that we have standard defines for the MSA MISC bits lets use
> them on HSW+ where we program these directly into the TRANS_MSA_MISC
> register.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/di
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Since HSW the PIPECONF progressive vs. interlaced selection is done
> with just two bits instead of the earlier three. Let's not look at
> the
> extra bit on HSW+. Also gen2 doesn't support interlaced displays at
>
On Thu, 2019-07-18 at 19:45 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> crtc_state->limited_color_range only applies to RGB output but
> we're currently setting it even for YCbCr output. That will
> lead to conflicting MSA and PIPECONF settings which can mess
> up the image. Let's make
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Pull the code for computing the limited color range
> setting into a small helper. We'll add a bit more to it
> later.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 30 +
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Looks like we're currently setting the MSA to xvYCC BT.709 instead
> of the YCbCr BT.601 claimed by the comment. But even that comment
> is wrong since we configure the CSC matrix to BT.709.
>
> Let's remove the bo
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Add definitions for the MSA (Main Stream Attribute) MISC bits. On
> some hardware you can program these directly into a register.
>
> Signed-off-by: Ville Syrjälä
> ---
> include/drm/drm_dp_helper.h | 42
> ++
On Fri, 2019-09-13 at 22:13 +0300, Ville Syrjälä wrote:
> On Thu, Sep 12, 2019 at 02:33:34PM +0300, Gwan-gyeong Mun wrote:
> > Because between HDMI and DP have different colorspaces, it renames
> > drm_mode_create_colorspace_property() function to
> > drm_mode_create_hdmi_colorspace_property() func
On Sat, 2019-09-07 at 21:43 -0400, Ilia Mirkin wrote:
> On Sat, Sep 7, 2019 at 7:20 PM Mun, Gwan-gyeong
> wrote:
> > On Fri, 2019-09-06 at 09:24 -0400, Ilia Mirkin wrote:
> > > On Fri, Sep 6, 2019 at 7:43 AM Ville Syrjälä
> > > wrote:
> > > > On Fri,
On Mon, 2019-09-09 at 13:25 +0300, Ville Syrjälä wrote:
> On Sat, Sep 07, 2019 at 11:19:55PM +0000, Mun, Gwan-gyeong wrote:
> > On Fri, 2019-09-06 at 09:24 -0400, Ilia Mirkin wrote:
> > > On Fri, Sep 6, 2019 at 7:43 AM Ville Syrjälä
> > > wrote:
> > > > O
; > > > Sent: Tuesday, September 3, 2019 6:12 PM
> > > > To: Mun, Gwan-gyeong
> > > > Cc: Intel Graphics Development > > > >; Shankar, Uma
> > > > ; dri-devel <
> > > > dri-devel@lists.freedesktop.org>
> > > > Sub
On Tue, 2019-08-27 at 01:14 +0530, Shankar, Uma wrote:
> > -Original Message-
> > From: Mun, Gwan-gyeong
> > Sent: Friday, August 23, 2019 3:23 PM
> > To: intel-...@lists.freedesktop.org
> > Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <
>
On Mon, 2019-09-02 at 17:44 +0300, Ville Syrjälä wrote:
> On Fri, Aug 23, 2019 at 12:52:29PM +0300, Gwan-gyeong Mun wrote:
> > In order to use colorspace property to Display Port connectors, it
> > extends
> > DRM_MODE_CONNECTOR_DisplayPort connector_type on
> > drm_mode_create_colorspace_property
On Mon, 2019-09-02 at 17:43 +0300, Ville Syrjälä wrote:
> On Fri, Aug 23, 2019 at 12:52:28PM +0300, Gwan-gyeong Mun wrote:
> > When BT.2020 Colorimetry output is used for DP, we should program
> > BT.2020
> > Colorimetry to MSA and VSC SDP. It adds output_colorspace to
> > intel_crtc_state struct a
On Tue, 2019-05-21 at 13:14 +0300, Laurent Pinchart wrote:
> Hello Jani,
>
> On Tue, May 21, 2019 at 09:44:04AM +0300, Jani Nikula wrote:
> > On Mon, 20 May 2019, Gwan-gyeong Mun
> > wrote:
> > > VSC SDP Payload for PSR is one of data block type of SDP
> > > (Secondaray Data
> > > Packet). In ord
On Fri, 2019-05-17 at 15:36 +0200, Maarten Lankhorst wrote:
> Op 10-05-2019 om 03:53 schreef Gwan-gyeong Mun:
> > Function intel_pixel_encoding_setup_vsc handles vsc header and data
> > block
> > setup for pixel encoding / colorimetry format.
> >
> > Setup VSC header and data block in function
> >
On Wed, 2019-05-08 at 20:58 +0300, Ville Syrjälä wrote:
> On Wed, May 08, 2019 at 11:17:56AM +0300, Gwan-gyeong Mun wrote:
> > Data M/N calculations were assumed a bpp as RGB format. But when we
> > are
> > using YCbCr 4:2:0 output format on DP, we should change bpp
> > calculations
> > as YCbCr 4:
On Wed, 2019-05-08 at 20:56 +0300, Ville Syrjälä wrote:
> On Wed, May 08, 2019 at 11:17:54AM +0300, Gwan-gyeong Mun wrote:
> > Function intel_pixel_encoding_setup_vsc handles vsc header and data
> > block
> > setup for pixel encoding / colorimetry format.
> >
> > Setup VSC header and data block in
On Wed, 2019-05-08 at 20:32 +0300, Ville Syrjälä wrote:
> On Wed, May 08, 2019 at 11:17:53AM +0300, Gwan-gyeong Mun wrote:
> > SDP VSC Header and Data Block follow DP 1.4a spec, section
> > 2.2.5.7.5,
> > chapter "VSC SDP Payload for Pixel Encoding/Colorimetry Format".
> >
> > Signed-off-by: Gwan-
On Thu, Apr 18, 2019 at 7:33 PM Jani Nikula wrote:
>
> On Thu, 18 Apr 2019, Gwan-gyeong Mun wrote:
> > The hotplug detection routine of drm_helper_hpd_irq_event() can detect
> > changing of status of connector, but it can not detect changing of
> > properties of the connector.
> > e.g. changing o
On Thu, 2019-04-18 at 10:28 +0200, Daniel Vetter wrote:
> On Thu, Apr 18, 2019 at 11:09:29AM +0300, Gwan-gyeong Mun wrote:
> > The hotplug detection routine of drm_helper_hpd_irq_event() can
> > detect
> > changing of status of connector, but it can not detect changing of
> > properties of the conn
On Mon, 2019-04-15 at 18:32 +0200, Daniel Vetter wrote:
> On Thu, Apr 11, 2019 at 05:36:30PM +0300, Gwan-gyeong Mun wrote:
> > This patch series fix missed detection of changing of edid on
> > between
> > suspend and resume.
> > First patch fixes drm_helper_hdp_irq_event() in order to fix a
> > bel
On Thu, 2019-04-11 at 17:00 +0100, Lisovskiy, Stanislav wrote:
> On Thu, 2019-04-11 at 17:36 +0300, Gwan-gyeong Mun wrote:
> > The hotplug detection routine of drm_helper_hpd_irq_event() can
> > detect
> > changing of status of connector, but it can not detect changing of
> > edid.
> >
> > Followi
On Fri, 2018-08-03 at 20:12 +0100, Chris Wilson wrote:
> Quoting Gwan-gyeong Mun (2018-08-03 17:41:50)
>
> Even for trivial patches, always include a changelog. In this case, I
> added "Trivial typo, s/loose/lose/, in i915_drm_resume."
>
> > Signed-off-by: Gwan-gyeong Mun
>
> Reviewed-by: Chris
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