Hi, guys,
On 3/19/19 1:53 PM, Maxime Ripard wrote:
On Mon, Mar 11, 2019 at 09:36:27PM +0530, Jagan Teki wrote:
On Mon, Mar 11, 2019 at 9:08 PM Maxime Ripard wrote:
On Mon, Mar 11, 2019 at 07:06:24PM +0530, Jagan Teki wrote:
pll-video => pll-mipi => tcon0 => tcon0-pixel-clock is the typical
M
Hi, Jagan,
On 3/15/19 4:45 PM, Maxime Ripard wrote:
On Fri, Mar 15, 2019 at 02:32:55PM +0100, Paul Kocialkowski wrote:
Hi,
On Fri, 2019-03-15 at 18:38 +0530, Jagan Teki wrote:
Some display panels would come up with a non-DSI output which
can have an option to connect DSI interface by means of
Eric, thanks for answer,
I am in doubt the type of my panel. It is Himax HX8379A-based panel.
Is there a deterministic way to find out which type of panel I have,
video or command ?
Sergey
On 12/17/18 9:12 PM, Eric Anholt wrote:
Sergey Suloev writes:
Eric, Noralf,
could either of
Eric, Noralf,
could either of you answer a question about Vc4 DRM, please ?
I am trying to connect MIPI DSI display to VC4 but it isn't showing
anything. I have noticed
that the DSI host transfer() method vc4_dsi_host_transfer gets called
for the commands that
I am sending from my panel driv
Hi, Jagan,
On 11/3/18 1:08 PM, Jagan Teki wrote:
Loop N1 instruction delay for burst mode lcd panel are
computed as per BSP code.
Reference code is available in BSP
(in drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
dsi_dev[sel]->dsi_inst_loop_num.bits.loop_n1=
(panel->lcd_ht-pan
To be exact, the issue does not happen in case I use default kernel
config but only with the custom one.
On 10/2/18 2:14 PM, Noralf Trønnes wrote:
Den 01.10.2018 21.45, skrev Noralf Trønnes:
Sergey Suloev reported a crash happening in drm_client_dev_hotplug()
when fbdev had failed to
This doesn't seem to fix the initially reported issue. The problem still
exists with 4.19.
On 10/2/18 2:14 PM, Noralf Trønnes wrote:
Den 01.10.2018 21.45, skrev Noralf Trønnes:
Sergey Suloev reported a crash happening in drm_client_dev_hotplug()
when fbdev had failed to reg
Hi, Stefan,
On 09/30/2018 10:38 PM, Stefan Wahren wrote:
Hi Sergey,
Sergey Suloev hat am 30. September 2018 um 15:24
geschrieben:
Here is my log
[ 2.868157] [drm:drm_setup_crtcs [drm_kms_helper]] connector 29
enabled? yes
[ 2.868199] [drm:drm_setup_crtcs [drm_kms_helper
well.
Sergey
On 09/29/2018 08:14 PM, Noralf Trønnes wrote:
Den 28.09.2018 23.01, skrev Stefan Wahren:
Hi,
Sergey Suloev already reported this NULL pointer dereference [1]. Now
he was able to provide a Kernel config and i'm able to reproduce it
with a Raspberry Pi 3 (arm64) and Linux 4.
c4-drm soc:gpu: [drm:drm_fb_helper_fbdev_setup
[drm_kms_helper]] *ERROR* Failed to set fbdev configuration
On 09/30/2018 03:29 PM, Noralf Trønnes wrote:
Den 29.09.2018 22.52, skrev Sergey Suloev:
Hi,
the last error message seems to come from the following config option:
CONFIG_DRM_FBDEV_OVERALLOC=200
Chan
I have no idea where 2880 is coming from, my monitor has resolution 1280
* 1024.
Is this a DRM bug ?
On 09/30/2018 03:29 PM, Noralf Trønnes wrote:
Den 29.09.2018 22.52, skrev Sergey Suloev:
Hi,
the last error message seems to come from the following config option
moment.
Sergey
On 09/29/2018 08:14 PM, Noralf Trønnes wrote:
Den 28.09.2018 23.01, skrev Stefan Wahren:
Hi,
Sergey Suloev already reported this NULL pointer dereference [1]. Now
he was able to provide a Kernel config and i'm able to reproduce it
with a Raspberry Pi 3 (arm64) and Linux 4.1
,
Sergey Suloev already reported this NULL pointer dereference [1]. Now
he was able to provide a Kernel config and i'm able to reproduce it
with a Raspberry Pi 3 (arm64) and Linux 4.19-rc5. It seems like a
invalid config [2] for vc4, but nevertheless the driver shouldn't
crash at
Another boot gave me a little bit different result
https://pastebin.com/FAwuVQf9
Please, see if you can help.
Forwarded Message
Subject:vc4 in v4.19-rc2
Date: Thu, 6 Sep 2018 11:01:01 +0300
From: Sergey Suloev
To: e...@anholt.net
CC: dri-devel
Hi,
On 09/05/2018 10:16 AM, Maxime Ripard wrote:
On Tue, Sep 04, 2018 at 12:40:44PM +0800, Icenowy Zheng wrote:
Video PLLs on A64 can be set to higher rate that it is actually
supported by HW.
Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP
clock driver. Interestengly,
Hi, Eric,
I found a critical issue with vc4 in v4.19-rc2. See log.
https://pastebin.com/PDUW99Na
Thank you,
Sergey
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Hi,
On 09/05/2018 10:16 AM, Maxime Ripard wrote:
On Tue, Sep 04, 2018 at 12:40:44PM +0800, Icenowy Zheng wrote:
Video PLLs on A64 can be set to higher rate that it is actually
supported by HW.
Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP
clock driver. Interestengly, u
Hi, guys,
On 05/18/2018 05:46 PM, Jernej Škrabec wrote:
Hi,
Dne petek, 18. maj 2018 ob 12:01:16 CEST je Maxime Ripard napisal(a):
On Fri, May 18, 2018 at 03:15:22PM +0530, Jagan Teki wrote:
From: Jernej Skrabec
Some SoCs with DW HDMI have multiple possible clock parents, like A64
and R40.
Hi, Jernej,
On 05/18/2018 06:15 PM, Jernej Škrabec wrote:
Hi,
Dne petek, 18. maj 2018 ob 17:09:40 CEST je Sergey Suloev napisal(a):
Hi, guys,
On 05/18/2018 05:46 PM, Jernej Škrabec wrote:
Hi,
Dne petek, 18. maj 2018 ob 12:01:16 CEST je Maxime Ripard napisal(a):
On Fri, May 18, 2018 at 03
Hi, Giulio,
On 05/05/2018 12:52 AM, Giulio Benetti wrote:
Hi Maxime!
Il 04/05/2018 10:06, Maxime Ripard ha scritto:
Hi,
On Wed, May 02, 2018 at 06:41:34PM +0200, Giulio Benetti wrote:
You don't have to handcode the fragments anymore with the new syntax,
and U-Boot makes it really trivial to
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