On 2016-08-21 19:22, Fabio Estevam wrote:
> From: Fabio Estevam
>
> In fsl_dcu_drm_pm_resume() we should disable the previously enabled
> clock (fsl_dev->clk) when enabling fsl_dev->pix_clk fails.
>
> Signed-off-by: Fabio Estevam
Applied, thanks!
--
Stefan
On 2016-07-25 00:08, Wei Yongjun wrote:
> Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR.
>
> Generated by: scripts/coccinelle/api/ptr_ret.cocci
>
> Signed-off-by: Wei Yongjun
Applied!
--
Stefan
rent endianness. Check
>> endianness using the device-tree property "big-endian" to determine the
>> location of DIV_RATIO.
>>
>> Cc: stable at vger.kernel.org
>> Fixes: 2d701449bce1 ("drm/fsl-dcu: use common clock framework for pixel
>> clock divide
On 2016-09-03 03:49, Mark Brown wrote:
> On Fri, Sep 02, 2016 at 02:22:46PM -0700, Stefan Agner wrote:
>> I guess the problem is that regmap_write does byte swapping because
>> ls1021a.dtsi defines the whole DCU register space to be big-endian. So
>> you end up doing byte swa
On 2016-09-04 19:28, Meng Yi wrote:
> Hi Stefan,
>
>> > + */
>> > +static u32 swap_bytes(u16 var)
>>
>> We certainly don't want a byte swapping function in the driver. I am sure
>> Linux
>> has appropriate functions for that already, however, I am not convinced that
>> we need that at all.
>>
>
Hi Meng, hi Mark,
[added Mark Brown to discuss the endian issue]
On 2016-07-15 01:50, Meng Yi wrote:
> Gamma correction is optional and can be used to adjust the color
> output values to match the gamut of a particular TFT LCD panel
>
> Signed-off-by: Meng Yi
> ---
> drivers/gpu/drm/fsl-dcu/Kc
bce1 ("drm/fsl-dcu: use common clock framework for pixel clock
divider")
Reported-by: Meng Yi
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
b
On 2016-08-31 23:42, Meng Yi wrote:
> Hi Stefan,
>
> Could you test this patch on vf610, I think it will woks fine.
See comment below.
>
> When could you merge this path? And how about the patches for gamma
> correction and multi-layer support by the way?
Still need to look in those patches. I
On 2016-08-22 00:13, Meng Yi wrote:
>> fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
>> pix_clk_in_name, 0, base + DCU_DIV_RATIO,
>> -0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
>> +24, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
>
Hi Dave,
This adds drm bridge support for the NXP/Freescale DCU. The patchset
has been discussed on the mailing list since quite some time...
Plus there is a small fix provided by Peter.
--
Stefan
The following changes since commit f82c13722275b6aca3a956a82846465ec789b367:
Merge branch 'exyno
On 2016-07-14 23:53, Meng Yi wrote:
> This patch rework the output code to add of_graph dt binding support
> for panel device and also keeps the backward compatibility
>
> Signed-off-by: Meng Yi
Applied, with Rob's Ack from the earlier documentation only patch for
the Documentation part.
--
Ste
On 2016-07-14 03:54, Meng Yi wrote:
> The current output code only supports connection to drm panels.
> Add code to support drm bridge, to support connections to
> external connectors.
>
> Signed-off-by: Meng Yi
> ---
> Changes since V1:
> -no change
> ---
> drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_r
Hi Meng,
This currently does not apply on top of drm-next, can you please rebase?
Some more comments below:
On 2016-07-14 03:54, Meng Yi wrote:
> This patch rework the output code to add of_graph dt binding support
> for panel device and also keeps the backward compatibility
>
> Signed-off-by:
On 2016-06-29 01:17, Meng Yi wrote:
> add of_graph dt binding for panel, and "fsl,panel" property
Nit: "binding" typically describes the requirement, the specification
and hence is under Documentation/devicetree/bindings/.
What you add here is the dt nodes according to the bindings...
Hence I wo
On 2016-06-29 01:17, Meng Yi wrote:
> dropped the old "fsl,panel" property, using the of_graph dt
> binding syntax
>
> Signed-off-by: Meng Yi
> ---
> Changes in V2:
> -drop the unit address of port
> ---
> Documentation/devicetree/bindings/display/fsl,dcu.txt | 9 +++--
> 1 file changed, 7 i
On 2016-06-28 02:32, Meng Yi wrote:
> This patch rework the output code to add of_graph dt binding support
> for panel device and also keeps the backward compatibility
>
> Signed-off-by: Meng Yi
> ---
> Changes in V2:
> -fix some coding style issue
> -add fsl_dev->connector.panel check
> -use fsl
On 2016-07-04 00:40, Peter Chen wrote:
> of_node_put needs to be called when the device node which is got
> from of_parse_phandle has finished using, but current code only
> calls it at error path, fix it by adding it at correct code path.
>
> Signed-off-by: Peter Chen
> ---
> drivers/gpu/drm/fs
On 2016-06-28 19:58, Meng Yi wrote:
>> >> Optional properties:
>> >> - fsl,tcon: The phandle to the timing controller node.
>> >> @@ -24,6 +24,11 @@ dcu: dcu at 2ce {
>> >> clocks = <&platform_clk 0>, <&platform_clk 0>;
>> >> clock-names = "dcu", "pix";
>> >> big-endian;
>>
On 2016-06-28 14:07, Rob Herring wrote:
> On Tue, Jun 28, 2016 at 05:39:07PM +0800, Meng Yi wrote:
>> dropped the old "fsl,panel" property, using the of_graph dt
>> binding syntax
>>
>> Signed-off-by: Meng Yi
>> ---
>> Documentation/devicetree/bindings/display/fsl,dcu.txt | 9 +++--
>> 1 file
On 2016-06-24 02:00, Meng Yi wrote:
> The current output code only supports connection to drm panels.
> Add codes to support drm bridge, to supports connection to
I sense to many s here.
Code in the C program code sense is typically an uncountable noun, hence
drop the s.
And "to support connecti
Use "drm/fsl-dcu:" in the subject, that is what we commonly used.
On 2016-06-24 02:00, Meng Yi wrote:
> This patch rework the output code to add of_graph dt binding support
> for panel device and also keeps the backward compatibility
>
> Signed-off-by: Meng Yi
> ---
> drivers/gpu/drm/fsl-dcu/fs
:
drm/fsl-dcu: disable vblank events on CRTC disable (2016-06-18 18:34:31 -0700)
Stefan Agner (6):
drm/fb_cma_helper: add suspend helper
drm/fsl-dcu: store layer registers in soc_data
drm/fsl-dcu: move layer
ock polarity changes which will be part of 4.7 work for
Tower? I could never actually test that since I don't have the display
here...
https://patchwork.kernel.org/patch/8874971/
This patch looks good to me:
Acked-by: Stefan Agner
--
Stefan
>
> Signed-off-by: Anthony Felice
> ---
On 2016-06-24 12:44, Anthony Felice wrote:
> Add driver for the Vybrid Tower CRTouch-based touchscreen. This is
> required for the touchscreen on the TWR-LCD-RGB to work on the Vybrid
> Tower platform.
>
> There is a known issue with this driver: rarely, SW1 on the TWR-LCD-RGB
> module needs to be
On 2016-06-14 02:20, Meng Yi wrote:
> This patch creates another Encoder for HDMI port, and linking the Encoder
> to appropriate DRM bridge. And this Encoder using same CRTC with RGB-LCD.
> For RGB-LCD and HDMI using the same hardware connection to DCU, RGB-LCD
> panel should be unplugged when usin
Commit 7566e247672d ("drm/fsl-dcu: handle initialization errors properly")
introduced error handling during initialization, but with a wrong cleanup
order.
Replace the error handling with the generic cleanup function
drm_mode_config_cleanup.
Signed-off-by: Stefan Agner
---
drivers/g
On 2016-06-16 21:02, Meng Yi wrote:
> The lable fail_connector should placed before fail_encoder since encoder was
> initialized before connector. which should also be called after
> connector initialization failed.
>
> Hi Stefan,
>
> What do you think?
The current error handling is wrong, I agr
On 2016-06-11 18:55, Meng Yi wrote:
> Hi Stefan,
>
> Thanks for your comments, and some feedback below:
>
>> > +
>> > +#include
>> > +#include
>> > +#include
>> > +#include
>> > +#include
>> > +#include
>>
>> I think you don't use i2c here anymore, so this include (and probably a lot
>> oth
Hi Meng,
Some comments below.
On 2016-05-15 01:34, Meng Yi wrote:
> This driver add the basic functions for Encoder, and link the Encoder to
> appropriate DRM bridge.
> This driver is depend on sii9022 driver(drm_bridge approach),which is
> sent by Boris Brezillon to community but not merged.
> h
ce492b3b8f99cf9d2f807ec22d8805c996a09503:
drm/fsl-dcu: use flat regmap cache (2016-06-08 15:12:01 -0700)
Stefan Agner (1):
drm/fsl-dcu: use flat regmap cache
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
On 2016-06-06 19:16, Meng Yi wrote:
> Hi Stefan,
>
> Sorry for reply late, I was on PTO. And another PTO on June 9~11, 2016.UTC+8
>
>> >> static const struct regmap_config fsl_dcu_regmap_config = {
>> >> .reg_bits = 32,
>> >> .reg_stride = 4,
>> >> .val_bits = 32,
>> >> .cache_ty
since v1:
> - Invert polarity - driving pixel data on the falling edge and sampling
>it at the rising edge is the default.
> - Rename imx_drm_set_bus_format_pins to imx_drm_set_bus_config as now,
>additionally to bus format and pins, it also sets polarities.
Looks good
On 2016-06-03 16:00, Daniel Vetter wrote:
> On Fri, Jun 03, 2016 at 03:43:19PM -0700, Stefan Agner wrote:
>> Using flat regmap cache instead of RB-tree to avoid the following
>> lockdep warning on driver load:
>> WARNING: CPU: 0 PID: 1 at kernel/locking/lockdep.c:2755
>>
-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
index ca0f7d83..36df2eb 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
+++ b
Use the drm_atomic_helper_suspend() and drm_atomic_helper_resume()
helpers to implement subsystem-level suspend/resume. This replaces
the (non-functional) regmap cache based suspend resume functionality.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 40
Use clk_prepare_enable and clk_disable_unprepare helpers. This also
fixes a sequence issue in the enable path which lead to a warning
on resume.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 11 ++-
1 file changed, 2 insertions(+), 9 deletions(-)
diff
Move the initialization code for layers into a separate function
in the plane file. This allows to reuse the function on resume.
Also move it at the very beginning which may not matter but makes
logically much more sense.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu
Store the number of registers per layer in soc_data. This is
more consistent with how the rest of SoC specific data are
handled.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 8 ++--
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 2 ++
drivers/gpu/drm/fsl-dcu
Implement a suspend/resume helper for CMA users which calls
drm_fb_helper_set_suspend.
Suggested-by: Thierry Reding
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/drm_fb_cma_helper.c | 15 +++
include/drm/drm_fb_cma_helper.h | 1 +
2 files changed, 16 insertions(+)
diff
://lists.freedesktop.org/archives/dri-devel/2016-June/109625.html
Dave, Thierry: Could you have a look at patch 1? If that looks good
for you I will take it through my tree...
Changes since v1:
- Rebase ontop of drm-next + regmap cache fix
Stefan Agner (6):
drm/fb_cma_helper: add suspend helper
drm/fsl
On 2016-05-26 02:11, Alexander Stein wrote:
> On Thursday 26 May 2016 08:23:42, Meng Yi wrote:
>> Hi Mark,
>>
>> > You've not specifically described the problem here - what are the
>> > endiannesses of both the CPU and the device you're talking to? What
>> > specifically is the endianess problem y
to true.
Use flat regmap cache and specify max register to be large
enouth to cover all registers available in LS1021a and Vybrids
register space.
Signed-off-by: Stefan Agner
Cc: Mark Brown
Cc: stable at vger.kernel.org
---
While regmap cache is used for suspend/resume only (which is
broken in
ems to me that the current code does not what atomic is asking for,
checking that is on my 2do...
I tested this patch individually, using modesetting driver. Things seem
to work as they did before.
Acked-by: Stefan Agner
But I guess to test the non-blocking commit, I would have to apply the
On 2016-05-27 05:20, Mark Brown wrote:
> On Thu, May 26, 2016 at 10:54:16PM -0700, Stefan Agner wrote:
>> On 2016-05-26 02:11, Alexander Stein wrote:
>
>> > This needs to be a flat cache. See
>> > https://lists.freedesktop.org/archives/dri-devel/2016-January/099121
On 2016-05-26 02:11, Alexander Stein wrote:
> On Thursday 26 May 2016 08:23:42, Meng Yi wrote:
>> Hi Mark,
>>
>> > You've not specifically described the problem here - what are the
>> > endiannesses of both the CPU and the device you're talking to? What
>> > specifically is the endianess problem y
y 03, 2016 5:27 PM
> To: 'dri-devel at lists.freedesktop.org'
> ; David Airlie ;
> 'Stefan Agner' ; 'airlied at redhat.com'
>
> Subject: fsl-dcu not works on latest "drm-next"
>
> Hi,
>
>
> I just tested the latest drm-next branch
On 2016-05-10 08:07, Philipp Zabel wrote:
> This patch allows panels to set pixel clock and data enable pin polarity
> other than the default of driving data at the rising pixel clock edge and
> active high display enable.
>
> Signed-off-by: Philipp Zabel
> ---
> drivers/gpu/drm/imx/imx-drm-
)
Stefan Agner (2):
drm: introduce bus_flags in drm_display_info
drm/fsl-dcu: use bus_flags for pixel clock polarity
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 5 +
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h | 4 ++--
drivers
On 2016-05-05 03:06, Daniel Vetter wrote:
> On Wed, May 04, 2016 at 10:08:59PM -0700, Stefan Agner wrote:
>> Introduce bus_flags to specify display bus properties like signal
>> polarities. This is useful for parallel display buses, e.g. to
>> specify the pixel clock or
#x27;t direct get
> the panel, save polarity on panel_desc means need more work to
> transmit it to crtc.
>
> Thanks.
>
> On 2016å¹´05æ05æ¥ 13:08, Stefan Agner wrote:
>> Introduce bus_flags to specify display bus properties like signal
>> polarities. This is usefu
ned-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 5 +
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h | 4 ++--
drivers/gpu/drm/panel/panel-simple.c | 3 ++-
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
b/drive
-by: Stefan Agner
---
drivers/gpu/drm/panel/panel-simple.c | 2 ++
include/drm/drm_crtc.h | 9 +
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index ceb2048..77ae07f 100644
--- a/drivers/gpu/drm
ic changes to the first commit
Changes since v1:
- Introduce bus_flags to convey the pixel clock polarity from
panel-simple.c to the driver.
Stefan Agner (2):
drm: introduce bus_flags in drm_display_info
drm/fsl-dcu: use bus_flags for pixel clock polarity
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_
Hi Meng,
Please use plain text mails on mailing lists.
On 2016-05-03 02:26, Meng Yi wrote:
> Hi,
>
> I just tested the latest drm-next branch on Freescale/NXP ls1021a-twr, and
> got some log below. And fsl-dcu not works.
>
> Since "drm-next" merged some branch , use git bisect had some pr
; Signed-off-by: Arnd Bergmann
> Fixes: 2d701449bce1 ("drm/fsl-dcu: use common clock framework for
> pixel clock divider")
Oh right, thx!
Acked-by: Stefan Agner
@Dave, can you pick that up directly or do you prefer a pull request?
--
Stefan
> ---
> drivers/gpu/drm/fsl-dcu/
ssive stack usage
Stefan Agner (11):
drm/fsl-dcu: disable clock on initialization failure and remove
drm/fsl-dcu: add extra clock for pixel clock
drm/fsl-dcu: use common clock framework for pixel clock divider
drm/fsl-dcu: add TCON driver
drm/fsl-dcu: detach panel on de
Applied patchset to my fsl-dcu tree.
--
Stefan
On 2016-04-16 22:25, Stefan Agner wrote:
> Hi all,
>
> This patchset fixes several issues around unloading/unbinding
> the driver. There is still one WARNING when unloading the driver
> while vblank interrupts are enabled. I am no
On 2016-02-22 13:33, Arnd Bergmann wrote:
> The fsl-dcu driver copies a drm_mode_config object to its
> stack but then only accesses a single member (dpms_property)
> once. The data structure is large enough to trigger a warning
> about the amount of kernel stack being used:
>
> drivers/gpu/drm/fs
-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
index ca0f7d83..36df2eb 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
+++ b
Use the drm_atomic_helper_suspend() and drm_atomic_helper_resume()
helpers to implement subsystem-level suspend/resume. This replaces
the (non-functional) regmap cache based suspend resume functionality.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 39
Use clk_prepare_enable and clk_disable_unprepare helpers. This also
fixes a sequence issue in the enable path which lead to a warning
on resume.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 11 ++-
1 file changed, 2 insertions(+), 9 deletions(-)
diff
Move the initialization code for layers into a separate function
in the plane file. This allows to reuse the function on resume.
Also move it at the very beginning which may not matter but makes
logically much more sense.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu
Store the number of registers per layer in soc_data. This is
more consistent with how the rest of SoC specific data are
handled.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 8 ++--
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 2 ++
drivers/gpu/drm/fsl-dcu
Implement a suspend/resume helper for CMA users which calls
drm_fb_helper_set_suspend.
Suggested-by: Thierry Reding
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/drm_fb_cma_helper.c | 15 +++
include/drm/drm_fb_cma_helper.h | 1 +
2 files changed, 16 insertions(+)
diff
obsoletes this patch:
https://lkml.org/lkml/2016/3/24/281
Stefan Agner (6):
drm/fb_cma_helper: add suspend helper
drm/fsl-dcu: store layer registers in soc_data
drm/fsl-dcu: move layer initialization to plane file
drm/fsl-dcu: use clk helpers
drm/fsl-dcu: implement suspend/resume using
ned-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 5 +
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h | 4 ++--
drivers/gpu/drm/panel/panel-simple.c | 3 ++-
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
b/drive
Introduce bus_flags to specify display bus properties like signal
polarities. This is useful for parallel display buses, e.g. to
specify the pixel clock or data enable polarity.
Suggested-by: Thierry Reding
Acked-by: Philipp Zabel
Acked-by: Manfred Schlaegl
Signed-off-by: Stefan Agner
s_flags to convey the pixel clock polarity from
panel-simple.c to the driver.
Stefan Agner (2):
drm: introduce bus_flags in drm_display_info
drm/fsl-dcu: use bus_flags for pixel clock polarity
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 5 +
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_
Use CMA helper drm_fbdev_cma_restore_mode to restore fbdev mode
in process which uses drm/kms dies.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
b/drivers/gpu/drm
Disabling output polling before unloading the driver.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index 182578d..f9227b7
Free fbdev CMA using drm_fbdev_cma_fini on unload. This fixes
a warning when unloading the driver:
WARNING: CPU: 0 PID: 164 at drivers/gpu/drm/drm_crtc.c:5930
drm_mode_config_cleanup+0x204/0x208
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 9 +
1 file
The driver uses different variable names for struct drm_device
across functions which is confusing. Stick to the more common
variable name dev. While at it, remove unnecessary if statement
in error handling.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 29
If the device tree property fsl,panel is missing, drm_panel_attach
is called with a NULL pointer as first argument. Having a panel is
basically mandatory since RGB is the only supported connector.
Check if a panel node has been found, return -ENODEV and cleanup
otherwise.
Signed-off-by: Stefan
Disable the earlier attached panel on connector destroy.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
index f586f1e..a07886f
nts welcome...
Stefan Agner (6):
drm/fsl-dcu: detach panel on destroy
drm/fsl-dcu: handle missing panel gracefully
drm/fsl-dcu: use variable name dev for struct drm_device
drm/fsl-dcu: deallocate fbdev CMA on unload
drm/fsl-dcu: disable output polling on driver unload
drm/fsl-dcu: implem
On 2016-04-11 18:38, Shawn Guo wrote:
> On Mon, Apr 04, 2016 at 10:28:33PM -0700, Stefan Agner wrote:
>> Similar to an earlier fix for the SAI clocks, the DCU clock hierarchy
>> mixes the bus clock with the display controllers pixel clock. Tests
>> have shown that the
The DCU IP has distinct clock inputs for register access and the
pixel clocks, at least in some implementations. LS1021a seems to
use the same clock, therefore specify the same clock for "dcu"
and "pix".
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/ls1021a.dtsi | 5 +++-
Enable dcu node which is used by the DCU DRM driver. Assign the 5.7"
EDT panel with VGA resolution which Toradex sells often with the
evaluation board.
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/vf-colibri-eval-v3.dtsi | 16 +++
arch/arm/boot/dts/vf-colibri.dtsi
Add the dcu and tcon nodes to enable the Display Controller Unit
and Timing Controller in Vybrid's SoC level device-tree file.
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/vfxxx.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/vfxxx.d
iming signals for raw TFT panels
or operate in a bypass mode which leaves all signals unaltered.
The driver currently only supports the bypass mode.
Acked-by: Rob Herring
Signed-off-by: Stefan Agner
---
.../devicetree/bindings/display/fsl,dcu.txt| 4 +
.../devicetree/bindings/displa
it also allows to see
the actual pixel clock in the sysfs clock summary.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 7 ++-
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 26 ++
2 files changed, 24 insertions(+), 9 deletions(-)
diff
The Vybrid DCU variant has two independent clock inputs, one
for the registers (IPG bus clock) and one for the pixel clock.
Support this distinction in the DCU DRM driver while staying
backward compatible for old device trees.
Signed-off-by: Stefan Agner
---
Documentation/devicetree/bindings
Fix error handling during probe by reordering initialization and
adding a error path which disables clock again. Also disable the
clock on remove.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 44 +++
1 file changed, 21 insertions(+), 23
Add the ipg (bus) clock for the TCON modules (Timing Controller). This
module is required by the new DCU DRM driver, since the display signals
pass through TCON.
Signed-off-by: Stefan Agner
---
drivers/clk/imx/clk-vf610.c | 3 +++
include/dt-bindings/clock/vf610-clock.h | 4 +++-
2
parent clock of VF610_CLK_DCUx to be the bus
clock (ipg_bus).
Since the clock has not been used far, there are no further changes
needed.
Signed-off-by: Stefan Agner
---
drivers/clk/imx/clk-vf610.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/imx/clk-vf610
Simplified TCON driver by removing suspend/resume
capabilities (encoder disable/enable makes sure that
TCON bypass gets disabled/reenabled on suspend)
- Use common clock framework to create a divider clock
which represents the DCU internal pixel clock divider
Stefan Agner (9):
ARM: imx: clk-
On 2016-03-29 00:26, Alexander Stein wrote:
> On Tuesday 29 March 2016 00:11:13, Stefan Agner wrote:
>> >> --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
>> >> +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
>> >>
>
On 2016-03-28 23:45, Alexander Stein wrote:
> Hi,
>
> some comments below.
>
> On Monday 28 March 2016 19:00:00, Stefan Agner wrote:
>> Add driver for the TCON (timing controller) module. The TCON module
>> is a separate module attached after the DCU (display co
Enable dcu node which is used by the DCU DRM driver. Assign the 5.7"
EDT panel with VGA resolution which Toradex sells often with the
evaluation board.
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/vf-colibri-eval-v3.dtsi | 16 +++
arch/arm/boot/dts/vf-colibri.dtsi
Add the dcu and tcon nodes to enable the Display Controller Unit
and Timing Controller in Vybrid's SoC level device-tree file.
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/vfxxx.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/vfxxx.d
iming signals for raw TFT panels
or operate in a bypass mode which leaves all signals unaltered.
The driver currently only supports the bypass mode.
Signed-off-by: Stefan Agner
---
.../devicetree/bindings/display/fsl,dcu.txt| 2 +
.../devicetree/bindings/display/fsl,tcon.txt
it also allows to see
the actual pixel clock in the sysfs clock summary.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 7 ++-
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 26 ++
2 files changed, 24 insertions(+), 9 deletions(-)
diff
The Vybrid DCU variant has two independent clock inputs, one
for the registers (IPG bus clock) and one for the pixel clock.
Support this distinction in the DCU DRM driver while staying
backward compatible with devices providing only a single clock
(e.g. LS1021a SoC's).
Signed-off-by: Stefan
Fix error handling during probe by reordering initialization and
adding a error path which disables clock again. Also disable the
clock on remove.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 44 +++
1 file changed, 21 insertions(+), 23
Add the ipg (bus) clock for the TCON modules (Timing Controller). This
module is required by the new DCU DRM driver, since the display signals
pass through TCON.
Signed-off-by: Stefan Agner
---
drivers/clk/imx/clk-vf610.c | 3 +++
include/dt-bindings/clock/vf610-clock.h | 4 +++-
2
parent clock of VF610_CLK_DCUx to be the bus
clock (ipg_bus).
Since the clock has not been used far, there are no further changes
needed.
Signed-off-by: Stefan Agner
---
drivers/clk/imx/clk-vf610.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/imx/clk-vf610
driver by removing suspend/resume
capabilities (encoder disable/enable makes sure that
TCON bypass gets disabled/reenabled on suspend)
- Use common clock framework to create a divider clock
which represents the DCU internal pixel clock divider
Stefan Agner (8):
ARM: imx: clk-vf610: fix DCU
Hi Alexander,
On 2016-03-24 06:33, Alexander Stein wrote:
> Using REGCACHE_RBTREE for MMIO regmap is not valid as spinlock's will be
> used during cache allocation.
>
> This fixes the following bug:
> BUG: sleeping function called from invalid context at mm/slab.h:388
> in_atomic(): 1, irqs_disab
u to fetch changes up to f76b9873d7db0afb51f2df389a99284ef484b86f:
drm/fsl-dcu: fix register initialization (2016-02-25 16:13:16 -0800)
Meng Yi (1):
drm: fsl-dcu: Fix no fb check bug
Stefan Agner (9):
MAINTAINERS:
On 2016-02-02 17:06, Stefan Agner wrote:
> The layer enumeration start with 0 (0-15 for LS1021a and 0-63 for
> Vybrid) whereas the register enumeration start from 1 (1-10 for
> LS1021a and 1-9 for Vybrid). The loop started off from 0 for both
> iterations and initialized the numb
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