r with the documentation, change the 'dsibclk'
variable to 'hsbyteclk'. This also make it easier to visually separate
'dsibclk' and 'dsiclk' variables.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/bridge/tc358768.c | 48 +++
Simplify the code by capturing the priv->dev value to dev variable, and
use it.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/bridge/tc358768.c | 41 ---
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358768.c
ingly, as it simplifies the PLL code.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/bridge/tc358768.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358768.c
b/drivers/gpu/drm/bridge/tc358768.c
index b668f77673c3..d5831a1236e9 1
: ff1ca6397b1d ("drm/bridge: Add tc358768 driver")
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/bridge/tc358768.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358768.c
b/drivers/gpu/drm/bridge/tc358768.c
index bc97a837955b..b6
smatch reports:
drivers/gpu/drm/bridge/tc358768.c:223 tc358768_update_bits() error:
uninitialized symbol 'orig'.
Fix this by bailing out from tc358768_update_bits() if the
tc358768_read() produces an error.
Fixes: ff1ca6397b1d ("drm/bridge: Add tc358768 driver")
Signed-of
s DSI HSW, HFP and VSDly calculations
- Adds DRM_BRIDGE_ATTACH_NO_CONNECTOR support
Tomi
Signed-off-by: Tomi Valkeinen
---
Tomi Valkeinen (11):
drm/bridge: tc358768: Fix use of uninitialized variable
drm/bridge: tc358768: Fix bit updates
drm/bridge: tc358768: Cleanup PL
truct drm_minor;
struct drm_panel;
struct edid;
struct i2c_adapter;
@@ -949,4 +950,6 @@ static inline struct drm_bridge *drmm_of_get_bridge(struct
drm_device *drm,
}
#endif
+void drm_bridge_debugfs_init(struct drm_minor *minor);
+
#endif
---
base-commit: a0c64d153d687756c8719b8d10e609d62e1cb6fd
change-id: 20230721-drm-bridge-chain-debugfs-0bbc1522f57a
Best regards,
--
Tomi Valkeinen
, ops: 0x0, OF:
/bus@f/i2c@2000/dsi@e:toshiba,tc358778
bridge[2] type: 0, ops: 0x3, OF:
/bus@f/i2c@2001/hdmi@48:lontium,lt8912b
bridge[3] type: 11, ops: 0x7, OF: /hdmi-connector:hdmi-connector
Signed-off-by: Tomi Valkeinen
---
Changes in v3:
On 25/07/2023 14:37, Laurent Pinchart wrote:
Hi Tomi,
Thank you for the patch.
On Fri, Jul 21, 2023 at 06:01:39PM +0300, Tomi Valkeinen wrote:
DRM bridges are not visible to the userspace and it may not be
immediately clear if the chain is somehow constructed incorrectly. I
have had two
, ops: 0x0, OF:
/bus@f/i2c@2000/dsi@e:toshiba,tc358778
bridge[2] type: 0, ops: 0x3, OF:
/bus@f/i2c@2001/hdmi@48:lontium,lt8912b
bridge[3] type: 11, ops: 0x7, OF: /hdmi-connector:hdmi-connector
Signed-off-by: Tomi Valkeinen
---
Changes in v2:
- Fixed compilation
, ops: 0x0, OF:
/bus@f/i2c@2000/dsi@e:toshiba,tc358778
bridge[2] type: 0, ops: 0x3, OF:
/bus@f/i2c@2001/hdmi@48:lontium,lt8912b
bridge[3] type: 11, ops: 0x7, OF: /hdmi-connector:hdmi-connector
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/drm_bridge.c
On 16/06/2023 18:08, Aradhya Bhatia wrote:
This patch series adds a new compatible for the Display SubSystem (DSS)
controller on TI's AM625 SoC. It further adds the required support for
the same in the tidss driver.
The AM625-DSS is a newer version of the DSS from the AM65X version with
the majo
Add drm-misc as the git tree for tilcdc and omapdrm. Change Tomi's email
to point to ideasonboard.com instead of kernel.org.
Signed-off-by: Tomi Valkeinen
---
MAINTAINERS | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index aa0aa6c
to reduce the required OLDI clock
output.
The second video port is same from AM65x DSS and it outputs DPI video
data. It can support 2K resolutions @ 60fps, independently.
Add the new controller's compatible and update descriptions.
Signed-off-by: Aradhya Bhatia
Reviewed-by: Tomi Valkeinen
Tomi
nd 1 of clock output.
I think it should be explained that OLDI is not supported in this
version, but will be added later.
Other than that:
Reviewed-by: Tomi Valkeinen
Tomi
On 08/06/2023 19:26, Laurent Pinchart wrote:
Hi Doug,
On Thu, Jun 08, 2023 at 09:08:15AM -0700, Doug Anderson wrote:
On Thu, Jun 1, 2023 at 8:40 AM Uwe Kleine-König wrote:
On Sun, May 07, 2023 at 06:25:23PM +0200, Uwe Kleine-König wrote:
this patch series adapts the platform drivers below dri
tidss.
Would it be possible for you to pick all the patches together once Tomi
acks the tidss patch?
Sure
I think this looks fine. For the series:
Reviewed-by: Tomi Valkeinen
Tomi
DMA_BIT));
+ ret = dma_set_mask(dpsub->dev, DMA_BIT_MASK(ZYNQMP_DISP_MAX_DMA_BIT));
+ if (ret)
+ return ret;
This seems reasonable.
Reviewed-by: Laurent Pinchart
Tomi, would you be able to quickly test this ?
Works for me.
Reviewed-by: Tomi Valkeinen
Tomi
on,
we can eventually remove DRM's wrapper functions entirely.
v4:
* use initializer macros for struct fb_ops
v2:
* use FB_SYS_HELPERS option
Signed-off-by: Thomas Zimmermann
Acked-by: Sam Ravnborg
Cc: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/Kconfig | 1 +
On 29/05/2023 08:37, Aradhya Bhatia wrote:
Btw, we seem to be missing get-output-fmt from the mdhp driver.
Yes, we are.
With the drm_bridge_attach call added, the display-connector bridge will
assign MEDIA_BUS_FMT_FIXED as the default output format. And most
bridges support only their primary o
On 16/05/2023 17:25, Aradhya Bhatia wrote:
Hi Neil,
Thank you for reviewing the patch.
On 16-May-23 12:51, Neil Armstrong wrote:
On 15/05/2023 17:59, Aradhya Bhatia wrote:
Hi Tomi,
On 12-May-23 14:45, Tomi Valkeinen wrote:
On 09/05/2023 12:30, Aradhya Bhatia wrote:
From: Nikhil Devshatwar
On 09/05/2023 12:30, Aradhya Bhatia wrote:
Hi all,
I have picked up this long standing series from Nikhil Devshatwar[1].
This series moves the tidss to using new connectoe model, where the SoC
driver (tidss) creates the connector and all the bridges are attached
with the flag DRM_BRIDGE_ATTACH_
negotiation can be added based on EDID data.
This patch adds the minimal required support to avoid failure
after moving to new connector model.
Signed-off-by: Nikhil Devshatwar
Reviewed-by: Tomi Valkeinen
You need to add your SoB to this and the other patches.
---
Notes:
changes from
riant.
Signed-off-by: Uwe Kleine-König
---
drivers/gpu/drm/tidss/tidss_drv.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
Reviewed-by: Tomi Valkeinen
Tomi
diff --git a/drivers/gpu/drm/tidss/tidss_drv.c
b/drivers/gpu/drm/tidss/tidss_drv.c
index 2dac8727d2f4..13177d58c8f9 1
On 14/04/2023 18:10, Jayesh Choudhary wrote:
On 06/04/23 07:22, Laurent Pinchart wrote:
Hi Jayesh,
Thank you for the patch.
On Wed, Apr 05, 2023 at 07:54:40PM +0530, Jayesh Choudhary wrote:
From: Rahul T R
In J721S2 EVMs DP0 hpd is not connected to correct
hpd pin on SOC, to handle such c
On 05/04/2023 17:24, Jayesh Choudhary wrote:
In J721s2 EVM, DP0 HPD is not connected to correct HPD pin on SOC
which results in HPD detect as always connnected, so when display
is not connected driver continuously retries to read EDID and DPCD
registers.
Where is the DP0 HPD connected to? Nowhe
On 12/04/2023 11:50, Laurent Pinchart wrote:
Hi Tony,
Thank you for the patch.
On Wed, Apr 12, 2023 at 10:39:53AM +0300, Tony Lindgren wrote:
We may not have dsi->dsidev initialized during probe, and that can
lead into various dsi related warnings as omap_dsi_host_detach() gets
called with dsi
Hi Thomas,
On 03/04/2023 13:40, Thomas Zimmermann wrote:
Convert omapdrm's fbdev code to struct drm_client. Replaces the current
ad-hoc integration. The conversion includes a number of cleanups. As
with most other drivers' fbdev emulation, fbdev in omapdrm is now just
another DRM client that run
Hi Thomas,
On 03/04/2023 11:24, Thomas Zimmermann wrote:
That's my only real comment. Kernel test bot had one comment too. But
other than that:
Reviewed-by: Tomi Valkeinen
I tested this series on TI DRA76 EVM, and worked fine for me.
That you so much.
I'm going to send out
t(dev->fb_helper);
+
+ ret = drm_fb_helper_init(dev, fb_helper);
+ if (ret)
+ goto err_drm_err;
+
+ if (!drm_drv_uses_atomic_modeset(dev))
Why do we need this? omapdrm supports atomic.
That's my only real comment. Kernel test bot had one comment too. But
othe
this could be as well merged to the next patch, as this is such
a short one.
Reviewed-by: Tomi Valkeinen
Tomi
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/omapdrm/omap_fbdev.c | 33 +++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/driver
Is this line needed anymore? As you dropped the priv->fbdev assignment
in omap_fbdev_init(), it would look symmetrical to also drop this one.
I'm sure it doesn't hurt, just wondering if this is something drivers
are supposed to do, or is this just an extra line in the driver.
In either case:
Reviewed-by: Tomi Valkeinen
Tomi
On 30/03/2023 11:32, Thomas Zimmermann wrote:
Fbdev's framebuffer stores a pointer to the GEM object. Remove
struct omap_fbdev.exynos_gem, which contains the same value. No
Copy paste error? =)
Reviewed-by: Tomi Valkeinen
Tomi
functional changes.
Signed-off-by: Thomas Zimme
t;fb);
+ if (fb)
+ drm_framebuffer_remove(fb);
drm_fb_helper_unprepare(helper);
kfree(fbdev);
Reviewed-by: Tomi Valkeinen
Tomi
/omapdrm/omap_drv.c
index 699ed814e021..fb403b44769c 100644
--- a/drivers/gpu/drm/omapdrm/omap_drv.c
+++ b/drivers/gpu/drm/omapdrm/omap_drv.c
@@ -6,6 +6,7 @@
#include
#include
+#include
#include
#include
Reviewed-by: Tomi Valkeinen
Tomi
m-misc-fixes ASAP.
If it's not too late:
Reviewed-by: Tomi Valkeinen
Tomi
On 27/02/2023 14:06, Akira Yokosawa wrote:
Hi Mauro,
On Sun, 26 Feb 2023 11:47:44 +0100, Mauro Carvalho Chehab wrote:
Em Sun, 26 Feb 2023 08:39:32 +0900
Akira Yokosawa escreveu:
[+CC: Jon, linux-doc]
On Wed, 8 Feb 2023 10:29:16 +0200, Tomi Valkeinen wrote:
Commit 8d0e3fc61abd ("
be written to 0 temporarily
before starting the hardware, make sure that the registers are always
set to valid values.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/rcar_du_group.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
Reviewed-by: Tomi Valkeinen
Tomi
thought I already did this... And I see I did, but never sent the
patch as I couldn't figure the part 2 =).
Reviewed-by: Tomi Valkeinen
Tomi
Hi,
On 22/02/2023 17:28, Nicolas Dufresne wrote:
Hi Tomi,
Le mercredi 21 décembre 2022 à 11:24 +0200, Tomi Valkeinen a écrit :
Add Y210, Y212 and Y216 formats.
Signed-off-by: Tomi Valkeinen
---
.../media/v4l/pixfmt-packed-yuv.rst | 49 ++-
drivers/media/v4l2
;routes[RCAR_DU_OUTPUT_DPAD1].possible_crtcs) &
+ BIT(rcrtc->index))
rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02,
0);
- }
/* Signal polarities */
dsmr = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)
Reviewed-by: Tomi Valkeinen
Tomi
.format = rcar_du_format_info(DRM_FORMAT_XRGB),
.source = RCAR_DU_PLANE_VSPD1,
.colorkey = 0,
};
Reviewed-by: Tomi Valkeinen
Tomi
enable = tidss_plane_atomic_enable,
.atomic_disable = tidss_plane_atomic_disable,
};
I haven't tested this, but looks fine to me.
Reviewed-by: Tomi Valkeinen
One thought, though, is that we still do dispc_plane_enable(false) in
tidss_plane_atomic_update() when the plane is not visible.
/gpu/drm/tidss/tidss_plane.c | 11 +--
3 files changed, 9 insertions(+), 22 deletions(-)
Reviewed-by: Tomi Valkeinen
Tomi
a minor comment below, other than that:
Reviewed-by: Tomi Valkeinen
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 18 ++--
drivers/gpu/drm/rcar-du/rcar_lvds.c| 114 +++--
drivers/gpu/drm/rcar-du/rcar_lvds.h| 12 ++-
3 files
code,
but the diff shows you moving the lvds pclk enable/disable code. Other
than that:
Reviewed-by: Tomi Valkeinen
Tomi
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/rcar_lvds.c | 97 +++--
1 file changed, 50 insertions(+), 47 deletions(-)
diff --git
gt;atomic_disable(lvds->companion,
- old_bridge_state);
+ rcar_lvds_atomic_disable(lvds->companion, old_bridge_state);
pm_runtime_put_sync(lvds->dev);
}
Reviewed-by: Tomi Valkeinen
Tomi
23 13:17, Mauro Carvalho Chehab wrote:
Em Wed, 8 Feb 2023 11:11:34 +0200
Laurent Pinchart escreveu:
Hi Tomi,
Thank you for the patch.
On Wed, Feb 08, 2023 at 10:29:16AM +0200, Tomi Valkeinen wrote:
Commit 8d0e3fc61abd ("media: Add 2-10-10-10 RGB formats") added
documatation for a few
ue.
Fixes: 8d0e3fc61abd ("media: Add 2-10-10-10 RGB formats")
Reported-by: Akira Yokosawa
Signed-off-by: Tomi Valkeinen
---
Note: the offending patch was merged via drm tree, so we may want to
apply the fix to the drm tree also.
Documentation/userspace-api/media/v4l/pixfmt-rgb.rst | 3 --
and BGRA1010102 formats.
Signed-off-by: Tomi Valkeinen
---
.../userspace-api/media/v4l/pixfmt-rgb.rst| 194 ++
drivers/media/v4l2-core/v4l2-ioctl.c | 3 +
include/uapi/linux/videodev2.h| 3 +
3 files changed, 200 insertions(+)
diff --git a/Document
On 06/02/2023 19:34, Aradhya Bhatia wrote:
On 06-Feb-23 18:35, Tomi Valkeinen wrote:
On 05/02/2023 15:08, Aradhya Bhatia wrote:
Hi Tomi,
Thanks for the review!
On 03-Feb-23 16:53, Tomi Valkeinen wrote:
On 25/01/2023 13:35, Aradhya Bhatia wrote:
Make DSS Video Ports agnostic of output bus
On 05/02/2023 15:42, Aradhya Bhatia wrote:
Hi Tomi,
On 03-Feb-23 20:42, Tomi Valkeinen wrote:
On 25/01/2023 13:35, Aradhya Bhatia wrote:
The newer version of DSS (AM625-DSS) has 2 OLDI TXes at its disposal.
These can be configured to support the following modes:
1
On 05/02/2023 15:08, Aradhya Bhatia wrote:
Hi Tomi,
Thanks for the review!
On 03-Feb-23 16:53, Tomi Valkeinen wrote:
On 25/01/2023 13:35, Aradhya Bhatia wrote:
Make DSS Video Ports agnostic of output bus types.
DSS controllers have had a 1-to-1 coupling between its VPs and its
output ports
On 05/02/2023 16:31, Aradhya Bhatia wrote:
On 03-Feb-23 21:03, Tomi Valkeinen wrote:
On 25/01/2023 13:35, Aradhya Bhatia wrote:
Add support for the DSS controller on TI's new AM625 SoC in the tidss
driver.
The first video port (VP0) in am625-dss can output OLDI signals through
2 OLDI
On 25/01/2023 13:35, Aradhya Bhatia wrote:
Add support for the DSS controller on TI's new AM625 SoC in the tidss
driver.
The first video port (VP0) in am625-dss can output OLDI signals through
2 OLDI TXes. A 3rd output port has been added with "DISPC_PORT_OLDI" bus
type.
Not a big thing here a
bits */
+#define AM625_OLDI0_PWRDN_TX BIT(0)
+#define AM625_OLDI1_PWRDN_TX BIT(1)
+
+/* LVDS Bandgap reference Enable/Disable */
+#define AM625_OLDI_PWRDN_BG BIT(8)
#endif /* __TIDSS_DISPC_REGS_H */
Reviewed-by: Tomi Valkeinen
Tomi
On 25/01/2023 13:35, Aradhya Bhatia wrote:
The newer version of DSS (AM625-DSS) has 2 OLDI TXes at its disposal.
These can be configured to support the following modes:
1. OLDI_SINGLE_LINK_SINGLE_MODE
Single Output over OLDI 0.
+--++-+ +---+
| ||
On 25/01/2023 13:35, Aradhya Bhatia wrote:
Make DSS Video Ports agnostic of output bus types.
DSS controllers have had a 1-to-1 coupling between its VPs and its
output ports. This no longer stands true for the new AM625 DSS. This
coupling, hence, has been removed by renaming the 'vp_bus_type' to
Reset LVDS using the reset control as CPG reset/release is required in
the hardware manual sequence.
Based on a BSP patch from Koji Matsuoka .
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/Kconfig | 1 +
drivers/gpu/drm/rcar-du/rcar_lvds.c | 20
The following registers do not exist on gen4, so we should not write
them: DEF6Rm, DEF7Rm, DEF8Rm, ESCRn, OTARn.
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 8 +---
drivers/gpu/drm/rcar-du/rcar_du_group.c | 24
Add simple runtime PM suspend and resume functionality.
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/Kconfig | 1 +
drivers/gpu/drm/rcar-du/rcar_lvds.c | 43 +
2 files changed, 38 insertions(+), 6 deletions(-)
diff
entry for the ES1, and a quirk flag,
RCAR_DU_QUIRK_H3_ES1_PCLK_STABILITY, for the workaround.
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 8 +
drivers/gpu/drm/rcar-du/rcar_du_drv.c | 48 ++
drivers/gpu/drm
From: Tomi Valkeinen
Hi,
Diff to v2:
- Depend on PM in Kconfig to ensure runtime PM works
- Fix access to DEFR7 in "drm: rcar-du: Stop accessing non-existant
registers on gen4"
- Use pm_runtime_put_sync() instead of pm_runtime_put()
- Add missing line feed
- Fix lvsd typo in comm
S1.x.
Add a new quirk, RCAR_DU_QUIRK_H3_ES1_PLL, for this. This way we can
always set the bit 21 on PLSC0 when choosing the PLL as the source
clock, and additionally set the bit 20 when on ES1.x.
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/rcar_du_c
From: Koji Matsuoka
According to hardware manual, LVDCR0 register must be cleared bit by bit
when disabling LVDS.
Signed-off-by: Koji Matsuoka
Signed-off-by: LUU HOAI
[tomi.valkeinen: simplified the code a bit]
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm
The RCAR DSI driver uses reset controller, so we should select it in the
Kconfig.
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du
On 20/01/2023 18:16, Laurent Pinchart wrote:
Hi Tomi,
Thank you for the patch.
On Fri, Jan 20, 2023 at 10:50:04AM +0200, Tomi Valkeinen wrote:
Add simple runtime PM suspend and resume functionality.
I think you need to depend on PM in Kconfig. That's not a compile-time
dependency
On 20/01/2023 19:05, Laurent Pinchart wrote:
On Fri, Jan 20, 2023 at 06:18:07PM +0200, Laurent Pinchart wrote:
Hi Tomi,
Thank you for the patch.
Another small comment: in the commit message, s/lvsd/lvds/
Yep.
On Fri, Jan 20, 2023 at 10:50:05AM +0200, Tomi Valkeinen wrote:
Reset LVDS
The following registers do not exist on gen4, so we should not write
them: DEF6Rm, DEF7Rm, DEF8Rm, ESCRn, OTARn.
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 8 +---
drivers/gpu/drm/rcar-du/rcar_du_group.c | 11 ---
2
On 20/01/2023 18:21, Laurent Pinchart wrote:
On Fri, Jan 20, 2023 at 10:50:09AM +0200, Tomi Valkeinen wrote:
The following registers do not exist on gen4, so we should not write
them: DEF6Rm, DEF7Rm, DEF8Rm, ESCRn, OTARn.
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
Add simple runtime PM suspend and resume functionality.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/rcar-du/rcar_lvds.c | 43 +
1 file changed, 37 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c
b/drivers/gpu/drm/rcar-du
S1.x.
Add a new quirk, RCAR_DU_QUIRK_H3_ES1_PLL, for this. This way we can
always set the bit 21 on PLSC0 when choosing the PLL as the source
clock, and additionally set the bit 20 when on ES1.x.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 23 --
Reset LVDS using the reset control as CPG reset/release is required in
the hardware manual sequence.
Based on a BSP patch from Koji Matsuoka .
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/rcar-du/Kconfig | 1 +
drivers/gpu/drm/rcar-du/rcar_lvds.c | 19 ++-
2 files
The RCAR DSI driver uses reset controller, so we should select it in the
Kconfig.
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du
From: Koji Matsuoka
According to hardware manual, LVDCR0 register must be cleared bit by bit
when disabling LVDS.
Signed-off-by: Koji Matsuoka
Signed-off-by: LUU HOAI
[tomi.valkeinen: simplified the code a bit]
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/rcar-du/rcar_lvds.c | 26
From: Tomi Valkeinen
Hi,
v2 of the series. Diff to v1 can be found below.
The main changes are:
- Runtime PM support for LVDS
- Skip rcar_du_group_setup() for gen4+
Tomi
Koji Matsuoka (1):
drm: rcar-du: lvds: Fix stop sequence
Tomi Valkeinen (6):
drm: rcar-du: dsi: add 's
entry for the ES1, and a quirk flag,
RCAR_DU_QUIRK_H3_ES1_PCLK_STABILITY, for the workaround.
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 8 +
drivers/gpu/drm/rcar-du/rcar_du_drv.c | 48 ++
drivers/gpu/drm
On 17/01/2023 18:04, Geert Uytterhoeven wrote:
Hi Tomi,
On Tue, Jan 17, 2023 at 2:54 PM Tomi Valkeinen
wrote:
From: Koji Matsuoka
Reset LVDS using the reset control as CPG reset/release is required in
H/W manual sequence.
Signed-off-by: Koji Matsuoka
Signed-off-by: LUU HOAI
On 18/01/2023 23:12, Laurent Pinchart wrote:
Hi Tomi,
Thank you for the patch.
On Tue, Jan 17, 2023 at 03:51:51PM +0200, Tomi Valkeinen wrote:
From: Koji Matsuoka
According to H/W manual, LVDCR0 register must be cleared bit by bit when
s@H/W@the hardware/
disabling LVDS.
I don't
On 18/01/2023 23:19, Laurent Pinchart wrote:
Hi Tomi,
Thank you for the patch.
On Tue, Jan 17, 2023 at 03:51:52PM +0200, Tomi Valkeinen wrote:
rcar_du_crtc.c does a soc_device_match() in
rcar_du_crtc_set_display_timing() to find out if the SoC is H3 ES1, and
s/ES1/ES1.x/
Same below.
if
On 18/01/2023 23:06, Laurent Pinchart wrote:
Hi Tomi,
Thank you for the patch.
On Tue, Jan 17, 2023 at 03:51:50PM +0200, Tomi Valkeinen wrote:
From: Koji Matsuoka
Reset LVDS using the reset control as CPG reset/release is required in
H/W manual sequence.
s@H/W@the hardware@
Signed-off
On 18/01/2023 23:54, Laurent Pinchart wrote:
Hi Tomi,
Thank you for the patch.
On Tue, Jan 17, 2023 at 03:51:54PM +0200, Tomi Valkeinen wrote:
The following registers do not exist on gen4, so we should not write
them: DEF6Rm, DEF8Rm, ESCRn, OTARn.
I think DEF7Rm should also be skipped. With
On 18/01/2023 23:38, Laurent Pinchart wrote:
Hi Tomi,
Thank you for the patch.
On Tue, Jan 17, 2023 at 03:51:53PM +0200, Tomi Valkeinen wrote:
On H3 ES1 two bits in DPLLCR are used to select the DU input dot clock
s/ES1/ES1.x/
Same below.
Ok. But I do wonder, is there a difference
On 19/01/2023 11:40, Laurent Pinchart wrote:
Hi Tomi,
On Thu, Jan 19, 2023 at 11:17:58AM +0200, Tomi Valkeinen wrote:
On 18/01/2023 23:38, Laurent Pinchart wrote:
On Tue, Jan 17, 2023 at 03:51:53PM +0200, Tomi Valkeinen wrote:
On H3 ES1 two bits in DPLLCR are used to select the DU input dot
On 17/01/2023 18:11, Geert Uytterhoeven wrote:
Hi Tomi,
On Tue, Jan 17, 2023 at 2:54 PM Tomi Valkeinen
wrote:
rcar_du_crtc.c does a soc_device_match() in
rcar_du_crtc_set_display_timing() to find out if the SoC is H3 ES1, and
if so, apply a WA.
We will need another H3 ES1 check in the
e ES1, and a quirk flag,
RCAR_DU_QUIRK_H3_ES1_PCLK_STABILITY, for the WA.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 8 +---
drivers/gpu/drm/rcar-du/rcar_du_drv.c | 51 +-
drivers/gpu/drm/rcar-du/rcar_du_drv.h | 1 +
3 files change
S1.
Add a new quirk, RCAR_DU_QUIRK_H3_ES1_PLL, for this, and a new
rcar_du_device_info entry for the ES1 SoC. Using these, we can always
set the bit 21 on PLSC0 when choosing the PLL as the source clock, and
additionally set the bit 20 when on ES1.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/d
The following registers do not exist on gen4, so we should not write
them: DEF6Rm, DEF8Rm, ESCRn, OTARn.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 8 +---
drivers/gpu/drm/rcar-du/rcar_du_group.c | 6 --
2 files changed, 9 insertions(+), 5 deletions
From: Koji Matsuoka
Reset LVDS using the reset control as CPG reset/release is required in
H/W manual sequence.
Signed-off-by: Koji Matsuoka
Signed-off-by: LUU HOAI
[tomi.valkeinen: Rewrite the patch description]
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/rcar-du/Kconfig | 1
From: Koji Matsuoka
According to H/W manual, LVDCR0 register must be cleared bit by bit when
disabling LVDS.
Signed-off-by: Koji Matsuoka
Signed-off-by: LUU HOAI
[tomi.valkeinen: simplified the code a bit]
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/rcar-du/rcar_lvds.c | 27
The RCAR DSI driver uses reset controller, so we should select it in the
Kconfig.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/rcar-du/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig
index fd2c2eaee26b
On 09/01/2023 18:21, Aradhya Bhatia wrote:
Hi Angelo,
Thanks for taking a look at the patches!
On 03-Jan-23 17:21, AngeloGioacchino Del Regno wrote:
Il 03/01/23 07:46, Aradhya Bhatia ha scritto:
Dual-link LVDS interfaces have 2 links, with even pixels traveling on
one link, and odd pixels on
From: Tomi Valkeinen
Hi,
Here are some small rcar-du patches based on commits in the Renesas BSP
tree.
Tomi
Koji Matsuoka (2):
drm: rcar-du: lvds: Add reset control
drm: rcar-du: Fix LVDS stop sequence
Tomi Valkeinen (4):
drm: rcar-du: dsi: add 'select RESET_CONTROLLER'
dr
Hi,
On 03/01/2023 12:19, Rahul T R wrote:
Following series of patches adds supports for CDNS DSI
bridge on j721e.
v11:
- Wrap commmit messages at 72 chars
- Fix the order in Kconfig and Makefile
- Clean up the includes, move macros and some headers to .c file
- Add missing forward decla
On 26/12/2022 16:56, Laurent Pinchart wrote:
Hi Tomi,
(CC'ing Daniel and Dave)
On Wed, Dec 21, 2022 at 11:24:41AM +0200, Tomi Valkeinen wrote:
From: Tomi Valkeinen
Hi,
These add new pixel formats for Renesas V3U and V4H SoCs.
As the display pipeline is split between DRM and
On 05/01/2023 14:31, Dmitry Baryshkov wrote:
On 04/01/2023 11:05, Neil Armstrong wrote:
On 04/01/2023 08:29, Tomi Valkeinen wrote:
On 28/12/2022 23:58, Dmitry Baryshkov wrote:
On 02/11/2022 20:06, Dmitry Baryshkov wrote:
From all the drivers using drm_bridge_connector only iMX/dcss and
OMAP
lts
in calling bridge->funcs->hpd_enable() before the rest of the pipeline
was set up properly.
For the series:
Reviewed-by: Tomi Valkeinen
I've been using this series in my local branch for quite a while to fix
the HPD issues. Works for me.
I still think the "fix" aspect
V3U is actually gen 4 IP, like in V4H. Bump up V3U gen in the
rcar_du_r8a779a0_info.
Signed-off-by: Tomi Valkeinen
Reviewed-by: Kieran Bingham
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/rcar_du_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
Add XBGR2101010, ABGR2101010 and BGRA1010102 formats.
Signed-off-by: Tomi Valkeinen
---
.../userspace-api/media/v4l/pixfmt-rgb.rst| 194 ++
drivers/media/v4l2-core/v4l2-ioctl.c | 3 +
include/uapi/linux/videodev2.h| 3 +
3 files changed, 200
Add Y210, Y212 and Y216 formats.
Signed-off-by: Tomi Valkeinen
---
.../media/v4l/pixfmt-packed-yuv.rst | 49 ++-
drivers/media/v4l2-core/v4l2-ioctl.c | 3 ++
include/uapi/linux/videodev2.h| 8 +++
3 files changed, 58 insertions(+), 2
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